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There is a dual stack core in VHDL around. Ask in the FORTH group. Simon ========================================= On Mon, 29 Mar 1999 07:36:59 -0600, "Mark Rogers" <markr14@hotmail.com> wrote: >I am not all that excited about companies springing up just to sell IP cores >so they can make royalties off other peoples products. I am not really >against it either (it's a free country/part of the world), but I would hate >to see some company turn into a Microsoft of IP. I think it would be neat >if a shareware/open source movement started in IP (assuming it hasn't >already). > >Most engineers I know don't like embedding other peoples designs into there >own, and if they do, they always want to tweak it. If it is a hardware guy >taking some VHDL or a software guy taking a C routine, he (or she) will want >to modify it. That's what engineers do. > >Besides, I think some IP, like processor cores could benefit from 1000's of >people working on it around the world just as Linux has. > >I suspect that ultimately the IP industry will evolve until it very closely >matches the software industry. A few power house companies supplying the >bulk of the IP, weekenders and college students cranking out shareware IP, >and then some huge open source products being developed over the web. > >Anyway, food for though... > >Mark > > > > Simon - http://www.tefbbs.com/spacetime/index.htmlArticle: 15551
All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750, HI116, etc.). With FPGAs able to do process data at such high data rates, the difficulty now seems to get the data to the FPGA. Level translators are available on the market, but seriously complicate system timing especially if multiple chips must be used. Does anyone know of FPGAs with ECL-compatible inputs? Any plans to bring some to market in the near future? Alternatively, does anyone have any comments on their experience interfacing FPGAs to fast ADCs? Thanks in advance. =============================================== Pierre Langlois Département de mathématiques et informatique Collège militaire royal du Canada langlois-p@rmc.ca ===============================================Article: 15552
Steve Casselman wrote: > You can configure down to the bit level with the Virtex. > You just give it a frame with one bit different. You > should > be able to do this at runtime although it won't be > supported > by the M1 software. JBits might be able to handle it > thought. > http://w > w.xilinx.com/products/software/sx/sxpresso.html#JBITS > Steve is right. His is a more positive way of saying it. The new frame is shifted in without upsetting anything, then it is swapped in, in parallel. So you can change any desired number of bits in the frame, down to only one bit. But you have to perform this operation one frame at a time. Peter AlfkeArticle: 15553
There is a company called Dynachip that produces FPGA's with ECL I/O. They
run up to 500 MHz i think.
In general however, you should be getting away from ECL and going to LVTTL
type signalling. The Xilinx Virtix family supports a bunch of signalling
standards and their I/O run faster than 250MHz.
Sincerely
********************************************************************
Signal Processing in Hardware and Software
Pete Dudley
Sandia National Labs
Dept 2336 MS 0505
PO BOX 5800
Albuquerque, NM 87185
voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov
********************************************************************
Pierre Langlois <langlois-p@rmc.ca> wrote in message
news:3700F2A2.BE961AEC@rmc.ca...
> All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750,
> HI116, etc.).
>
> With FPGAs able to do process data at such high data rates, the
> difficulty now seems to get the data to the FPGA. Level translators are
> available on the market, but seriously complicate system timing
> especially if multiple chips must be used.
>
> Does anyone know of FPGAs with ECL-compatible inputs? Any plans to
> bring some to market in the near future?
>
> Alternatively, does anyone have any comments on their experience
> interfacing FPGAs to fast ADCs?
>
> Thanks in advance.
>
> ===============================================
> Pierre Langlois
> Département de mathématiques et informatique
> Collège militaire royal du Canada
> langlois-p@rmc.ca
> ===============================================
>
>
Article: 15554hi, i've worked with the spt7760 (1 gigasample per second with a 1:2 demux on the output). are there high-speed adc's available with lvttl i/o? the ones that i have seen have been all ecl. thanks, rk ___________________________________ Peter A Dudley wrote: > There is a company called Dynachip that produces FPGA's with ECL I/O. They > run up to 500 MHz i think. > > In general however, you should be getting away from ECL and going to LVTTL > type signalling. The Xilinx Virtix family supports a bunch of signalling > standards and their I/O run faster than 250MHz. > > Sincerely > > ******************************************************************** > Signal Processing in Hardware and Software > > Pete Dudley > Sandia National Labs > Dept 2336 MS 0505 > PO BOX 5800 > Albuquerque, NM 87185 > > voice: 505.844.5565 fax: 505.844.2925 email: padudle@sandia.gov > > ******************************************************************** > > Pierre Langlois <langlois-p@rmc.ca> wrote in message > news:3700F2A2.BE961AEC@rmc.ca... > > All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750, > > HI116, etc.). > > > > With FPGAs able to do process data at such high data rates, the > > difficulty now seems to get the data to the FPGA. Level translators are > > available on the market, but seriously complicate system timing > > especially if multiple chips must be used. > > > > Does anyone know of FPGAs with ECL-compatible inputs? Any plans to > > bring some to market in the near future? > > > > Alternatively, does anyone have any comments on their experience > > interfacing FPGAs to fast ADCs? > > > > Thanks in advance. > > > > =============================================== > > Pierre Langlois > > Département de mathématiques et informatique > > Collège militaire royal du Canada > > langlois-p@rmc.ca > > =============================================== > > > >Article: 15555
On Sun, 28 Mar 1999 19:33:22 GMT, Richard Guerin <guerin2@home.com> wrote: <snip> >So, I guess to answer your question, NO we don't pay for ASIC layout >tools .... it's rolled up into the price of the silicon. Rather, the Verily thou art a fortunate soul. However I would surmise that the cost goes on your bill for NRE as a service line item along with mask charges etc. rather than as a rider on part price. That is, unless you are a VERY valued customer, and then we are back to the "free tools and services for those who can best afford them" thread. Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 15556
On Mon, 29 Mar 1999 15:37:06 +0100, David Pashley <David@edasource.com> wrote: <after my four possible reasons> >None of these. Disagree. I think I got it pretty close... >The reason Xilinx bought NeoCAD was that from the perspective of the >market leader, a P&R tool which supported Actel, Altera, Lucent and >Xilinx, AND offered a virtually free of charge version which allowed you >to try out the different options, was rightly seen as a massive threat. Let's not forget dearly departed Motorola. Your analysis probably qualifies for my d), yes? I was being rather tongue-in-cheek with my original post. I did carry the AT&T/Lucent flag for a while, remember? >Also, the VC people were ready to sell up. Happens all the time. People want to make money, or stop losing money. Often in the EDA industry it can be a fine line between the two states. Often covered up by marketing hype and spin-doctors keeping the perception going while fervently trying to hide reality from prying eyes. Just watch after DAC. ;-) >OK, there was some mileage in c) above, but not $18m worth. Having seen some of the figures many pundits talk about in terms of the "value" of EDA companies that either went IPO or want to, I'd say Xilinx got a bargain by today's standards. If that was the real price. >Also, nobody "lived it up a little". NeoCAD was owned by VCs, not the >employees, many of whom were therefore negatively impacted by the >ensuing closedown. Somebody got the money, and I'm sure the founders made a few quid on the side. A number of employees found jobs with Xilinx and Lucent as I recall, but of course some people were hit. On the VC side, coming off Venture (or private) Capital is sometimes traumatic. It can kill a company when the marketeers who didn't have to worry about money suddenly have to start making it with the product they have at that moment. No more selling futures and BS. No more bombing prices to win business and keep the competition out. You stop giving away your product to gain ethereal "market share" and suddenly have to cut the high-brow ideas of wizzy products announced 12 months ago that half your company's engineers are still "working on". Of course, being assimilated by a greater entity could be an even worse fate, your technology broken down for the trophies considered desirable. ugh! But get it right, and you're a very rich man. That's the dream isn't it? >I wonder how the industry would have looked today with vendor- >independent P&R? I'd wager pretty much the same as it is today. The high volume users that keep the respective vendors in their orders of popularity would still have vendor independent synthesis and simulation. Hence, still picking the silicon that was right for the job. As we know, P&R tool availability is not an issue for companies who may spend tens of millions on FPGAs each year. It may be argued that smaller companies might benefit from buying a single P&R tool and a vendor independent schematic/synthesis/simulation capture package, but anyone who remembers the prices of NeoCAD might surmise that such a solution would likely cost more than a copy of every vendor's low-cost tools today. Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 15557
Dynachip (http://www.dyna.com/) offers FPGAs with ECL/PECL I/O. The older DL5000 can use single-ended ECL&PECL, the newer DY6000 can handle a number of single-ended or differential LV-PECL inputs (can do LVDS, too). Haven't tried these parts yet. As for using level translators with "normal" FPGAs, skew specs on modern parts are pretty good, for example the 100ELT23 (diff PECL to TTL) has 2 ns prop. delay typ., and specs 0.5 ns max part-to-part skew. It only guarantees 0.8-2.0V TTL swings up to 160 MHz, though. Agree that faster I/O on mainstream FPGAs would be nice. regards, Tom Pierre Langlois wrote: > > All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750, > HI116, etc.). > > With FPGAs able to do process data at such high data rates, the > difficulty now seems to get the data to the FPGA. Level translators are > available on the market, but seriously complicate system timing > especially if multiple chips must be used. > > Does anyone know of FPGAs with ECL-compatible inputs? Any plans to > bring some to market in the near future? > > Alternatively, does anyone have any comments on their experience > interfacing FPGAs to fast ADCs? > -- Tom BurgessArticle: 15558
> That is, unless you are a VERY valued customer, and then we are back > to the "free tools and services for those who can best afford them" > thread. You are right about that. Not only do I not pay for the tools because I work for a large company, but I pay very low prices for FPGAs/CPLDs (haven't done ASICs so I cant speak for those parts). This was really evident when my company bought another smaller company (by smaller, I mean only 2 billion in rev). There was a significant problem for the company X sales rep at the small company. As soon as we bought them they went under our contract prices with company X which were about 1/3 to 1/4 of what they were charging the small company before. This means that the small companies are paying for our free tools both in the cost of the tools themselves, and in the cost of the parts they purchase. But wait, it gets much worse, a couple of major FPGA vendors gave myself and a number of other engineers at my company free fully functional FPGA software to take home. VHDL, simulation, full licenses, free updates, the works. All I really care about though is the free lunch. I don't care if my company or the vendor pays for the tools. I know I am not paying for them. Of course, if I ever go independent, I will feel your pain. MarkArticle: 15559
In article <3700F2A2.BE961AEC@rmc.ca>, Pierre Langlois <langlois-p@rmc.ca> wrote: >All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750, >HI116, etc.). Analog Devices (http://www.analog.com) has some spiffy ADC's with faster clock speeds and non-ECL outputs. The AD9054-200 is spectacular: 200MHz, CMOS output, $31 last I checked. They have even more high-end ADC's with more bits or more converters, running at comparable speeds. With Analog Devices' progress, I see little need for ECL ADC's any more except at the extreme speed end. Alex Rast arast@inficom.comArticle: 15560
In article <3700F2A2.BE961AEC@rmc.ca>,
Pierre Langlois <langlois-p@rmc.ca> wrote:
>Alternatively, does anyone have any comments on their experience
>interfacing FPGAs to fast ADCs?
This problem is common enough that there are two parts which should exist:
An 8-channel 8-bit parallel to serial converter/TTL-ECL converter and an
8-channel 8-bit serial to parallel converter/ECL-TTL converter. Basically
these would either take 64 bits of TTL input and multiplex them for an 8-bit
ECL output at 8 times the input rate, or demultiplex an 8-bit ECL input to
64-bits of TTL output at 1/8 the input rate. The parts should have clock
dividers and synchronizers built in. The DEMUX should work at at least
500MHz so that they can be used with that Maxim 500MHz ADC and the MUX
should work at at least 1GHz so that it can be used with TRW DACs. These
chips would also be useful for applications like the AMD's optical taxi
chips.
The Brooktree Bt424 is a 4-channel 250MHz MUX version of the above, but as
far as I know there is no DEMUX. You can make the DEMUX in discrete ECL,
but you end up with something like 40 $15 chips and lots of heat.
Also, take a look at the AD9054: it is a cheap 200MHz 8-bit A/D (380MHz
input bandwidth) with a 2:1 demux built in giving 16-bits of 100MHz TTL
compatible outputs. I'm feeding this into an XC4013E-2 with no problem. My
main complaint with this chip is that you can not control the reference
ladder voltages (it's fixed for 1V pp signal around 2.5V), so automatic gain
control becomes a complicated issue (I'm using the 500MHz AD834 analog
multiplier to achieve this, no doubt at some loss to linearity and noise).
You could perhaps use two or more ADCs in parallel (perhaps fed by taps off
an analog delay line?), but it's expensive and messy :-(
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 15561Peter Alfke wrote: > There is no cross-over point. > All CMOS has dynamic power consumption = CfVsquared. > All conventional CPLDs add to this a substantial quiescent > current in their wiredAND read amplifiers ( Coolrunner > avoids that by using expensive multiplexers). > FPGAs have a only few milliamps ( or less ) for housekeeping > functions. > > So given the same voltage swing, internal capacitance and > activity, the dynamic power is identical, and the CPLD > always consumes more power due to the static component.. Peter, Pardon me for jumping in here, where perhapse I don't belong, but... If we're comparing FPGA's to CPLD's, wouldn't it be wrong to assume "the same internal capacitance and activity"? I would guess that because of the vastly different architecture we can't assume that the the same number of signals would be switching/second and that those signals have the same capacitance. David Kessner davidk@peakaudio.comArticle: 15562
Check out Aptix or Axis. Both use Altera parts, but in differnet ways. I think Aptix might be the closest thing to what DEC had (Although I've never heard of PAMette, and I've been in the industry for more years than I care to remember).Article: 15563
Can anyone tell me of any useful information on the net for creating a VB GUI, to program and interface with an FPGA. Preferably using the parallel port in EPP mode. The target device is a Xilinx 4020XL. I'm just a student , so don't be too technical, ThanksArticle: 15564
David Kessner wrote: > Peter Alfke wrote: > > > So given the same voltage swing, internal capacitance > and > > activity, the dynamic power is identical, and the CPLD > > always consumes more power due to the static component.. > > Peter, > > Pardon me for jumping in here, where perhapse I don't > belong, but... That's what we all do, it's ok > > > If we're comparing FPGA's to CPLD's, wouldn't it be wrong > to > assume "the same internal capacitance and activity"? > > I would guess that because of the vastly different > architecture > we can't assume that the the same number of signals would > be switching/second and that those signals have the same > capacitance. > Yes, you are right, and I tried to cover that with " apples vs oranges". For a particular design that is "CPLD-friendly" (whatever that means), there is probably such a cross-over. But that is not the general case. "Never say never". Peter AlfkeArticle: 15565
Mike Roberts wrote: just a few odds and ends ... sram vs. eeprom vs. antifuse is an interesting discussion ... but i'll stick to the odds and ends. :-) ------------------------------------------- > OTPs require socketing (expensive for high pin count devices) for > development and extra handling that adds to failures and consumes time. the sockets are not that expensive for development, i've gotten them for ~ $100 ea. (pqfp208) they do consume some "time" if they are not handled carefully or if they go in and out of the socket too many times or if you don't have a steady hand. handled carefully they work pretty well and no real reason, for most apps, to take them in and out. usually i'll just surface mount solder the parts down and be done with it though. also, what do you think about the pbga's? --------------------------------------------------------------- > You > can also consume tubes of parts (expensive parts) in the process. this one i haven't experienced. ----------------------------------------------------------------- > In > production, Anti-fuse devices have long programming times that make them > undesirable for large production runs. isn't that why they invented high-school kids? :-) i do low -> moderate volume, so i don't care. but the vendors offerred programming services that was pretty reasonable [hopefully not sweat shop labor like kathy lee gifford uses]. ------------------------------------------------------------------ > I think your are misunderstanding me. I don't want to see Anti-fuse fade > away, I just can't see a bright future. And I am not alone. TI didn't see a > brignt future -- they stopped 2nd sourcing Actel and sold resources to > Actel. just for a bit of humor, but didn't TI get out of the DRAM business too? -------------------------------------------------------------------- > Cypress didn't see a bright future -- they stop 2nd sourcing > Quicklogic. Anti-fuse devices, because of their speed, do have a market. If > the speed wasn't there, their market shrinks further. > If you have a non Hi-Rel application at memium to slow speed -- do you > choose on OTP device or a re-programmable part? This is where a majority of > the applications are and the reason SRAM based FPGAs are so popular. don't know, haven't costed 'em ... gate for gate+config mem, how do the costs stack up? [assuming you don't need to reconfigure]. i just caught a marketeering press release which made some claims about sales, although i didn't pay much attention, was just hitting the "what's new" button, and never did a one on one comparison. of course, as we've seen from other threads, your price might vary w/ volume, so i wouldn't be able to make the comparison (low volume). rkArticle: 15566
The Altera APEX series of FPGAs has LVTTL and LVCMOS IO support. The APEX E series (1.8V core) also supports a bunch of other IO signal levels, including LV Differential. Check your local Altera rep for info, availability of devices and development SW. http://www.altera.com/html/products/apex.html -- Bob Elkind Pierre Langlois wrote: > > All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750, > HI116, etc.). > > With FPGAs able to do process data at such high data rates, the > difficulty now seems to get the data to the FPGA. Level translators are > available on the market, but seriously complicate system timing > especially if multiple chips must be used. > > Does anyone know of FPGAs with ECL-compatible inputs? Any plans to > bring some to market in the near future? > > Alternatively, does anyone have any comments on their experience > interfacing FPGAs to fast ADCs? > > Thanks in advance. > > =============================================== > Pierre Langlois > Département de mathématiques et informatique > Collège militaire royal du Canada > langlois-p@rmc.ca > ===============================================Article: 15567
Stuart Clubb wrote: > > On Sun, 28 Mar 1999 19:33:22 GMT, Richard Guerin <guerin2@home.com> > wrote: > > <snip> > > > However I would surmise that the > cost goes on your bill for NRE as a service line item along with mask > charges etc. rather than as a rider on part price. You're 100% correct ... the aforementioned service(s) contribute a major component of the non recurring silicon cost.Article: 15568
I have recently been looking at this problem and have come across the
following devices. Not having used them I can not speak as to their
suitability or availability.
GIGA GD16333 4:32 demux
Fijitsu FMM4005EK 2:16 demux
Rockwell 5:64 demux ?????
www.rsc.rockwell.com/converters/tech_8-64.htm
Hope that this is of some help.
If you know of any other integrated solutions to this problem I would be
interested to know. In addition does any one know how fast the LVDS inputs
on the Altera 20KE are likely to work?
Stephen King
CRL
sking@crl.co.uk
Pierre Langlois wrote:
> All the fast (>100 MHz) ADCs I know of have ECL outputs (SPT 7750,
> HI116, etc.).
>
> With FPGAs able to do process data at such high data rates, the
> difficulty now seems to get the data to the FPGA. Level translators are
> available on the market, but seriously complicate system timing
> especially if multiple chips must be used.
>
> Does anyone know of FPGAs with ECL-compatible inputs? Any plans to
> bring some to market in the near future?
>
> Alternatively, does anyone have any comments on their experience
> interfacing FPGAs to fast ADCs?
>
> Thanks in advance.
>
> ===============================================
> Pierre Langlois
> Département de mathématiques et informatique
> Collège militaire royal du Canada
> langlois-p@rmc.ca
> ===============================================
Article: 15569I've almost got to the point of giving up trying to ask VCC for advice before our lab purchase some of their virtex virtual workbench development boards. Hopef ully someone here may be able to help me with the following The Virtual workbench is a stand alone board - does anyone know if cable to connect to the pc to download the configuration (sorry not too hot on the terminology - that's why we want the boards - to learn!) are supplied, or if not, why type needs to be purchased. I have also been advised that the foundation software should be one of the most appropriate for us to use - any comments on this? I certainly hope someone can help me as the funding we have has to be used very soon otherwise we lose it! Many thanks for any advice anyone can give Daryl BradleyArticle: 15570
Hi,all I want to know if MAX+PlusII 9.01(PLS-WEB version) supports Timing-driven compilation for MAX7xxx? Thanks. mike.Article: 15571
Peter Alfke wrote: > Steve Casselman wrote: > > > You can configure down to the bit level with the Virtex. > > You just give it a frame with one bit different. You > > should > > be able to do this at runtime although it won't be > > supported > > by the M1 software. JBits might be able to handle it > > thought. > > http://w > > w.xilinx.com/products/software/sx/sxpresso.html#JBITS > > > > Steve is right. His is a more positive way of saying it. > The new frame is shifted in without upsetting anything, then > it is swapped in, in parallel. So you can change any desired > number of bits in the frame, down to only one bit. > But you have to perform this operation one frame at a time. > > Peter Alfke Hi, I was wondering if such an operation requires the download of a whole frame to the Virtex ? It it is the case, this leads to a significant reconfiguration overhead , (a few hundred microseconds ) Am I right? Steven DerrienArticle: 15572
WildBeach <wildbeach@aol.com> wrote: : [...] (Although I've never heard of PAMette, and I've been in the : industry for more years than I care to remember). The PAM in PCI PAMette stands for "Programmable Active Memory". See: http://www.research.digital.com/SRC/pamette/ ...for glossy photograps of the hardware and other details. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Calm down - it's only zeros and ones.Article: 15573
In article <37011ccc.213181@nntp.netcruiser>, Stuart Clubb <s_clubb@NOSPAMnetcomuk.co.uk> writes >On Mon, 29 Mar 1999 15:37:06 +0100, David Pashley ><David@edasource.com> wrote: > <snip> >>I wonder how the industry would have looked today with vendor- >>independent P&R? > >I'd wager pretty much the same as it is today. The high volume users >that keep the respective vendors in their orders of popularity would >still have vendor independent synthesis and simulation. Hence, still >picking the silicon that was right for the job. As we know, P&R tool >availability is not an issue for companies who may spend tens of >millions on FPGAs each year. Do you really think so? Don't you find that even high-volume users are remarkably loyal to their chosen FPGA vendor, and that familiarity with the vendor environment plays a part in this? I believe that the FPGA vendors would have been less successful in creating this high level of brand-loyalty were they to have not sold their own tools. It's vital to the market-leaders to keep their products well-differentiated, as that means high margins. Contrast the situation where FPGAs might become a commodity that can be chosen after the design is done. > >It may be argued that smaller companies might benefit from buying a >single P&R tool and a vendor independent >schematic/synthesis/simulation capture package, but anyone who >remembers the prices of NeoCAD might surmise that such a solution >would likely cost more than a copy of every vendor's low-cost tools >today. > The pricing of NeoCAD was correctly set high for the early-adopter market. Naturally, it would have fallen dramatically as the vendor- independent market grew, and the Xilinx power-user opportunity (which is where 95% of actual NeoCAD sales happened) declined. DavidArticle: 15574
I'm looking for an affordable package for schematic capture, VHDL systhesis & FPGA systhesis. I work at home and do not have the resources of a large company. If any one can help me identify any sources please reply to the post or email: evansamuel@earthlink.net. Thanks, Evan Samuel
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