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In article <93k0v2$1sj8$1@news.cz.js.cn>, "Beyond Feng" <ef0025@sina.com> wrote: > Hi: > Could you tell me which group is focusing on IC, ASIC, FPGA or Digital > Circuit Design? > Thanks, > > Beyond > comp.arch.fpga comp.lang.verilog comp.lang.vhdl Best regards Tsvetan ---- PCB prototypes for $26 at http://run.to/pcb Sent via Deja.com http://www.deja.com/Article: 28401
I am in the first time to use FPGA Express. I wrote an Verilog HDL file and it can be compiled by Express. But I don't know how to simulate it. Can you give me some advice? ThanksArticle: 28402
In article <93kaj6$2v1v$1@news.cz.js.cn>, "Beyond Feng" <ef0025@sina.com> wrote: > I am in the first time to use FPGA Express. I wrote an Verilog HDL file and > it can be compiled by Express. But I don't know how to simulate it. Can you > give me some advice? Thanks > > FPGA Express is a synthesis tool not a simulator. You need a simulator, popular simulators are VCS, NC-SIM, Finsim, ModelTech. Sent via Deja.com http://www.deja.com/Article: 28403
Hi You will not be able to simulate your design with FPGA Express since it's a Synthesis tool, i.e. the tool compiles your HDL Code into gates. For simulation you need another tool (i.e. a simulator). There are various companys which sell simulators and of course you have to build a testbench around your HDL code to stimulate your design. This is a very short description. You should have a look at the Synopsys homepage for their products. Additionally you can have a look at e.g. the xilinx homepage. There you should find some explanations about typical design flows. Hope this helps Ansgar P.S: If any X's exist in my email address pls remove to reply. Beyond Feng <ef0025@sina.com> schrieb in im Newsbeitrag: 93kaj6$2v1v$1@news.cz.js.cn... > I am in the first time to use FPGA Express. I wrote an Verilog HDL file and > it can be compiled by Express. But I don't know how to simulate it. Can you > give me some advice? Thanks > >Article: 28404
Greetings, I have a verilog module that FPGA Express and Ambit can compile just fine. When I use XST in Foundation 3.3.06i XST hangs at 50%. I have let it run over night with no results. I am targeting Spartan II 2S200. While I muck about the code trying to get XST to finish the compile I thought I would ask if anybody has had a similar experience with XST and what they did to fix it. I'm thinking that some of the register lengths may be a bit much for the tool to handle. regards JerryArticle: 28405
Wolfgang Friedrich wrote: > Hello, > > Peter Alfke schrieb: > > > > I suggested a slight twist to this design: > > Same logic, but feed the XOR from the D-inputs of the binary counter, not their > > Q outputs. This way the binary and grey counters are "in step". > > Peter Alfke > > How do I get access to the D-inputs of the binary counter in VHDL? you have to seperate counter asynchronous logic and D-FFs by using an intermediate vector. This intermediate vector will go to Peter Alfke's suggestion. If necessary, you might have to design the binary counter in gate-level (handcrafty). UtkuArticle: 28406
hi all, Is there any harm from using the clock net to drive some ram address. ( one address wire for example toggle between 1 and zero), --Erika Sent via Deja.com http://www.deja.com/Article: 28407
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Hi, <br>I'm using a Block SelectRAM in a VirtexE Design. During the timing simulation with Synopsys VHDL Debugger (version 1999-10) I get the following warning: <p>Assertion WARNING at ... in design unit VPACKAGE from ... "Invalid ADDRESS: 0101010101. Memory contents will be set to 'X'." <p>The address, data, enable and write enbalbe signals are correct, but the simulation produces this assertion. I had a look at the SIMPRIM model of the BlockRAM. There is a function ADDR_IS_VALID, which checks for the validity of the argument. <p><font face="Courier New,Courier"><font size=-1> function ADDR_IS_VALID (</font></font> <br><font face="Courier New,Courier"><font size=-1> SLV : in std_logic_vector</font></font> <br><font face="Courier New,Courier"><font size=-1> ) return boolean is</font></font> <br><font face="Courier New,Courier"><font size=-1> </font></font> <br><font face="Courier New,Courier"><font size=-1> variable IS_VALID : boolean := TRUE;</font></font> <br><font face="Courier New,Courier"><font size=-1> </font></font> <br><font face="Courier New,Courier"><font size=-1> begin</font></font> <br><font face="Courier New,Courier"><font size=-1> for I in SLV'high downto SLV'low loop</font></font> <br><font face="Courier New,Courier"><font size=-1> if (SLV(I) /= '0' AND SLV(I) /= '1') then</font></font> <br><font face="Courier New,Courier"><font size=-1> IS_VALID := FALSE;</font></font> <br><font face="Courier New,Courier"><font size=-1> end if;</font></font> <br><font face="Courier New,Courier"><font size=-1> end loop;</font></font> <br><font face="Courier New,Courier"><font size=-1> return IS_VALID;</font></font> <br><font face="Courier New,Courier"><font size=-1> end ADDR_IS_VALID;</font></font> <p>The address (SLV) is "0101010101", but the function generates FALSE. Is it a bug in the simulation software? <br>Do you know this problem? <p>Thanks <br>Christian</html>Article: 28408
For the latest news about the WISHBONE System-on-chip (SoC) Interconnection Architecture for Portable IP Cores, see: http://www.opencores.org/press/pr_8jan2001.shtmlArticle: 28409
Any 4-bit counter is trivial, since 4-input LUTs allow us to create any of the 15! different possible counters, a humunous number of differnt designs, all at the same trivial cost. There isn't even a need nor a benefit of the carry structure. 16 to 24 bits is a much more interesting and fruitful area... Peter Alfke ================== "John L. Smith" wrote: > Here is some direct logic for a 4 bit Gray code counter: > > G0 <- !( G3 @ G2 @ G1 ) > G1 <- G0 !( G3 @ G2 ) + !G0 G1 > G2 <- !G3 G1 !G0 + G2 ( !G3 + !G1 + G0 ) > G3 <- G2 !G1 !G0 + G3 ( G2 + G1 + G0 ) > > ( + = or, @ = xor, ! = not, and is implied) > > Generally, the reflected code is logic intensive, > because _every_ bit depends _every_ other bit > (except G0 does not depend on itself!) > > Here's the reverse conversion as well: > > G(N) = B(N) > G[n] = B[n] @ B[n+1] B[n] = G[N] @ G[N-1] @ G[N-2] ... @ G[n] > (N = MS bit, n = any smaller bit) > > Kevin Neilson wrote: > > > > You are right that the design wouldn't work if you just read the > > unregistered XOR outputs in another domain. The second set of flops are > > required. That is, you clock the conventional counter and the Gray pipeline > > registers on clock A, and then you can read the Gray registers from domain > > B safely. The XOR outputs can glitch so they need to be registered. > > > > Eric Smith wrote in message ... > > >If you're using Gray counters because you have counters in two clock > > >domains (e.g., for a FIFO), doesn't implmenting them as binary counters > > >with converters defeat the purpose? With that implementation you can > > >have glitches where multiple bits change simultaneously. > > >Article: 28410
--------------674E81B0FE10E2CB432BC052 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit erika_uk@my-deja.com wrote: > hi all, > > Is there any harm from using the clock net to drive some ram address. ( > one address wire for example toggle between 1 and zero), > No, no harm. The address input doesn't know anything about the source of its signal. If you wiggle very fast, the power consumption may go up. But no real problem. What makes you even think so? Peter Alfke --------------674E81B0FE10E2CB432BC052 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>erika_uk@my-deja.com wrote: <blockquote TYPE=CITE>hi all, <p>Is there any harm from using the clock net to drive some ram address. ( <br>one address wire for example toggle between 1 and zero), <br><a href="http://www.deja.com/"></a> </blockquote> No, no harm. The address input doesn't know anything about the source of its signal. If you wiggle very fast, the power consumption may go up. But no real problem. What makes you even think so? <p>Peter Alfke <br> </html> --------------674E81B0FE10E2CB432BC052--Article: 28411
Dennis McCrohan wrote: <snip lotsa good comments> The reason I mentioned Yellow Dog Linux on a Mac is not to be argumentative, but to somewhat prove your point! While I'd imagine that going from RedHat to Debian to Mandrake, all on x86 boxes, should be reasonably easy (after all, aren't the major differences in the installation program and the included utilities?), going from x86 to PPC to SPARC to Alpha presents real problems. Clearly, Xilinx won't ship their tools in source form, so recompiling by the end user for a different platform is out of the question. Then again, I'm probably a masochist for wanting to run Linux on a Mac anyway. But it works, and I can run Mac-On-Linux (which runs Mac OS 9 as a Linux task!) and Photoshop doesn't seem to slow down. (Note to gimp partisans: Photoshop still beats the pants offa the gimp. Go away.) Next trick: intall Virtual PC on the Mac-On-Linux, and see if the Xilinx tools run there. ModelSim and Synplify both use dongles (which I vastly prefer over that FlexLM bogosity) but the Mac ain't got a parallel port so I'm SOL there. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28412
Wolfgang Friedrich wrote: > Hello, > > Peter Alfke schrieb: > > > > I suggested a slight twist to this design: > > Same logic, but feed the XOR from the D-inputs of the binary counter, not their > > Q outputs. This way the binary and grey counters are "in step". > > Peter Alfke > > How do I get access to the D-inputs of the binary counter in VHDL? > Well, on the chip these Ds are brought out on the X and Y outputs of the CLB or slice, whether you ask for it or not. So there clearly is no hardware obstacle. I leave it to the software wizards to figure out a way. Maybe create a specialized macro... BTW, somebody mentioned the loss of speed. I am looking at the next generation data sheet ( yes, you will have access to it very soon..) The additional delay going through an extra LUT is max 0.50 ns for the slowest speed grade, the set-up time is even less, and the clock-to-Q is max 0.48 ns for the slowest part. So the Grey counter will not be the speed-limiting part in a FIFO. 250 MHz, aiming for 300. I have not given up on building a 1 GHz frequency counter in XC2V40... Moore's Law is definitely still working for us. :-) Peter Alfke, Xilinx ApplicationsArticle: 28413
Andy Peters <"apeters <"@> n o a o [.] e d u> writes:
> to SPARC to Alpha presents real problems. Clearly, Xilinx won't ship
> their tools in source form, so recompiling by the end user for a
</sort of kidding mode on>
Maybe they should --- after all they are making money selling chips...
</sort of kidding mode off>
> Next trick: intall Virtual PC on the Mac-On-Linux, and see if the Xilinx
I started this tread and I failed to emphasize one of my points: I do
not want to run Windows under Linux. I would like to run the Xilinx
tools in a UNIX environment as I do today (on Solaris), but on a
faster/cheaper platform.
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com
#include <stdio.h>/* compile/run this program to get my email address */
int main(void) {printf ("petter\100gustad\056com\nmy opinions only\n");}
Article: 28414Greetings; I need to implement a small CRC function in an FPGA design I'm currently working on. I've scoured the net for information, and have read (and re-read) various articles: http://www.netrino.com/Connecting/2000-01/index.html by Michael Barr ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt by Ross Williams I've also generated the code I need using Jan Decaluwe's CRC tool (http://www.easics.com/webtools/crctool). I think I have a good understanding of CRCs, and I can work out examples on paper or follow the various software examples given. Where I'm stuck is in understanding how to go from the definition of the CRC to the requisite XOR statements, as seen in code generated by Jan's CRC tool. I would greatly appreciate a pointer to this information. While I could just use the code I have, I'd much rather understand how it was made. Thanks, JamieArticle: 28415
Wolfgang Friedrich wrote: > > Hello, > > Peter Alfke schrieb: > > > > I suggested a slight twist to this design: > > Same logic, but feed the XOR from the D-inputs of the binary counter, not their > > Q outputs. This way the binary and grey counters are "in step". > > Peter Alfke > > How do I get access to the D-inputs of the binary counter in VHDL? > describe the counter as a combinatorial increment function: count_d<=count+1; process(clk) if clk'event and clk='1' then count<=count_d; end if; -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28416
You forgot Aldec, which I think is one of the best values for the money. bjrosen wrote: > > In article <93kaj6$2v1v$1@news.cz.js.cn>, > "Beyond Feng" <ef0025@sina.com> wrote: > > I am in the first time to use FPGA Express. I wrote an Verilog HDL > file and > > it can be compiled by Express. But I don't know how to simulate it. > Can you > > give me some advice? Thanks > > > > > > FPGA Express is a synthesis tool not a simulator. You need a simulator, > popular simulators are VCS, NC-SIM, Finsim, ModelTech. > > Sent via Deja.com > http://www.deja.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28417
Jamie Sanderson wrote: > Greetings; > > I need to implement a small CRC function in an FPGA design I'm currently > working on. I've scoured the net for information, and have read (and > re-read) various articles: > > http://www.netrino.com/Connecting/2000-01/index.html by Michael Barr > ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt by Ross Williams > > I've also generated the code I need using Jan Decaluwe's CRC tool > (http://www.easics.com/webtools/crctool). > > I think I have a good understanding of CRCs, and I can work out examples on > paper or follow the various software examples given. Where I'm stuck is in > understanding how to go from the definition of the CRC to the requisite XOR > statements, as seen in code generated by Jan's CRC tool. I would greatly > appreciate a pointer to this information. While I could just use the code I > have, I'd much rather understand how it was made. > > Thanks, > JamieArticle: 28418
bjrosen <bjrosen@polybus.com> wrote in <93jj36$c4a$1@nnrp1.deja.com>: >Windows systems suffer from DLL hell, there is no >equivalent on Linux. When you install a new program on Linux you never >have to worry that it will stomp on some other program. On Windows you >have a 50/50 chance of mangling your system every time you install >something. Why does Windows suffer from DLL hell, but Linux doesn't? Both use shared libraries. When Windows apps install DLL's into the system directory, isn't it usually to deal with a prior shortcoming in Windows? Might we not see apps trying to do the same thing in Linux, installing their own updates to system libraries, like libc, gtk, or kde? (Experienced developers and admins won't allow this, but what about inexperienced developers coupled with ignorant users?)Article: 28419
Don't understand what your question is. Are you talking about how to code in HDL or how to find those polynomial? Jamie Sanderson wrote: > Greetings; > > I need to implement a small CRC function in an FPGA design I'm currently > working on. I've scoured the net for information, and have read (and > re-read) various articles: > > http://www.netrino.com/Connecting/2000-01/index.html by Michael Barr > ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt by Ross Williams > > I've also generated the code I need using Jan Decaluwe's CRC tool > (http://www.easics.com/webtools/crctool). > > I think I have a good understanding of CRCs, and I can work out examples on > paper or follow the various software examples given. Where I'm stuck is in > understanding how to go from the definition of the CRC to the requisite XOR > statements, as seen in code generated by Jan's CRC tool. I would greatly > appreciate a pointer to this information. While I could just use the code I > have, I'd much rather understand how it was made. > > Thanks, > JamieArticle: 28420
erika_uk@my-deja.com wrote: > > hi all, > > Is there any harm from using the clock net to drive some ram address. ( > one address wire for example toggle between 1 and zero), I'm not sure your logic will work the way you want it to if your clock is one of the address bits! -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28421
Bill Lenihan wrote: > > I know how to make binary up/down counters and LFSR-based counters in > verilog, but does anyone know of an algorithmic/equation-based way to > make grey-code counters? > > The only examples I've seen are from old PAL application notes, and they > are for 4-bit grey counters that are described as 16-state state > machines, which is ok if you are keeping the counter at 4-bits, but > impractical if you are going to much wider bit widths. What I'd like to see (and I think I suggested this to the Synplicity guys) is an attribute or something in the synthesis tool that lets you select gray-code or binary-code counters. That would be useful. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28422
In article <3A5D0A4F.F88B75E3@xilinx.com>, Peter Alfke <peter.alfke@xilinx.com> writes: > See the response by Dennis McCrohan. > He is not the official Xilinx spokesman, neither am I, but he brought up some > valid points. Quality assurance and support can be an enormous burden, that > must be weighed against the potential total benefit, i.e. additional chip > sales. It might be interesting to scan your list of bug reports and see how many are platform related. I've sent in 6 questions to support@xilinx since last Nov. None have been platform related. -- These are my opinions, not necessarily my employers. I hate spam.Article: 28423
thanks peter, i was just thinking if there is any negative points from routing the clk net through the non dedicated routing ressources In article <3A5DE811.C46239FF@xilinx.com>, peter.alfke@xilinx.com wrote: > > --------------674E81B0FE10E2CB432BC052 > Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x- mac-creator="4D4F5353" > Content-Transfer-Encoding: 7bit > > erika_uk@my-deja.com wrote: > > > hi all, > > > > Is there any harm from using the clock net to drive some ram address. ( > > one address wire for example toggle between 1 and zero), > > > > No, no harm. The address input doesn't know anything about the source of > its signal. If you wiggle very fast, the power consumption may go up. But > no real problem. What makes you even think so? > > Peter Alfke > > --------------674E81B0FE10E2CB432BC052 > Content-Type: text/html; charset=us-ascii > Content-Transfer-Encoding: 7bit > > <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> > <html> > > <p>erika_uk@my-deja.com wrote: > <blockquote TYPE=CITE>hi all, > <p>Is there any harm from using the clock net to drive some ram address. > ( > <br>one address wire for example toggle between 1 and zero), > <br><a href="http://www.deja.com/"></a> </blockquote> > No, no harm. The address input doesn't know anything about the source of > its signal. If you wiggle very fast, the power consumption may go up. But > no real problem. What makes you even think so? > <p>Peter Alfke > <br> </html> > > --------------674E81B0FE10E2CB432BC052-- > > Sent via Deja.com http://www.deja.com/Article: 28424
We are running into a diabolic JTAG failure with an XC95144XL-CS144 part. Just to give you the environment, the programming PC is a Windows NT 4.0, SP4 machine running Xilinx's Foundation 2.1i, SP6 software (a big POS, but that is another story) We are using the MultiLINX cable for programming (because our hardware also has an XCV300 in it). I configured the cable for serial port, 38,400 baud. The XC95144 chip sits on a card that plugs into the motherboard where our JTAG header is going. In any case, when I go to download a config into the chip, the JTAG prog S/W comes back with a message "...boundary-scan chain test failed at bit position '7' on instance '9500bas(Device1)'..." I have checked our device boards, made sure we're getting power to the CPLD, verified that the JTAG signal pins connect to the board carrying the XC95144, swapped boards, changed baud rates on the cable, and done pretty much everything Xlinx recommends in their appnotes on debugging JTAG problems, as well as as much testing of our own hardware as I can. If you look at the output of the cable with a scope, none of the JTAG lines ever see data on them. I'm suspicious we may have a bad cable, but are there other possibilities? Is there some oddball software incompatibility? Strange idisyncracies in the XC95144? Please reply to both e-mail addresses below. Alex Rast arast@inficom.com arast@qwest.net
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