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Peter Alfke wrote: > > Theoretically correct, > but in reality it depends on the complexity of the Grey-control logic. > In the design I am touting, there is actually a binary counter enclosed. > Bye-bye power saving. > > Peter Alfke > > Theron Hicks wrote: > > > Also, the switching noise may be substantially less as only one bit is changing > > at a time. > > But it could be a usefule technique if driving the address lines of a bank of external parrallel memory devices. Nial.Article: 28751
This is a multi-part message in MIME format. --------------1944BD390000634147542768 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all! Is the Virtex-II (1.5 volt core) cappable of being programmed with the xilinx MultiLINX cable (2.5 - 5 Volt spec)? Thank you all for your answers attn. Juan --------------1944BD390000634147542768 Content-Type: text/x-vcard; charset=us-ascii; name="jmrivas.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Juan M. Rivas Content-Disposition: attachment; filename="jmrivas.vcf" begin:vcard n:Rivas;Juan M. tel;home:(617)255-1268 tel;work:(617) 253-5097 x-mozilla-html:FALSE org:Media Lab, M.I.T.;Object Based Media version:2.1 email;internet:jmrivas@media.mit.edu title:Research Assistant adr;quoted-printable:;;20 Ames Street=0D=0A;Cambridge;Massachusetts;02139;U.S.A. fn:Juan M. Rivas end:vcard --------------1944BD390000634147542768--Article: 28752
<sulimma@my-deja.com> wrote in message news:94hqsc$s94$1@nnrp1.deja.com...
> Have a look at bresenhams line drawing algorithm.
>
> It solves the problem of counting n steps in m clock cycles with
> the best possible error and affordable hardware.
>
> e.g. if n and m are x bits, you need 2x LUTs
Interesting.
The error accumulation in Bresenham's, for dx > dy, is something like this:
e = 2*dy - dx;
_2dx = 2*dx;
_2dy = 2*dy;
while (dx-- > 0) {
if (e > 0) e -= _2dx;
e += _2dy;
}
I see that the inner loop can be done with two adders, e.g., 2x LUTs, e.g.:
e' = (e > 0) ? e - _2dx : e;
e = e' + _2dy;
and if you can sometimes tolerate two cycles per step (e.g. m > n), I think
the inner loop can also be done in Virtex in 1x LUTs:
e = sel ? (e - _2dx) : (e + _2dy)
which uses only 1 4-LUT per bit with an equation something like
o[i] = sel ? (e[i]^~_2dx[i]) : (e^_2dy[i])
and with MUXCY and XORCY configured appropriately.
The dx (n) downcounter is another x LUTs, or about 2+x/4 LUTs if you can use
an LFSR.
[Again, here are some Virtex adder configurations that I believe require
just one LUT per bit:
o = add ? a + b : a - b;
o = add ? a + b : c;
o = adder ? (addf1 ? a + b : a - b) : (addf1 ? f1(a,b) : f2(a,b));
o = addb ? a + b : a + c;
See also http://www.fpgacpu.org/log/nov00.html#001112]
Jan Gray, Gray Research LLC
Article: 28753Utku Ozcan wrote: > > Can I simulate a Verilog model of a RAMB4_S8_S8 element of > Virtex-E in a VHDL testbench? Not succeeded in that yet. > > RAMB4_S8_S8 is in $XILINX/verilog/src/unisims and this Verilog > code requires $XILINX/verilog/src/glbl.v to be compiled correctly. > > In typical Verilog testbench following must be done: > > glbl my_glbl (); > > In VHDL, its equivalent I can figure out would be: > > my_glbl : glbl; > > But when I choose "Design->Load Design..." and architecture > of VHDL testbench, Modelsim tells me that it cannot resolve > glbl in glbl.GSR assignment in RAMB4_S8_S8 element, although > I had compiled it into work library. > > The reason why I have use Verilog models of Xilinx macros instantiated > in VHDL testbench is that there are plenty of VHDL codes which call > Xilinx macros. > > VHDL models can be used by using: > > LIBRARY UNISIM; > USE UNISIM.all; > > ... which are not typed in original VHDL codes. But if I do it, then > Synplify will be angry with that, because it will try to compile > VHDL simulation models of Xilinx macros, which is nonsense. > > Is it possible to use LIBRARY and USE constructs with GENERATE?: > > IF SIMULATION=TRUE GENERATE > LIBRARY UNISIM; > USE UNISIM.all; > END IF; The easiest thing to do is to add a directive to your code. For Synplify, do the following: -- synthesis translate_off library unisim; use unisim.all; -- synthesis translate_on Voila. The synthesis tool will ignore the library clause and do the right thing, and the simulator will use the library and do the right thing. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 28754
They've probably been too busy getting ready for this Thursday's simulcast event. Surprised I haven't seen it mentioned in the NG. I don't work for them, so I hope I can [plug] http://www.xilinx.com/events/seminars/xtremedsp.htm coming to a theatre near you. Ray Andraka wrote: > > Anyone know why Xilinx isn't putting the recent copies of their XCell magazine > online? They've only got up through the 2nd Qtr 2000, and that's the way it has > been since around October. I can't imagine why they wouldn't want the extra > exposure by having it available online. (I have an article on digital > downconversion in Q4 I'd like to link to, several people have asked). > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 28755
Hi. I´have just got my jtag programmer functioning, and now I want to test something simple with it. I am completely new to programmable logic, so I need some info about how to connect it... I guess I will need a global clock, but what else will I need? All I want to do is get some led's blinking. My device is a xilinx XC9572 PC44.Article: 28756
Ray, I have opened a case internally to look into it. Nice article. Austin Ray Andraka wrote: > Anyone know why Xilinx isn't putting the recent copies of their XCell magazine > online? They've only got up through the 2nd Qtr 2000, and that's the way it has > been since around October. I can't imagine why they wouldn't want the extra > exposure by having it available online. (I have an article on digital > downconversion in Q4 I'd like to link to, several people have asked). > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 28757
Will be fixed next week. It sometimes helps to complain to the newsgroup. :-) Peter Alfke Ray Andraka wrote: > Anyone know why Xilinx isn't putting the recent copies of their XCell magazine > online? They've only got up through the 2nd Qtr 2000, and that's the way it has > been since around October. I can't imagine why they wouldn't want the extra > exposure by having it available online. (I have an article on digital > downconversion in Q4 I'd like to link to, several people have asked). > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 28758
Hello! As far as synthesis results go, which one of the latest versions of these products (Leo Spec 2000.1b or FPGA Express/Compiler II 3.5.6022) produces "better" results? I typically target Altera PLDs (MAX7000AE) and Xilinx 4000XL parts using mixed VHDL + schematics and was curious to see which tool might produce faster + smaller designs(from VHDL source). Is there an area in which one products excels vs. the other?(i.e. Leo does better Verilog synth vs. FPGA Xpr, etc.) Thanks! Vasant.Article: 28759
Hello all, I have a existing design that has been going through the design flow just fine for months. All of a sudden the placer and router scores went through the roof! To the point where my design won't compile. When I look at my UCF file with the Constraint's Editor I see a tab at the bottom called "Source Constraints". I click on that tab and look at the contents in the window. I see several TIMESPEC statements that I have not added and they are causing my design to not compile properly. the TIMESPECs added were things like PADS to PADS and PADS to FFS, etc. The values they are using are too fast. I do not know why this started and how to get rid of them. Some things in the design are not constrained and that is intended. It seems like the tools are trying to force 100% coverage by added these TIMESPECs??? I have all the most recent Service Patches installed. Any clues would be most appreciated. Thank you, Steve S&K ElectronicsArticle: 28760
kolja@prowokulta.org wrote: > > Austin Lesea <austin.lesea@xilinx.com> wrote: > > Kolja, > > > > Page 338 in the Virtex II handbook (datasheet) details stand alone > master > > select map with no cpld (just the flash memory, and the 2v part). > > Just to give you an example on why I will not use XC18V02: > > Insight/Memec Germany sells me small quantities of > > XC2S200 for DEM 60,- (about $28) > XC18V02 for DEM 68,- (about $32) > > It does not make much sense to double the price of the PFGA for > configuration. > > A XC9036XL plus AM28F040 kosts me DEM 15,- ($7) and is a factor of 5 > below the Xilinx PROM. It costs more board space, though. > > You really should start building FLASH based FPGAs. Actel claims they > take up less silicon area, anyway. I doubt it's possible to get flash in 0.15/0.12 um as use d by the Virtex-II -- Lasse (+)--------------------------(+) | Lasse Langwadt Christensen | | Aalborg, Denmark | (+)--------------------------(+)Article: 28761
Kevin Neilson schrieb: > [ Fas counter description] > This 32-bit counter takes 75 flops, but runs synchronously at at fantastic > speeds. You can do a 64-bit counter at the same speed. I How about using the SRL16?? Would save a lot of ressources?? -- MFG FalkArticle: 28762
Ayup! Opening a helpline case a few weeks ago did nothing. Newsgroup post... Thanks. Peter Alfke wrote: > > Will be fixed next week. > It sometimes helps to complain to the newsgroup. :-) > Peter Alfke > > Ray Andraka wrote: > > > Anyone know why Xilinx isn't putting the recent copies of their XCell magazine > > online? They've only got up through the 2nd Qtr 2000, and that's the way it has > > been since around October. I can't imagine why they wouldn't want the extra > > exposure by having it available online. (I have an article on digital > > downconversion in Q4 I'd like to link to, several people have asked). > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28763
Austin Lesea wrote: > > Ray, > > I have opened a case internally to look into it. Nice article. Thanks! > > Austin > > Ray Andraka wrote: > > > Anyone know why Xilinx isn't putting the recent copies of their XCell magazine > > online? They've only got up through the 2nd Qtr 2000, and that's the way it has > > been since around October. I can't imagine why they wouldn't want the extra > > exposure by having it available online. (I have an article on digital > > downconversion in Q4 I'd like to link to, several people have asked). > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28764
THis is a very sensitive issue for me. I've been asking Xilinx for 6 years now, "When will Xilinx support Linux?" The answers are always the same. 1. Well you know it's very difficult having all this support stuff, it costs money .... yada yada.... 2. The markets just not there .... 3. The best answer yet and the one that rings most true. " When Cisco "god" asks for it." Xilinx will support Linux when one of the following happens. 1. When Altera beats them to the market. 2. When god asks them. 3. When the user community makes such a STINK about the lack of innovation and forward thinking and quite frankly "F..K Y.U" attitude that they have no choice. I find that I can get by reasonably well running VMWARE and WIN4LIN. Perhaps the user community should press the issue by forming a coalition which has some power to make it's needs appreciated. Until then, will you guy's who work for god "Cisco" start rattling Xilinx corporate. Regards, CybinArticle: 28765
I design a schematics with Xilinx Foundation F1.5 for my diploma, where I want to have two IOPAD for one pin of Spartan XCS10 at different place of the schematic. Could I make this? Thank you! Latchezar Kostov Sent via Deja.com http://www.deja.com/Article: 28766
Lasse, Flash technology tends to lag about two years behind the standard CMOS process. Right now, 0.18u flash is just in the first process development stage, not sampling yet. We are actively examining all of the many ways one could provide configurations to our FPGA's. For large farms of our new parts, Flash Memory Cards may be the best answer for price/performance. Austin Lasse Langwadt Christensen wrote: > kolja@prowokulta.org wrote: > > > > Austin Lesea <austin.lesea@xilinx.com> wrote: > > > Kolja, > > > > > > Page 338 in the Virtex II handbook (datasheet) details stand alone > > master > > > select map with no cpld (just the flash memory, and the 2v part). > > > > Just to give you an example on why I will not use XC18V02: > > > > Insight/Memec Germany sells me small quantities of > > > > XC2S200 for DEM 60,- (about $28) > > XC18V02 for DEM 68,- (about $32) > > > > It does not make much sense to double the price of the PFGA for > > configuration. > > > > A XC9036XL plus AM28F040 kosts me DEM 15,- ($7) and is a factor of 5 > > below the Xilinx PROM. It costs more board space, though. > > > > You really should start building FLASH based FPGAs. Actel claims they > > take up less silicon area, anyway. > > I doubt it's possible to get flash in 0.15/0.12 um as use d by the > Virtex-II > > -- Lasse > (+)--------------------------(+) > | Lasse Langwadt Christensen | > | Aalborg, Denmark | > (+)--------------------------(+)Article: 28767
You haven't compared the clock-to-Qs of the flip-flops and SRL16's have you? Falk Brunner wrote: > > Kevin Neilson schrieb: > > > [ Fas counter description] > > > This 32-bit counter takes 75 flops, but runs synchronously at at fantastic > > speeds. You can do a 64-bit counter at the same speed. I > > How about using the SRL16?? Would save a lot of ressources?? > > -- > MFG > Falk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28768
I've got a page on my website that addresses multiplication for FPGAs. Might be a good place to start anyway. eric.levrault@mageos.com wrote: > > Hi, > > Can you help me ? > > I search a book or a note on different multiplier architecture !!! > > -- > Eric -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 28769
It is a *chicken and egg* issue. If they don't support Linux, not many people want to use the Linux version and if not many people are asking for Linux version, the company won't support it! cybin wrote: > THis is a very sensitive issue for me. I've been asking Xilinx for 6 > years now, "When will Xilinx support Linux?" The answers are always the > same. > > 1. Well you know it's very difficult having all this support stuff, it > costs money .... yada yada.... > 2. The markets just not there .... > 3. The best answer yet and the one that rings most true. " When Cisco > "god" asks for it." > > Xilinx will support Linux when one of the following happens. > > 1. When Altera beats them to the market. > 2. When god asks them. > 3. When the user community makes such a STINK about the lack of > innovation and forward thinking and quite frankly "F..K Y.U" attitude > that they have no choice. > > I find that I can get by reasonably well running VMWARE and WIN4LIN. > > Perhaps the user community should press the issue by forming a coalition > which has some power to make it's needs appreciated. Until then, will > you guy's who work for god "Cisco" start rattling Xilinx corporate. > > Regards, > > CybinArticle: 28770
I have instantiated the startup virtex block in one of my top level design, which has some other components instantiated. I have connected the toplevel reset to the startup virtex blocks input. Now to what pin or signal should i connect the reset ports of other components instantiated in my toplevel? Please give me the solution. Thanks in advanceArticle: 28771
I don't understand this obsession about weird counters ( well, maybe I do, been a culprit myself...) But carry logic at 35 ps per bit makes straightfroward binary counters so fast that alternatives are hardly meaningful. See "my" Gray counter. Its binary base runs at 300 MHz for 24 bits, 190 MHz for 64 bits ( in Virtex-II with conservative speeds files) Hanging the Gray converter onto the binary D-inputs increases the delay by a few 100 ps, not a big slow-down. Who wants to compete with that? BTW, I love SRL16s also. Peter Alfke ================================ Ray Andraka wrote: > You haven't compared the clock-to-Qs of the flip-flops and SRL16's have you? > > Falk Brunner wrote: > > > > Kevin Neilson schrieb: > > > > > [ Fas counter description] > > > > > This 32-bit counter takes 75 flops, but runs synchronously at at fantastic > > > speeds. You can do a 64-bit counter at the same speed. I > > > > How about using the SRL16?? Would save a lot of ressources?? > > > > -- > > MFG > > Falk > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 28772
Advice: Switch to Xilinx Le Mer Michel <michel.lemer@sta.fr> wrote in message news:93uecf$mcr$1@s1.read.news.oleane.net... > > <pineji@my-deja.com> a écrit dans le message : > 93t0n1$s6u$1@nnrp1.deja.com... > > In article <93n68n$c8v$1@s1.read.news.oleane.net>, > > "Le Mer Michel" <michel.lemer@sta.fr> wrote: > > > Hi > > > The exact message is : > > > # ** Warning: */APEX20k_ASYNCH_MEM SETUP High VIOLATION ON WADDR(1) > > WITH > > > RESPECT TO WE; > > > # Expected := 2.06 ns; Observed := 1.41 ns; At : 49989.401 ns > > > # Time: 49989401 ps Iteration: 4 Instance: > > > /test/i1/i1_ai3_ai2_ai1_alpm_ram_dp_component_asram_asegment_a0_a_a4_a > > /apexm > > > em > > > # ** Warning: */APEX20k_ASYNCH_MEM SETUP Low VIOLATION ON WADDR(0) > > WITH > > > RESPECT TO WE; > > > # Expected := 2.06 ns; Observed := 1.41 ns; At : 49989.401 ns > > > # Time: 49989401 ps Iteration: 4 Instance: > > > /test/i1/i1_ai3_ai2_ai1_alpm_ram_dp_component_asram_asegment_a0_a_a4_a > > /apexm > > > em > > > .... > > > > > > Michel Le Mer. > > > > > > S.K. Sharma <sanjay.kumar.sharma@philips.com> a écrit dans le > > message : > > > 93hoat$r9c$1@porthos.nl.uu.net... > > > > Hi Michel, > > > > Could you post the exact error message! > > > > Thanks > > > > Sanjay > > > > > > > > -- > > > > Sanjay Kumar Sharma > > > > ASIC Design Engineer > > > > Philips Semiconductors > > > > Eindhoven, The Netherlands > > > > "Le Mer Michel" <michel.lemer@sta.fr> wrote in message > > > > news:93c9gj$kk4$1@s1.read.news.oleane.net... > > > > > Hello > > > > > > > > > > I have a strange message about APEX20K_ timing violation during > > > simulation > > > > > despite I use the APEX 20KE family and that all the frequencies > > are met > > > > > according to Quartus. > > > > > > > > > > Any suggestions? > > > > > > > > > > Thanks > > > > > -- > > > > > Michel Le Mer immeuble Cerium > > > > > STA 12, square du Chene Germain > > > > > 02 23 20 04 72 35510 Cesson-Sevigne > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > With the small amount of information provided I'd venture to guess > > that you are using the built in SRAM in an asynchronous fashion. The > > static timing check should have yielded an error but did not either > > because a generated clock was not properly described to Quartus or the > > tool may just be incapable of detecting this error for this > > configuration. I would suggest using the SRAM in its synchonous > > configuration and generating the control signals for the synchronous > > SRAM with the same clock as the SRAM. > > > > Josh > > -- > > Altera FPGA Consulting- Not ACAP Affiliated > > > > > > Sent via Deja.com > > http://www.deja.com/ > > Hi > > I use a synchronous RAM and all the signals are synchronous. The source code > is generated with the Quartus Megawizard. The source code is below. As you > can see, everything is registered. > > Michel Le Mer. > > > -- megafunction wizard: %LPM_RAM_DP% > -- GENERATION: STANDARD > -- VERSION: WM1.0 > -- MODULE: lpm_ram_dp > > -- ============================================================ > -- File Name: position_ram.vhd > -- Megafunction Name(s): > -- lpm_ram_dp > -- ============================================================ > -- ************************************************************ > -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! > -- ************************************************************ > > > --Copyright (C) 1991-2000 Altera Corporation > --Any megafunction design, and related net list (encrypted or decrypted), > --support information, device programming or simulation file, and any other > --associated documentation or information provided by Altera or a partner > --under Altera's Megafunction Partnership Program may be used only to > --program PLD devices (but not masked PLD devices) from Altera. Any other > --use of such megafunction design, net list, support information, device > --programming or simulation file, or any other related documentation or > --information is prohibited for any other purpose, including, but not > --limited to modification, reverse engineering, de-compiling, or use with > --any other silicon devices, unless such use is explicitly licensed under > --a separate agreement with Altera or a megafunction partner. Title to > --the intellectual property, including patents, copyrights, trademarks, > --trade secrets, or maskworks, embodied in any such megafunction design, > --net list, support information, device programming or simulation file, or > --any other related documentation or information provided by Altera or a > --megafunction partner, remains with Altera, the megafunction partner, or > --their respective licensors. No other licenses, including any licenses > --needed under any third party's intellectual property, are provided herein. > > LIBRARY ieee; > USE ieee.std_logic_1164.all; > LIBRARY LPM; > USE LPM.lpm_components.all; > > ENTITY position_ram IS > PORT > ( > data : IN STD_LOGIC_VECTOR (6 DOWNTO 0); > wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0); > rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0); > wren : IN STD_LOGIC := '1'; > clock : IN STD_LOGIC ; > q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) > ); > END position_ram; > > > ARCHITECTURE SYN OF position_ram IS > > SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); > > > > COMPONENT lpm_ram_dp > GENERIC ( > lpm_width : NATURAL; > lpm_widthad : NATURAL; > lpm_indata : STRING; > lpm_wraddress_control : STRING; > lpm_rdaddress_control : STRING; > lpm_outdata : STRING; > lpm_file : STRING; > lpm_hint : STRING > ); > PORT ( > rdclock : IN STD_LOGIC ; > wren : IN STD_LOGIC ; > wrclock : IN STD_LOGIC ; > q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); > data : IN STD_LOGIC_VECTOR (6 DOWNTO 0); > rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0); > wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0) > ); > END COMPONENT; > > BEGIN > q <= sub_wire0(6 DOWNTO 0); > > lpm_ram_dp_component : lpm_ram_dp > GENERIC MAP ( > lpm_width => 7, > lpm_widthad => 5, > lpm_indata => "REGISTERED", > lpm_wraddress_control => "REGISTERED", > lpm_rdaddress_control => "REGISTERED", > lpm_outdata => "REGISTERED", > lpm_file => "D:/My_designs/LS_modulateur/horloge/src/position_ram.hex", > lpm_hint => "USE_EAB=ON" > ) > PORT MAP ( > rdclock => clock, > wren => wren, > wrclock => clock, > data => data, > rdaddress => rdaddress, > wraddress => wraddress, > q => sub_wire0 > ); > > > > END SYN; > > -- ============================================================ > -- CNX file retrieval info > -- ============================================================ > -- Retrieval info: PRIVATE: WidthData NUMERIC "7" > -- Retrieval info: PRIVATE: WidthAddr NUMERIC "5" > -- Retrieval info: PRIVATE: Clock NUMERIC "0" > -- Retrieval info: PRIVATE: rden NUMERIC "0" > -- Retrieval info: PRIVATE: REGdata NUMERIC "1" > -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" > -- Retrieval info: PRIVATE: REGwren NUMERIC "1" > -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" > -- Retrieval info: PRIVATE: REGrren NUMERIC "1" > -- Retrieval info: PRIVATE: REGq NUMERIC "1" > -- Retrieval info: PRIVATE: enable NUMERIC "0" > -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" > -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" > -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" > -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" > -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" > -- Retrieval info: PRIVATE: CLRq NUMERIC "0" > -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" > -- Retrieval info: PRIVATE: MIFfilename STRING > "D:\My_designs\LS_modulateur\horloge\src\position_ram.hex" > -- Retrieval info: PRIVATE: UseLCs NUMERIC "0" > -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" > -- Retrieval info: CONSTANT: LPM_WIDTHAD NUMERIC "5" > -- Retrieval info: CONSTANT: LPM_INDATA STRING "REGISTERED" > -- Retrieval info: CONSTANT: LPM_WRADDRESS_CONTROL STRING "REGISTERED" > -- Retrieval info: CONSTANT: LPM_RDADDRESS_CONTROL STRING "REGISTERED" > -- Retrieval info: CONSTANT: LPM_OUTDATA STRING "REGISTERED" > -- Retrieval info: CONSTANT: LPM_FILE STRING > "D:/My_designs/LS_modulateur/horloge/src/position_ram.hex" > -- Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON" > -- Retrieval info: USED_PORT: data 0 0 7 0 INPUT NODEFVAL data[6..0] > -- Retrieval info: USED_PORT: q 0 0 7 0 OUTPUT NODEFVAL q[6..0] > -- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL > wraddress[4..0] > -- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL > rdaddress[4..0] > -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren > -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock > -- Retrieval info: CONNECT: @data 0 0 7 0 data 0 0 7 0 > -- Retrieval info: CONNECT: q 0 0 7 0 @q 0 0 7 0 > -- Retrieval info: CONNECT: @wraddress 0 0 5 0 wraddress 0 0 5 0 > -- Retrieval info: CONNECT: @rdaddress 0 0 5 0 rdaddress 0 0 5 0 > -- Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0 > -- Retrieval info: CONNECT: @wrclock 0 0 0 0 clock 0 0 0 0 > -- Retrieval info: CONNECT: @rdclock 0 0 0 0 clock 0 0 0 0 > > >Article: 28773
The 4k and Spartan placer was good at placing pins. For Virtex and derivatives (including SpartanII) the recomendation is to do the pin placement yourself, but give it some thought. The chip will provide slightly better routing with a left to right data flow. Also, since the carry chains flow upward, arrange your data bus inputs with the LSB toward the bottom of the chip and MSB toward the top (left side of die). Jim Rick Filipkiewicz <rick@algor.co.uk> wrote in message news:3A64BAC7.13395DB6@algor.co.uk... > > > Ray Andraka wrote: > > > NO! > > > > There are a few things the automatic placement is exceptionally poor at, with > > pin placement leading the list, followed by tbuf placement, and data-path > > placement. You should always specify the pin placement rather than letting the > > tools do it. Even a bad guess is likely to be better than the random placement > > generated by the tools, especially if you start itrating a design. See earlier > > posts in this thread for some guidelines on assigning pins. > > > > As for number of pins used, 100% is not a problem...most of the designs I touch > > have 100% of the pins defined. The only time 100% pin utilization becomes a > > problem is when you let the tools do the assigning! > > > > Jakab Tanko wrote: > > > > > > NO, pins are better left to be picked by the place&route tool. > > > At minimum I think you should put together a dummy design, > > > if you don't have time for a detailed one, do a quick place and route > > > and go with that. As for the pins 100% is 20% to many used pins, I > > > would select a larger device or different package to get more I/O pins. > > > This is of course just my opinion and I could be wrong, > > > > > > jakab > > > > > Another consideration is that leaving the pin assignment to the P&R tools can lead > to a pinout that makes the PCB autorouter give up & die. Esp the case with the full > square FG devices e.g. FG676. > >Article: 28774
Your symptom also describes the case when the Parallel Cable driver wasn't loaded during your software install. You can download the WebPack JTAG programmer from the Xilinx website to correct this. Tomasz Nakielski <tnakiels@poland.com> wrote in message news:ee6f629.2@WebX.sUN8CHnE... > Hello. > > I have a problem with programming Virtex (XVC200PQ240) via > JTAG Parallel Cable III Model DLC5 and Programmer 3.3.06i. from one of my PC. > I receive message: "Communication with the cable could not be established". I have tried with all settings of Parallel Port (lpt 1). > On the other computer everything is OK (There is older version of Foundation). On both PC is Windows 98 SE so I think the Parallel Cable is OK. > > If someone knows what's wrong just write to me. > > Tomasz >
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