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ray@andraka.com (Ray Andraka) wrote in <398A231A.BFF1BCBB@andraka.com>: >All well and good for the average user. Here's a quick, opinionated response from the average user. ;) I tend to use the timing listed in the data book for a couple of things: 1. When I want to do a quick comparison between devices . . . an example is to get a feeling for just how much slower the -4 speed grade really is, or is a X2S-6 and a XCV-6 really similar? 2. Being a not expert user (yet), I often use it to decode the "detailed, complete and very accurate analysis" using the paper book. For example, when I'm looking at trce output, I can flip open the book, and see 'Tbeck' is the "setup time for the enable pin on a blockRAM". (And, related to #1, I can quickly see how much better TBeck is on the other flavours.) 3. I really like having things on paper. When the book's sitting on my desk, I know that at least most of what I'm likely to look for (Except package drawings!!!) is in the book. I don't have to search through subdirectory''s and whatnot. Admittedly, if I was better organised, that maybe wouldn't be so much of a problem, but . . . >Still for the expert, it helps to have >this information available in some form >that is easier to access than going into >the chip editor as an aid for >development of highly optimized blocks. Does the chip editor show you somewhere all of the timing parameters? Or do you have to do a trace on a net that uses the particular timing parameter you're looking for? If I could open the chip editor and see the different timing parameters for different pieces, without having to throw together a design first, I'd be happy. -KentArticle: 24326
Rick Filipkiewicz <rick@algor.co.uk> wrote: The notifier did the trick- thanks. > Stephen Lohning wrote: >> Yes create your self a small sdf file with the particular instances that are known >> to >> exibit async behaviour and change them to have 0 setup hold. >> Carry this out after your first annatotion has been done. If you have a lot of them >> you can even write a perl program to create the sdf for you. >> If you are really sensible you will append _Meta or something similar so you can >> find >> them all at one. If not it is just an iterative process to find all the async flops. >> >> Then go and give the designer/coders a big kick up the behind because on large >> design it makes verification really difficult. >> Stephen >> >> PS. This process works with NC-verilog > I'm guessing here but I assume that the X's are being triggered in the FF modules whan a > violation causes the notifier output of the timing checks to toggle. This is normally > used by a simulation model to set FF outputs to `X' where they will stay until the next > clock edge. Therefore the crudest trick is to disable the all notifiers. In Verilog-XL > type simulators there's a command line flag something like +no_notifier. The next level > is to turn them off in the FF's concerned by using a ``force'' statement in the top > level testbench: > initial begin > force <hierarch inst name>.notifier = 0; > end > I combine this with modifying the SDF to increase the delays on these FFs. The final > trick is to use a special model for async FFs. Its here that the various FPGA & ASIC > vendors need a kick up the !!! This situation is so common that they should provide such > models as a standard part of their sim libraries. Its a little tricky to do since such > a model has to behave normally until there's a violation. When there is one it should go > to `X' for a while and then randomly settle to 1 or 0. Its awkward since it breaks the > simple-minded SDF backannotation used in most model libs.Article: 24327
Hi- We are looking to have a CPLD on our board interface with a PPC processor over the 60x bus. This CPLD when all is said and done is around 600 flops. I tried squishing it down and the best I could do was 550 flops. The issue is I have been having a really difficult time finding a hard device that will be present at power up to fit into. I am not into these one time programmable chips because my IO count is high and will probably need a BGA package- and we cannot do those in house for debug. So Quicklogic is out. Altera and Cypress go up to 512 macrocells (Cypress has a new family in October but I am not going to risk it- and they are not so much CPLD as FPGA with embedded flash). Lattice has a 840 macrocell device but their software has been less than promising. They are supposed to give me a new version. Xilinx CPLD family is tiny. I have considered breaking this device up- but if I can get one device I will thrilled. It greatly increases my IO count board complexity. An FPGA with a boot prom does not seem to please the diag people very much- but I will work on them. Anyone lend any ideas here? Thanks, qwArticle: 24328
> Is there some whiz-bang approach that makes better sense than the obvious > one I've suggested ? Any thoughts on resource usage ? I don't know if this is a better idea than a look up table, but I've always used two counters which are setup to count down. The outputs are decoded and when the 1st counter hits all 0s, the lowest bit is active high, used to enable the 2nd counter and reset the 1st. The 2nd counter's outputs are decoded too and when it hits all 0s it's decoded output resets it or something like that(it's been awhile since I did this). Basically the 1st counter is used for the the PRI (frequency that the pulses come by) and the other for the pulse width. By controlling what values they count down from, you can control the PRI or pulse-width quite flexibly. This setup is analogous to using two "for loops," the outer loop controlling the rate that the pulses come and the inner controlling the pulse-width or how long the signal stays high from it's activation. In an FPGA I am not sure if a lookup table scheme or comparators or something else would work better or not... Thanks, Vasant. vasantr at utdallas . eduArticle: 24329
> > to how Austin Franklin feels about using Orcad ;) > > > > We are all wondering this. Austin, care to tell us how you feel without holding > anything back? :-) I have to hold back (and believe me I am)... Hell, I think Windows 3.1 was a better product, and a lot more functional...crashed about as much too... Do you know that OrCAD defaults its 'autosave' option to off....Article: 24330
Anyone have any Verilog code they'd be willing to share for a 'decent' multiplier? I am looking for something that can do a 24 x 24 multiply...it can take quite a few cycles, and it's for a Virtex architecture. I already have x <= a * b ; // ;-) Thanks!Article: 24331
Isn't it getting a little absurd for Innoveda to perpetuate this farce? I guess the OEM version thing is really just a way to get people to try their software on a shareware basis. Then they have to pony up a few grand to use it for real projects. If you are willing to put up with the BS of copying the K lines, you can use the OEM thing as much as you want. But if you want to do real work even just with FPGAs, you need to buy the full license seat to be compatible with others using full license seats. It may be good marketing, but it sucks for the users! Don Husby wrote: > > Philip Freidin <philip@fliptronics.com> wrote: > > Which would work only if you knew how to generate the security number > > on the K line. I have no idea how to calculate it. > > Last time I checked, you could give every file the same K-line since > Viewlogic no longer checks the name on the K-line against the file name. > > Your post-processor can simply overwrite the existing K-line with a > known valid one. It's probably best to comment-out the old one in case > you need it later. > > -- > Don Husby <husby@fnal.gov> http://www-ese.fnal.gov/people/husby > Fermi National Accelerator Lab Phone: 630-840-3668 > Batavia, IL 60510 Fax: 630-840-5406 -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24332
What's all this "AC parameters" stuff, anyhow? I would appreciate it if you continued to publish the timings for the various functional blocks. In fact there are some missing that I would like to see added or put back (and don't ask me which since I have not done a Xilinx design in a year or more). I expect to be doing some Spartan II designs later this year and I will be very happy to tell you exactly what you did wrong with the data sheet then :) In general, when I am looking at doing a tricky design, I like to work on paper with blocks I can push around (or better a whiteboard). This is much complicated by the lack of routing info, but it does not stop me from waving hands and thinking. The lack of AC timing data stops me completely. Is there a simple way to get info from the tools without having a design of some kind? I think the bottom line is that the tools are not so easy to use outside of an actual design effort. If a simple tool could be used to construct a simple test case and let the tools analyze it, that might work OK. But you still can't do it on a whiteboard! Why couldn't Bob Pease be a digital designer??? Peter Alfke wrote: ...snip... > How would you react if we reduced the published on-chip delay > parameters to a limited number of relevant performance values, and > then referred you to the software tool for the detailed, complete > and very accurate analysis ? > Wouldn't you be better off ? This entirely depends on which data you take out and which you keep. I seem to recall that it is a little harder now to determine the delay through a carry chain than it used to be, but I am not sure of that. I vote for more data rather than less. > This was triggered by the recent debate over the delay differences > between the 4 different LUT inputs. I feel strongly that the > designers should not be bothered with such details. The software > should analyze and synthesize this for you. I thought that discussion was for an Altera part and not a Xilinx one. If this was an issue for Xilinx parts, I would love to see that timing data in the data book. I don't know if you can control the input used in any of the Xilinx tools. But if there is a difference in timing it would be nice to know about and control. Software taking control is nice if you can truly depend on it. But I do not trust software to look out for my interests any more than I do the government. > This is Peter speaking. It is not an official Xilinx proposal. > It is also not an attempt to save cost and paper, although it would > do that as a side benefit. > > It is just a fresh look at a 40-year old habit. > Every couple of dozen years one should clean out the closet :-) > > Please let me know what you think. > I know I can count on your opinionated response ! > > Peter Alfke > > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24333
qwerty@scottfamily.cc wrote: > > Hi- > We are looking to have a CPLD on our board interface with a PPC processor > over the 60x bus. This CPLD when all is said and done is around 600 flops. > > I tried squishing it down and the best I could do was 550 flops. The issue > is I have been having a really difficult time finding a hard device that will > be present at power up to fit into. I am not into these one time programmable > chips because my IO count is high and will probably need a BGA package- and we > cannot do those in house for debug. So Quicklogic is out. Altera and Cypress > go up to 512 macrocells (Cypress has a new family in October but I am not > going to risk it- and they are not so much CPLD as FPGA with embedded flash). > Lattice has a 840 macrocell device but their software has > been less than promising. They are supposed to give me a new version. Xilinx > CPLD family is tiny. > > I have considered breaking this device up- but if I can get one device I will > thrilled. It greatly increases my IO count board complexity. An FPGA with > a boot prom does not seem to please the diag people > very much- but I will work on them. > > Anyone lend any ideas here? > > Thanks, > qw I am not clear on what the issues with the "diag people" are. An FPGA sounds like just what you need to me. You can have it loaded at power up by using one of the outputs from the FPGA (perhaps LDC, Low During Configuration) hold the rest of the board in reset until the chip is loaded. The power on reset holds the FPGA PROG- low until the power is stable. Then when the chip has loaded itself, the rest of the board powers up and you are off and running! -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24334
Austin Franklin wrote: > > > > to how Austin Franklin feels about using Orcad ;) > > > > > > > We are all wondering this. Austin, care to tell us how you feel without > holding > > anything back? :-) > > I have to hold back (and believe me I am)... Hell, I think Windows 3.1 was > a better product, and a lot more functional...crashed about as much too... > > Do you know that OrCAD defaults its 'autosave' option to off.... Sounds like a personal problem to me. Go see the chaplain! ;) I am no fan of Orcad after using their Express product for FPGA non-design. That was about a month before I started using Foundation instead. And it took me 3 weeks to get the approval! -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24335
George Pontis wrote: > > Hello FPGA users, > > Can someone suggest a good approach for implementing PWM modulation in a > Spartan-XL FPGA ? The goal is to generate a 200KHz carrier with 10KHz > PWM; the input clock at 40MHz should be ample. The output will be aplied > to a half-H power driver and filtered. I also need to be able to control > the amplitude of the 10KHz component at a slow rate. > > My thought for a possible approach is to build a small lookup table in a > dual-port RAM block. An external CPU would compute the pulse widths > appropriate for the desired 10KHz amplitude, then download the table into > FPGA RAM. Then FPGA hardware cycles through the table, generating pulses > of the appropriate width every 5us. A table of 20 entries with even 4 bit > resolution seems reasonable. > > Is there some whiz-bang approach that makes better sense than the obvious > one I've suggested ? Any thoughts on resource usage ? What you describe makes perfect sense as long as your assumptions (the numbers) are correct. The 4 bit resolution does not sound right to me though. I believe this is the range of the counter (loaded from the RAM) that time the 200 KHz pulse widths. With a 40 MHz master clock, you can have pulse widths from 0 to 200 counts. So you need 8 bits of resolution. If you don't need to use the full range of counter values, then I guess 4 bits might be enough. But you may need to add an offset to each value if you want a voltage range centered signal. It might be just as easy to use an 8 bit value and let the software put the range where ever you want it. The resolution may be important if you are slowly varying the 10 KHz signal. The counter resolution will limit the fineness of the amplitude steps. Since this can not be filtered, you may see distinct steps in the amplitude of the 10 KHz signal as it is slowly varied. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24336
Xilinx Synthesis Technology? I know they use this to synthesize netlists from VHDL and Verilog in their WebPACK tools. peter dudley wrote: > I saw a reference to XST in an earlier post. Could someone please explain to > me what is XST? > > I'm running Xilinx 2.1i software and I've never heard of XST. > > Thanks, > > -- > Pete Dudley > > Arroyo Grande Systems -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 24337
Hi all, Could someone direct me to some hardware (PCI card?) that can do Sparse Matrix x Vector multiplication REALLY FAST? Thanks, Frank Tripp frank_tripp@hotmail.comArticle: 24338
Hi Guys I will be attending interview for ASIC designer position. Can someone tell me what sort of technical questions are asked. Tricky questions etc . Yitzak ----------------------------------------------------------- Got questions? Get answers over the phone at Keen.com. Up to 100 minutes free! http://www.keen.comArticle: 24339
> This was triggered by the recent debate over the delay differences > between the 4 different LUT inputs. I feel strongly that the > designers should not be bothered with such details. The software > should analyze and synthesize this for you. Software has a long history of not being smart enough to do the right thing. So independent of whether the numbers are in the data sheet or we have to get them from a tool, I think it's important for the designer to understand the low level issues AND for there to be some path to make the software do what the designer wants when he is smarter than the software. Perhaps that represents a flaw in my approach, but I always seem to get involved in the parts of the design that are right on the edge. I'm talking about simple chunks of logic that people can do by hand, not large complicated problems that are too big for a person to work on. -- These are my opinions, not necessarily my employers. I hate spam.Article: 24340
Thanks for bringing up an interesting issue.
> What benefit is there in publishing a select subset of these values
> in the data sheet, necessarily excluding most routing delays ?
...
Perhaps what's needed is useful timing specs that do include routing
delays. What the designer wants to know is how fast a circuit will
run. How about specs for things like:
16 bit counter. (and 8 and 32...)
moving data from one column to another via tbufs and long lines.
getting data from one CLB through N levels of logic to another CLB.
getting data across chip (or N columns) via local routing.
and other directions too?
something for RAMs - assuming good placement ???
I guess what I'm suggesting is a handful of "typical" things
that designers will want to do. I'm assuming clean but useful
designs.
Then if I know I want to run the clock at x ns, I can see
what tools are available and/or see how close to the edge
I'm getting. If I'm real close, I'll expect troubles
and/or the software to take longer to find a solution.
Perhaps we need both bleeding edge numbers and sane/normal ones.
I don't have a good example, but, say, if there is only one
particular routing that will get the spec then I'd like a warning
about that or another number that will be easier to meet.
For extra credit, publish the high level source code that
can be used to extract the timing info from a chip. :)
--
These are my opinions, not necessarily my employers. I hate spam.
Article: 24341Hi From what I've heard, Xilinx plans to give it to their customers. Maybe it's bundled with 3.1? I had a chance to try it. It's a bit better than FPGA Express (and it's much faster) but it had some problems with parameters. Since it was under development, I suppose it's been fixed. Dave Vanden Bout a écrit : > > Xilinx Synthesis Technology? I know they use this to synthesize > netlists from VHDL and Verilog in their WebPACK tools. > > peter dudley wrote: > > > I saw a reference to XST in an earlier post. Could someone please > > explain to me what is XST? > > > > I'm running Xilinx 2.1i software and I've never heard of XST. > > > > Thanks, -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 24342
> Anyone have any Verilog code they'd be willing to share for a 'decent' > multiplier? I am looking for something that can do a 24 x 24 multiply...it > can take quite a few cycles, and it's for a Virtex architecture. Have you tried Coregen? No source, but it sounds like it's the result that matters to you.. Opinions expressed here are probably not shared by my employer, etc.. /Bye, TorbjörnArticle: 24343
<the original post isn't on my server, so this is probably in the wrong place...> My vote is to keep the detailed specs on paper somewhere, though not necessarily on the data sheet. It's too difficult to use the tools to get detailed info before starting a design. I'd be happy to see less information on the real datasheet, but it would have to be more usable. Remember the old advice that used to appear here regularly - "50% CLB, 50% routing"? Ok, this is far too inaccurate to put on a datasheet, or anywhere else, but at least it had the merit that you could get a first approximation to how fast your block would go. The main factor that originally stopped me from using Xilinx devices was that I couldn't get any feel for how fast they were by reading the datasheet. Perhaps you could come up with a better way to estimate relative CLB and routing ratios - maybe a datasheet section giving some typical routing delays for tracks of various lengths and fanouts, and then a subset of the CLB and IOB delays. Have a look at Lattice's old 1000-series datasheets (they may still be the same - I've only got the '94 databook). It's not directly applicable, of course, since the architecture is different and the routing is more deterministic, but the idea is nice - a block diagram including CLB and IOB elements, and some potential ways to join them up, referencing some delay and typical routing parameters. This would give new (and old) users a really nice way to get a feel for a block before starting the design. EvanArticle: 24344
On Fri, 04 Aug 2000 00:51:56 -0400, Dave Vanden Bout <devb@xess.com> wrote: >Xilinx Synthesis Technology? I know they use this to synthesize netlists from >VHDL and Verilog in their WebPACK tools. I hadn't realised it was used on Webpack, but it comes with 3.1. I don't know if it's priced separately or if it's a freebie. It's the old Minc synthesiser, acquired (I think) along with the Synario stuff a year or two ago, which is all re-appearing in 3.1, after some development. I've only seen a demo, so I've got no real details, but the project manager front-end will look very familiar to anyone who's used Synario or the later Abels. I think the Synario schematic capture tool is also included in the Project Manager, but I didn't see it. EvanArticle: 24345
John Chambers writes: > > I need to interface a Lattice 1032E to a 3.3V processor. I know I could > buy a 3.3V part but I happen to have a 5V device. I've measured the pin > output voltage of the 5V part and it never goes above 3.3V. Has anyone > tried a 5V/3.3V interface with a 5V Lattice CPLD? > > John There is no problem to drive the 1032E with 3.3V, because this is still TTL-Level! The question is, can the 3.3V-device handle the 5V from the 1032E. If not, use Quickswitches to translate! We have the combination Motorola MPC68360 (QUICC,3.3V but 5V-tolerant) and 1032E-70LT (5V). The 1032E has a measured voltage of 4.2V. Helmut -- ==================================================== Dipl.Ing. Helmut Juchems DATUS AG Phone: +49-241-16802-0 Hardware-Development Fax: +49-241-16802-80 Tempelhoferstr. 4-8 EMail: hj@datus.com D-52068 Aachen WWW: http://www.datus.com Germany ====================================================Article: 24346
Hi, In time being, i can't take a look on them. but may be in future, i have to work on XESS board. will you remove this material from the web. also, is the XESS board powerful, or is it just used for student initiation, sort of training for the beginners Regards --Erika In article <39896091.E1BDB2C0@xess.com>, Dave Vanden Bout <devb@xess.com> wrote: > XESS Corp. is releasing the sixth section of its "myCSoC" tutorial for > free downloading at http://www.xess.com/myCSoC-CDROM.html. We will > release a new section each week. > > Each section describes a design example for the Triscend configurable > system-on-chip device (CSoC). The Triscend TE505 CSoC integrates an > 8051 microcontroller core with a programmable logic array to create a > chip whose software and hardware are both reprogrammable. The tutorial > examples show how the Triscend FastChip development software is used to > configure the TE505's programmable logic into peripheral functions that > cooperate with the microcontroller core. > > -- > || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || > || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || > || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24347
altera... In article <39885819.A5F7A46D@fliptronics.com>, Philip Freidin <philip@fliptronics.com> wrote: > > > Jamil Khatib wrote: > > Could you please suggest me the best FPGA to use that has minimum price, > > maximum logic gates and provides maximum FIFO memory buffer. > > Jamil Khatib > > Xilinx. > Xilinx Spartan and Spartan-II > Xilinx Virtex > Xilinx Virtex-E > Xilinx. > > I am not biassed, really. > > -- > Philip Freidin > > Mindspring that acquired Earthlink that acquired Netcom has > decided to kill off all Shell accounts, including mine. > > My new primary email address is philip@fliptronics.com > > I'm sure the inconvenience to you will be less than it is for me. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24348
x o r m
x w s
x o r
x_______w__ m
| | s
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|___________|
How will we spot the synthesis and timing analyser bugs if we don't have
the fundamental data to check results :o?
As a sad old seat of the pantser I welcome detailed timing, from the
planning stage, to pushing the speed envelope and in checking the
results of sometimes appalling synthesis - the relative infancy of these
(VHDL) tools leaves me with limited trust of their capabilities in
difficult imps.
However, could you take an ac parameter spec and mark it up with the
changes you are considering - an unprotected pdf maybe with strikethro's
on what you would consider leaving out & put it up for comment.
Having just read thro' ac params in my data book, I wouldn't want to see
it much lighter.
thanks,
Dave
dmac
remove the obvious for email reply
Article: 24349I've made my opinions known here many times regarding suitability of Altera vs Xilinx for DSP applications. Xilinx is a hands down winner there due to a more capable carry chain and the ability to implement compact delay queues. karenwlead@my-deja.com wrote: > > altera... > In article <39885819.A5F7A46D@fliptronics.com>, > Philip Freidin <philip@fliptronics.com> wrote: > > > > > > Jamil Khatib wrote: > > > Could you please suggest me the best FPGA to use that has minimum > price, > > > maximum logic gates and provides maximum FIFO memory buffer. > > > Jamil Khatib > > > > Xilinx. > > Xilinx Spartan and Spartan-II > > Xilinx Virtex > > Xilinx Virtex-E > > Xilinx. > > > > I am not biassed, really. > > > > -- > > Philip Freidin > > > > Mindspring that acquired Earthlink that acquired Netcom has > > decided to kill off all Shell accounts, including mine. > > > > My new primary email address is philip@fliptronics.com > > > > I'm sure the inconvenience to you will be less than it is for me. > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
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