Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Depending on the actual device, at speed greater than 50Mhz, FPGAs start approaching CPLDs and I have seen data that over 100Mhz some CPLDs actually consume less current. There is a cross-over point. Mike Peter <z80@ds2.com> wrote in message news:37032252.1109691361@news.netcomuk.co.uk... > This is true but generally you need to run a FPGA very fast indeed to > get its dynamic Icc to approach the static Icc of a similar size CPLD. > > >If you take the quiescent > >(static) current away and compare FPGAs and CPLDs, you will see that they > >are comparable for the same gate count at the same frequency. > > > -- > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but remove the X and the Y. > Please do NOT copy usenet posts to email - it is NOT necessary.Article: 15526
Stuart Clubb <s_clubb@NOSPAMnetcomuk.co.uk> wrote: > c) An attempt to access a technology that was seen as superior to that > in house at the time. (Why M1 instead of XACT7.0?) What is the story with that anyway? The software looks like what it is doing is more intelligent, but ... I had some designs in an XC4010-5, which I needed to retarget to 4013E-4. I changed the libraries over, route with M1.4 and the design doesn't run up to speed. I re-route the original design on XACT 5.2 for 4013E-4 and it runs fine? Odd. Hamish -- Hamish Moffatt Mobile: +61 412 011 176 hamish@rising.com.au Rising Software Australia Pty. Ltd. Developers of music education software including Auralia & Musition. 31 Elmhurst Road, Blackburn, Victoria Australia, 3130 Phone: +61 3 9894 4788 Fax: +61 3 9894 3362 USA Toll Free: 1-888-667-7839 Internet: http://www.rising.com.au/Article: 15527
I am not all that excited about companies springing up just to sell IP cores so they can make royalties off other peoples products. I am not really against it either (it's a free country/part of the world), but I would hate to see some company turn into a Microsoft of IP. I think it would be neat if a shareware/open source movement started in IP (assuming it hasn't already). Most engineers I know don't like embedding other peoples designs into there own, and if they do, they always want to tweak it. If it is a hardware guy taking some VHDL or a software guy taking a C routine, he (or she) will want to modify it. That's what engineers do. Besides, I think some IP, like processor cores could benefit from 1000's of people working on it around the world just as Linux has. I suspect that ultimately the IP industry will evolve until it very closely matches the software industry. A few power house companies supplying the bulk of the IP, weekenders and college students cranking out shareware IP, and then some huge open source products being developed over the web. Anyway, food for though... MarkArticle: 15528
Hello, Has anyone successfully implemented a neural network in Xilinx 4000/6000 FPGA's , or does anyone know where to find more information ? Thanx.Article: 15529
I want use Xchecker to download program into Xilinx (serial cable), and with the same interface, exchange data with the computer (like Terminal into Windows). Then, I search plan about the xilinx serial download cable. Thanks mail to herve.echelard@wanadoo.frArticle: 15530
In article <36fe724f.179207@nntp.netcruiser>, Stuart Clubb <s_clubb@NOSPAMnetcomuk.co.uk> writes > >Then you can get bought by Xilinx for a chunk of money and live it up >a little! Was the real reason(s) Xilinx paid money for NeoCAD: > >a) An incompetent financial decision by Xilinx management who paid way >over the worth for a "no way to make money" company and technology. > >b) A philanthropic gesture as part of Xilinx charity to lost causes. > >c) An attempt to access a technology that was seen as superior to that >in house at the time. (Why M1 instead of XACT7.0?) > >d) A direct attack upon other competing FPGA vendors supported solely >by NeoCAD software, in order to destroy their P&R capability, and thus >place uncertainty and doubt in the market place (even if some of them >had legal rights to code etc.) > >My money would be on b) right? (insert tongue in cheek now). > None of these. The reason Xilinx bought NeoCAD was that from the perspective of the market leader, a P&R tool which supported Actel, Altera, Lucent and Xilinx, AND offered a virtually free of charge version which allowed you to try out the different options, was rightly seen as a massive threat. Also, the VC people were ready to sell up. OK, there was some mileage in c) above, but not $18m worth. Also, nobody "lived it up a little". NeoCAD was owned by VCs, not the employees, many of whom were therefore negatively impacted by the ensuing closedown. I wonder how the industry would have looked today with vendor- independent P&R? -- David Pashley < --------------------------- < < < --- mailto:david@edasource.com | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | http://www.edasource.com < < < Fax: +44 1280 700577 | ------------------------------ < ---------------------------------Article: 15531
Mike Roberts wrote: > > The aerospace and defense market is definately niche and can not drive new > product development. It is also very hard to support a company on an > industry/market that is shrinking. I'm sure these companies have a broader base than just Hi-Rel and saftey critical applications ... >>Antifuse devices do offer low >>quiescent current and are non-volatile (they are also very fast). Hmmm .... blazing speed and miserly power consumption .... bet that might attract a few customers ;-) > I re-iterate, the future does not look bright for anti-fuse based FPGAs. You know the old analogy between opinions and a paricular body cavity ... they say that every body's got one ;-) Of course, a few strong supporting points could elevate an opinion to a position ... care to share some of your insight ?Article: 15532
Mark Rogers wrote: > > If you really want free tools, then work at a big company. I don't pay for > any tools from any FPGA vendor. And I make the FAE's come in and help me > install the software and get me started using it. Another thing I do is > just crank out some VHDL, give it to a bunch of FPGA vendors and tell them > to fit it in there parts. Smallest, lowest power, cheapest part wins the > design. This has really worked well between Xilinx and Altera, man those > guys will fight it out. We also get them to convert are old schematic based > designs to VHDL for us. I can relate ... At my corp. they even provide free VHDL training, free VHDL books, free lunch, etc ... Although I must admit, getting these guys to convert your schematics to VHDL really takes the cake. BTW, do you find that these vender converted VHDL implementations tend to contain instances of vendor specific macros ?Article: 15533
mike, one thing to look at, and you might want to pull some numbers, is the size of the aerospace and defense _electronics_ markets [i don't follow marketing stuff very closely]. anyways, i've read a number of times, iirc, that while defense budgets shrink, the defense electronics budgets are either stable or growing [perhaps some old issues of military & aerospace electronics will help, i don't save mine]. also, with regards to space, the commercial space market is growing, and the extent of that growth and if and how it will accellerate is the topic of intense debate [see sci.space.* newsgroups, for example]. of course one could debate the +'s and -'s of differing storage/configuration technologies in different environments which always proves to be interesting ... ... along with how to cope with each of the technologies and what their limits are. have a nice day, rk ________________________________________________________________ Richard Guerin wrote: > Mike Roberts wrote: > > > > The aerospace and defense market is definately niche and can not drive new > > product development. It is also very hard to support a company on an > > industry/market that is shrinking. > > I'm sure these companies have a broader base than just Hi-Rel and saftey > critical applications ... > > >>Antifuse devices do offer low > >>quiescent current and are non-volatile (they are also very fast). > > Hmmm .... blazing speed and miserly power consumption .... bet that > might attract a few customers ;-) > > > I re-iterate, the future does not look bright for anti-fuse based FPGAs. > > You know the old analogy between opinions and a paricular body cavity > ... they say that every body's got one ;-) > Of course, a few strong supporting points could elevate an opinion to a > position ... care to share some of your insight ?Article: 15534
Jamie Morken wrote: > Hi, > > Does anyone know why the new virtex parts are partially > reconfigurable > by column? That is the natural structure ever since XC2000. Each frame is shifted into a "vertical" shift register, then transferred into the configuration latches in parallel. > Are they planning on allowing partial reconfiguration like > > the XC6200 series had? No. The addressing is by frame only, not random for the whole configuration space. Peter Alfke, Xilinx ApplicationsArticle: 15535
Richard Guerin <guerin2@home.com> wrote in message news:36FFA6F5.E730F3A7@home.com... > > I can relate ... At my corp. they even provide free VHDL training, free > VHDL books, free lunch, etc ... Although I must admit, getting these > guys to convert your schematics to VHDL really takes the cake. BTW, do > you find that these vender converted VHDL implementations tend to > contain instances of vendor specific macros ? I dig the free lunches also. Although I have found that the free VHDL training tends to be 10% VHDL and 90% : this is why my part is better than everyone else's. I have not personally had my own design converted by them, although I came close. The problem I have with that is the resulting VHDL would kind of look like C code that was written from some one else's assembly. It just won't have the high level structure that makes VHDL so nice. I have not heard of vendor specific macros being a big issue, although I am sure you have to put up resistance to it. I tend to insist that if there tools are any good they won't need vendor specific macros. That sort of thing prevents us from being able to give a bunch of vendors some VHDL and seeing who has the best fit. Although there are certain areas where it just makes sense like embedded ram or ROM blocks. In these cases we can get the opposing FAE to help with the conversion, that is, if he wants a shot at having a design win. MarkArticle: 15536
Mike Roberts wrote: > Depending on the actual device, at speed greater than > 50Mhz, FPGAs start > approaching CPLDs and I have seen data that over 100Mhz > some CPLDs actually > consume less current. There is a cross-over point. There is no cross-over point. All CMOS has dynamic power consumption = CfVsquared. All conventional CPLDs add to this a substantial quiescent current in their wiredAND read amplifiers ( Coolrunner avoids that by using expensive multiplexers). FPGAs have a only few milliamps ( or less ) for housekeeping functions. So given the same voltage swing, internal capacitance and activity, the dynamic power is identical, and the CPLD always consumes more power due to the static component.. Of course, it's really comparing apples and oranges. Peter Alfke, Xilinx ApplicationsArticle: 15537
David Pashley wrote: > I > > The reason Xilinx bought NeoCAD was that from the > perspective of the > market leader, a P&R tool which supported Actel, Altera, > Lucent and > Xilinx, AND offered a virtually free of charge version > which allowed you > to try out the different options, was rightly seen as a > massive threat. > Students of medieval history can easily find out that NeoCAD had given up any ideas about general design portability, long before Xilinx made them an offer they could not refuse... Peter AlfkeArticle: 15538
Ray Andraka wrote: > Actually in that case, I would have preferred to have a SRAM based FPGA in > there, but not its PROM. In the event of a incident where the equipment > might wind up in the wrong hands, simply removing power or hitting the > program pin would wipe out the SRAM and there would be no chance of the > enemy even getting one working copy to use or study. In that case, the > FPGA would be programmed sometime before the mission, so that the only > copy of the program on board is the one in the FPGA. Can you imagine the technicians in the military base using byteblaster and xchecker cables while they are pumping gas into the fighers and bombers? It would be pretty amusing to see a critical mission aborted because DONE does not go high. Just a deep thought :) > Looked at in that > way, the SRAM FPGA provides the ultimate in security as long as you can > tolerate keeping it alive. > > Richard Guerin wrote: > > > Mike Roberts wrote: > > <snip> > > > The non-reprogrammability seems to be the biggest drawback. > > > > In some market segments this is actually viewed as a desirable feature > > along with design security (could you imagine the impact to national > > security if the Serbs could extract crypto decoding implementation > > from the recently downed F117A ?) > > > > >The future does not look bright for anti-fuse FPGAs. > > > > They have their niche market .... future is secure so long as > > aerospace and defense applications continue retargeting ASICS to > > FPGAs. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randrakaArticle: 15539
Does anyone know of an equivalent to DEC's PAM (based on Xilinx) that uses Altera FLEX chips for Rapid Prototyping. Also anyone using PAM (other than for university work)? -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15540
In article <7dns8o$3be$1@mach.vub.ac.be>, "De Valck Joeri" <jfdvalck@info.vub.ac.be> wrote: >Hello, > >Has anyone successfully implemented a neural network in Xilinx 4000/6000 >FPGA's , or does anyone know where to find more information ? > >Thanx. Yes. Check out: M. Gschwind, V. Salapura, O. Maischiberger,"A Fast FPGA Implementation of a General Purpose Neuron", FPL '94 Proceedings, Springer-Verlag 1994, ISBN# 3-540-58419-6 And also see their paper "A Generic Building Block for Hopfield Neural Networks with On-Chip Learning". Indeed, many of their papers, and plenty of other useful references, are at http://www.vlsivie.tuwien.ac.at/mike/custom-computing.html Look in the papers for the references. Alex Rast arast@inficom.comArticle: 15541
Peter Alfke wrote: > Jamie Morken wrote: > > > Hi, > > > > Does anyone know why the new virtex parts are partially > > reconfigurable > > by column? > > That is the natural structure ever since XC2000. Each frame > is shifted into a "vertical" shift register, then > transferred into the configuration latches in parallel. > > > Are they planning on allowing partial reconfiguration like > > > > the XC6200 series had? > > No. The addressing is by frame only, not random for the > whole configuration space. > > Peter Alfke, Xilinx Applications You can configure down to the bit level with the Virtex. You just give it a frame with one bit different. You should be able to do this at runtime although it won't be supported by the M1 software. JBits might be able to handle it thought. http://www.xilinx.com/products/software/sx/sxpresso.html#JBITS -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 15542
Richard Guerin wrote: > > Ray Andraka wrote: > > > > Actually in that case, I would have preferred to have a SRAM based FPGA in > > there, but not its PROM. > > Hmmm .... an interesting suggestion. However, as they say in the > business, "don't think that would fly (pun intended)" ;-) > > Your suggested approach assumes an ideal operating environment ... that > there would be no ACFT power interruption or other upset event during > the normal course of a mission. A weapon system like the F117 would be > required to survive in an extremely hostile environment (including > flying through nuclear fallout) and still be able to complete its > intended mission. I realize that this is not a typical consideration in > most lower-tech and consumer applications .... doubt that most FPGA > designers have to worry about passing environmental stress screening > (shake-and-bake) tests. It would probably be a good idea to divide things into what's absolutely nescesary and what can be done without e.g. communication vs. controlsystems but.. theres probably lots of stuff uploaded to RAM anyways, and I'de think the crypto is based on the codes, not on the algoritmes being secret. If it were a problem a solution would be to simply "vaporize" everything critical in the event that the pilot leaves the plane using the ejection seat. --L2C --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_---- Lasse Langwadt Christensen, MSEE (to be in 1999) Aalborg University, Department of communication tech. Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.orgArticle: 15543
Hervé Echelard wrote: > I want use Xchecker to download program into Xilinx (serial cable), and with > the same interface, exchange data with the computer (like Terminal into > Windows). > > Then, I search plan about the xilinx serial download cable. > > Thanks > > mail to herve.echelard@wanadoo.fr Hello In the foundaton help content, try the Hardare User guide. Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes France (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 15544
On Mon, 22 Mar 1999 15:38:11, Ray Andraka <randraka@ids.net> wrote: > count and vary from vendor to vendor. Personally, I find it more useful > to count CLBs. What are them? Damiano Rullo Trezzano S/N Milan, Italy http://members.it.tripod.de/Damianoux/index.html mailto: dmn@cheerful.com mailto: damiano@mclink.itArticle: 15545
David, Check out http://www.apsfpga.com look under SUPPORT. There are some VHDL examples there. David Braendler wrote: > Can anyone provide some pointers to free/shareware VHDL code which is > available for Active-VHDL / XILINX ? > > Cheers. > > Dave Breandler > Swinburne University of Technology -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 15546
APS wrote: > > David, > > Check out http://www.apsfpga.com look under SUPPORT. There are some VHDL > examples there. Some of the more interesting links on the page http://www.associatedpro.com/aps/labx84.html don't seem to work, namely the links Advanced Labs, MODULAR Code Design and Recommended VHDL Do's and Don'ts. Can you do something about this? Thanks, -- name : Jo Depreitere | University of Ghent e-mail : jdp@elis.rug.ac.be | Electronics and Information Systems Dept. Phone : ++32+9/264 34 09 | Sint-Pietersnieuwstraat 41, B-9000 Ghent Fax : ++32+9/264 35 94 | http://www.elis.rug.ac.be/~jdpArticle: 15547
Look at the history of one time programmable (OTP) devices. EPROMs have been replaced by flash for external program storage and on-chip for micros. PALs gave way to GALs. No one is developing any more EPROM based CPLDs, they are all Flash or E2PROM. OTPs require socketing (expensive for high pin count devices) for development and extra handling that adds to failures and consumes time. You can also consume tubes of parts (expensive parts) in the process. In production, Anti-fuse devices have long programming times that make them undesirable for large production runs. I think your are misunderstanding me. I don't want to see Anti-fuse fade away, I just can't see a bright future. And I am not alone. TI didn't see a brignt future -- they stopped 2nd sourcing Actel and sold resources to Actel. Cypress didn't see a bright future -- they stop 2nd sourcing Quicklogic. Anti-fuse devices, because of their speed, do have a market. If the speed wasn't there, their market shrinks further. If you have a non Hi-Rel application at memium to slow speed -- do you choose on OTP device or a re-programmable part? This is where a majority of the applications are and the reason SRAM based FPGAs are so popular. Richard Guerin <guerin2@home.com> wrote in message news:36FFA33A.36BC2703@home.com... > > > Mike Roberts wrote: > > > > The aerospace and defense market is definately niche and can not drive new > > product development. It is also very hard to support a company on an > > industry/market that is shrinking. > > I'm sure these companies have a broader base than just Hi-Rel and saftey > critical applications ... > > >>Antifuse devices do offer low > >>quiescent current and are non-volatile (they are also very fast). > > Hmmm .... blazing speed and miserly power consumption .... bet that > might attract a few customers ;-) > > > I re-iterate, the future does not look bright for anti-fuse based FPGAs. > > You know the old analogy between opinions and a paricular body cavity > ... they say that every body's got one ;-) > Of course, a few strong supporting points could elevate an opinion to a > position ... care to share some of your insight ?Article: 15548
In article <36FFB708.1BD59892@xilinx.com>, Peter Alfke <peter@xilinx.com> writes >David Pashley wrote: > >> I >> >> The reason Xilinx bought NeoCAD was that from the >> perspective of the >> market leader, a P&R tool which supported Actel, Altera, >> Lucent and >> Xilinx, AND offered a virtually free of charge version >> which allowed you >> to try out the different options, was rightly seen as a >> massive threat. >> > >Students of medieval history can easily find out that NeoCAD >had given up any ideas about general design portability, >long before Xilinx made them an offer they could not >refuse... > Well, you may call it medieval history, but I remember it well, and recall it differently. Perhaps you can tell us how to "easily find out" about your version of events? David PashleyArticle: 15549
I suppose I should have made this comment a little less vendor specific. I count the logic blocks, which xilinx calls CLBs (configurable logic blocks), altera calls LEs (logic elements) etc. Of course to make any comparisons useful, you do need do have some knowledge of the logic cell architecture too. NO-SPAM damiano wrote: > On Mon, 22 Mar 1999 15:38:11, Ray Andraka <randraka@ids.net> wrote: > > > count and vary from vendor to vendor. Personally, I find it more useful > > to count CLBs. > > What are them? > > Damiano Rullo > Trezzano S/N > Milan, Italy > http://members.it.tripod.de/Damianoux/index.html > mailto: dmn@cheerful.com > mailto: damiano@mclink.it -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z