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Hello,
I have bought a Xilinx FPGA Demonstration Board containing two chips:
a XC3020A and a XC4003E. Up to now I've been able to program only very
small combinatorial circuits into the smallest FPGA. In particular when
I try downloading some slightly bigger projects nothing happens and I
have no idea of what's wrong.
Has anyone of you used this board and is willing to give me some hint ?
Can you redirect me to someone able to answer my questions ?
Thank you.
Davide
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Davide Falchieri
VLSI & Fuzzy Logic Research Group
Physics Department, Bologna University
40127,Viale Berti Pichat 6/2, Bologna(ITALY)
TEL:+39-51-2095077, FAX:+39-51-2095297
URL:http://sunvlsi4.bo.infn.it/~davide
e-mail : davide.falchieri@bo.infn.it
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Article: 16826Anyone using the PCI cores from Xilinx? Has anyone tied I2O into a FPGA with the above PCI core, or implemented the bottom end of I2O in a FPGA? Does it require an IO processor on the target I/O card, or can this bit of it be implemented in an FPGA? Andy.Article: 16827
In article <37610A6A.33A5A7D1@harris.com>, Brian Boorman <XZY.bboorman@harris.com> wrote: > Reinoud wrote: > > > > gibsond@bournemouth.ac.uk wrote: > > > I'm trying to use the student edition of Xilinx F1.5. When I place and > > > route, if I've locked all the pin in the design to specific locations > > > the flow engine hangs when it gets to the constructive placer. If I > > > leave at least one pin un-located there is no problem. Is this a > <snip> > > Duh. I think I can figure out where that single remaining I/O would > > be placed, given that only one pin isn't locked. > > > > - Reinoud > > I think you assume too much. He may not be using all the pins of the > device, so leaving it unlocked would allow the placer to put it on > whatever unused pin it felt like using. Another work-around is to create > a dummy signal pin that does something trivial and let that pin that you > don't care about be the "floater". > > I would try searching the online support section at www.xilinx.com and > failing that call the tech support line and pose it to them. Xilinx is > one of the best in terms of technical support (IMHO). > -- > Brian C. Boorman > Harris RF Communications > Rochester, NY 14610 > XYZ.bboorman@harris.com > <Remove the XYZ. for valid address> > Thanks for the advice. I'll give it a try (a bit of a pain though). Unfortunately Xilinx do not offer any support for the student edition and I can't find the answer on the support pages. Darrell. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16828
A friend and I have just been through exactly this problem: Student edition F1.5 hangs in the router. We also had crashes in the mapper. The solution to both was to apply BOTH the F1.5 service pack, and the version 2 hot fix to that service pack. Do not apply F1.5i service packs to version F1.5, it wont work. The main service pack is at ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip and the increment is at ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp2_nt.zip For ref, see this for warnings http://www.xilinx.com/techdocs/4897.htm Some of the problems seem to be related to having visual C++ V 6.0 on your system. Philip Freidin In article <7jqnpo$c7r$1@nnrp1.deja.com> gibsond@bournemouth.ac.uk writes: >Hi, > >I'm trying to use the student edition of Xilinx F1.5. When I place and >route, if I've locked all the pin in the design to specific locations >the flow engine hangs when it gets to the constructive placer. If I >leave at least one pin un-located there is no problem. Is this a >limitation of the student edition or a known problem. Has anyone else >come across this? Is there a work around other that not locating all >the pins. It is a bit of a pain not being able to specify all >locations. > >Thanks, > >Darrell Gibson. > > > >Sent via Deja.com http://www.deja.com/ >Share what you know. Learn what you don't.Article: 16829
david braendler <dbraendler@swin.edu.au> wrote: : I'm looking at buying a Virtex board (preferably with a PCI interface) : and I'd be interested to here what people think of the Virtex boards : that they have used. As a related question, I only know of three suppliers of Virtex boards at the moment: VCC: http://www.vcc.com/VW.html Nallatech: http://www.nallatech.com/dime/ballynuey/ballynuey.htm Annapolis: http://www.annapmicro.com/PR9126.html Are there any other Virtex board suppliers out there? -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Call me if you want my number; mail me if you want my address.Article: 16830
Hi,
I just got the free demoof actel desktop (free until jan 2000). The
licence agreement proposes other devices as Xilinx, altera...
As it's an actel product i'm not sure time limited licences for those
devices are free too.
anyone already tried?
thanks
C.COMBARET
--
Fais le ou ne le fais pas, mais il n'y a pas d'essai.
Yoda
Article: 16831gibsond@bournemouth.ac.uk wrote: > > Thanks for the advice. I'll give it a try (a bit of a pain though). > Unfortunately Xilinx do not offer any support for the student edition > and I can't find the answer on the support pages. > > Darrell. > If you send me a zipped up copy of your design, I can try running it through our full blown version. I have the 1.4 version of student edition at home at didn't have problems. I have 1.5i here at work. E-mail address below (don't forget to de-spam) -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 16832
Thank god I don't work with this DORK... I hope you will keep your critisism constructive from now on.. thanks Reinoud <dus@casema.net> wrote in message news:3760F06A.E0E039FE@casema.net... > gibsond@bournemouth.ac.uk wrote: > > I'm trying to use the student edition of Xilinx F1.5. When I place and > > route, if I've locked all the pin in the design to specific locations > > the flow engine hangs when it gets to the constructive placer. If I > > leave at least one pin un-located there is no problem. Is this a > > limitation of the student edition or a known problem. Has anyone else > > come across this? Is there a work around other that not locating all > > the pins. It is a bit of a pain not being able to specify all > > locations. > > Duh. I think I can figure out where that single remaining I/O would > be placed, given that only one pin isn't locked. > > - ReinoudArticle: 16833
www.exemplar.com
they may have a 10 or so day trial version
Wenwei Qiao <WWQiao@SIGNTECH.COM> wrote in message
news:M9Y53.419$r03.218693764@dca1-nnrp1.news.digex.net...
> What and where is Leonardo?
>
> David Hawke <dhawke@globalnet.co.uk> wrote in message
> news:7j703e$aga$1@gxsn.com...
> > You could always use Leonardo to read in the Altera EDIF and then
retarget
> > towards Xilinx.
> > I use this quite a lot when I need a quick (but slightly dirty
conversion)
> >
> > Regards,
> >
> > David Hawke.
> > Xilinx.
> >
> > Bill Gates wrote in message <7j69in$9nf$1@tourist.gnt.net>...
> > >Unfortunately the EDIF that Max+plus gave you uses parts available for
> the
> > >particular
> > >chip family that was selected by the Max tools and the Xilinx part you
> want
> > >to use
> > >does not have the same parts (i.e. AND1 for instance). If you get this
> to
> > >actually work
> > >I would be amazed.
> > >
> > >If you have the original VHDL code (that is if you didnt use Max's AHDL
> or
> > >some
> > >schematic entry) then I would use that instead by either compiling it
in
> > >Xilinx or some
> > >"better" tool like leonardo or synplicity.
> > >
> > >Good luck... maybe someone else has a suggestion as to how to edit the
> edif
> > >file
> > >or something to that nature.
> > >
> > >
> > >Vitolo <setel@mx3.redestb.es> wrote in message
> > >news:7j0s18$h9b29@SGI3651ef0...
> > >> Hi, all:
> > >>
> > >> I need convert a ALTERA design(MAX+PLUSII) into a XILINX design
> > >(Foundation
> > >> F1.3). I try export a Edif 200 file from MAX+PLUS and import netlist
> into
> > >> Schematic Editor of Foundation. I complet the design with the new
> > >component
> > >> (IBUF, OBUF, pads) and save. When i try export the netlist in a XNF
> file,
> > >> ihave a error message ("Missing AND1 model or library error") then i
> > >export
> > >> in a VHD file and have ("Cannot read pin descriptors for AND1")
error.
> > >>
> > >> I want to generate a VHDL file (XILINX Foundation compatible) from a
> EDIF
> > >> ,or other, ALTERA file. How i can to do?
> > >>
> > >>
> > >>
> > >
> > >
> >
> >
>
>
Article: 16834Just FYI, There is a list of available FPGA boards on The Programmable Logic Jump Station at http://www.optimagic.com/boards.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- david braendler wrote in message <3760678A.A8A66A58@swin.edu.au>... >I'm looking at buying a Virtex board (preferably with a PCI interface) >and I'd be interested to here what people think of the Virtex boards >that they have used. > > >Cheers >-- >--------------------------------------------------------------------------- ------------------ > >David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm >Centre for Intelligent Systems >Swinburne University of Technology >--------------------------------------------------------------------------- ----------------- > > >Article: 16835
I have done a PCI interface, that supported I2O in a Xilinx FPGA. I have my own PCI core, I did not use the Xilinx core, but I feel the current Xilinx core is just fine. It doesn't have any DMA though. Why would you need I2O support if your card didn't have a processor on it? Austin Franklin austin@darkroom.com In article <376120BD.44DCC54A@nortelnetworks.com>, Andy Bryant <ajb2@nortelnetworks.com> wrote: > Anyone using the PCI cores from Xilinx? > > Has anyone tied I2O into a FPGA with the above PCI core, or implemented > the bottom end of I2O in a FPGA? Does it require an IO processor on the > target I/O card, or can this bit of it be implemented in an FPGA? > > Andy. > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16836
Dear all, I tried to program an Altera EPC2 serial EEPROM via the JTAG interface. I used the Altera MAXPLUSII software and the byteblaster. But the JTAG chain check did not find the EPC2 on the bus. These is a simple 4 wire interface....and I checked the wires many times. Pull ups are all connected as given by the AN of altera.. without success.. Did anybody of you have some experience and success doing this job?. Please let me know if you use also an EPC2 in JTAG mode having similar problems.... Kind RegardsArticle: 16837
This is a multi-part message in MIME format. --------------708A8B60C9F2B5605EEF2136 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I need to implement digital filters (in general) on FPGAs, I want to do it with VHDL descriptions. Has anyone done this yet? Is there any site where I can get any examples? So, I need some bibliographics references about digital filters implementation. Thanks, and sorry by my poor english. --------------708A8B60C9F2B5605EEF2136 Content-Type: text/x-vcard; charset=us-ascii; name="jmorenoz.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for José Antonio Moreno Zamora Content-Disposition: attachment; filename="jmorenoz.vcf" begin:vcard n:Moreno Zamora;José Antonio tel;cell:+34-617-281660 tel;fax:+34-927-257267 tel;home:+34-924-230593 tel;work:+34-927-257267 x-mozilla-html:TRUE url:http://atc.unex.es/joseanmo/ org:Universidad de Extremadura;Departamento de Informática version:2.1 email;internet:jmorenoz@nexo.es title:Profesor adr;quoted-printable:;;Escuela Polit=E9cnica=0D=0AAvda. Universidad, s/n;Cáceres;Cáceres;10071;Spain fn:José Antonio Moreno Zamora end:vcard --------------708A8B60C9F2B5605EEF2136--Article: 16838
Yes, I have done it, but I don't have examples on-line. The filters are the same as those done under schematic entry. You do need to at least go to a low level RTL description to get the needed construction for more than a few taps. VHDL will not infer a distributed arithmetic structure from a high level description. Also, the filter is a fairly regular structure. You'll want to direct the placement to get reasonable performance. With all that in mind, I find it is considerably less painful to do the filter in schematics, with the exception of generating the coefficient LUTs. Of course, once you've done the painful work (especially if you've taken extra pains to make it parameterizable) in VHDL, reuse is easier. FIR filters are quite a bit easier to do in FPGAs than IIRs and are generally capable of higher data rates because you run into problems pipelining the feedback in IIR filters. You might look at some papers on the Xilinx website by Greg Goslin for a good overview of how it is done. José Antonio Moreno Zamora wrote: > I need to implement digital filters (in general) on FPGAs, I want to do > it with VHDL descriptions. > Has anyone done this yet? > Is there any site where I can get any examples? > So, I need some bibliographics references about digital filters > implementation. > Thanks, and sorry by my poor english. > > ------------------------------------------------------------------------ > > José Antonio Moreno Zamora <jmorenoz@nexo.es> > Profesor > Universidad de Extremadura > Departamento de Informática > > José Antonio Moreno Zamora > Profesor <jmorenoz@nexo.es> > Universidad de Extremadura HTML Mail > Departamento de Informática > Escuela Politécnica Avda. Universidad, s/n;Cáceres;Cáceres;10071;Spain Cellular: +34-617-281660 > Fax: +34-927-257267 > Home: +34-924-230593 > Work: +34-927-257267 > Additional Information: > Last Name Moreno Zamora > First NameJosé Antonio > Version 2.1 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16839
> >I need to implement digital filters (in general) on FPGAs, I want to do >it with VHDL descriptions. >Has anyone done this yet? >Is there any site where I can get any examples? >So, I need some bibliographics references about digital filters >implementation. >Thanks, and sorry by my poor english. Have a look at http://www.iowegian.com/loadfir.htm Hans.Article: 16840
Greetings, As independent developers of cost critical hardware designs, we are fed up with trying to find ballpark prices for available technology. Please reply if you have similar experience and would be interested in contributing and using a web resource for the publishing of such data. Regards, Simon Armstrong simon@gatecrashers.comArticle: 16841
Hi, Most of the articles related to reconfigurable computing links to the site www.reconfig.com. This site is not accessible. Any idea what happemed to this site. Thanks, Rajul Maheshwari CS & E Dept.Article: 16842
Bill Gates wrote: > > Thank god I don't work with this DORK... Thank you, mr. Gates, for making me look relatively non-dorky around here. :-) Darrel, sorry for misinterpreting your post. I thought you were missing the obvious, but instead I was. Duh. On the subject, I have run fully locked designs through both XSE F1.5 (unpatched) and full F1.5i (sp1), without problems. However, I *did* see crashes with both versions. The XSE died often in horrible and obscure ways, when only a subset of device files was installed. Fixed by reinstalling with all devices. The full version died on several Windows installations, in the mapper I think, due to an outdated msvcrt.dll. Fixed by manually moving the right dll (found in the Foundation directory tree somewhere) in place. Good luck, - ReinoudArticle: 16843
Hi I would like if there is any macro or VHDL code to handle real (floating point) numbers with synthesizable Xilinx Express VHDL. Please, email me. Thanks in advance. Juan -- ----------------------------------------------------- | Juan Antonio Gomez Pulido | | | | Dep. de Informatica | Dep. of Computer Sciences | | Escuela Politecnica | Escuela Politecnica | | Univ. de Extremadura | University of Extremadura | | 10071 Caceres. España | 10071 Caceres. Spain. | | Fax: (927)257202 | Fax: +34-927-257202 | | Email: jangomez@unex.es | -----------------------------------------------------Article: 16844
The ADC-RC1000 from Alpha Data can be fitted with any of V400 through to V1000 in a BGA560 package and the board is also compatible with 40150XV/40250XV. It also has two PCI mezz slots for further expansion and a PCI-PCI bridge to the host. contact sales@alphadata.co.uk for further info. Tim Tyler wrote in message <929123439.7940@BITS.bris.ac.uk>... >david braendler <dbraendler@swin.edu.au> wrote: > >: I'm looking at buying a Virtex board (preferably with a PCI interface) >: and I'd be interested to here what people think of the Virtex boards >: that they have used. > >As a related question, I only know of three suppliers of Virtex boards >at the moment: > >VCC: http://www.vcc.com/VW.html >Nallatech: http://www.nallatech.com/dime/ballynuey/ballynuey.htm >Annapolis: http://www.annapmicro.com/PR9126.html > >Are there any other Virtex board suppliers out there? >-- >__________ > |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com > >Call me if you want my number; mail me if you want my address.Article: 16845
Do you know of anyone who has used a VCC virtual workbench yet? We've had ours on order since April and are still waiting for it to arrive to try it out "Steven K. Knapp" wrote: > Just FYI, > > There is a list of available FPGA boards on The Programmable Logic Jump > Station at http://www.optimagic.com/boards.html. > > ----------------------------------------------------------- > Steven K. Knapp > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com > ----------------------------------------------------------- > > david braendler wrote in message <3760678A.A8A66A58@swin.edu.au>... > >I'm looking at buying a Virtex board (preferably with a PCI interface) > >and I'd be interested to here what people think of the Virtex boards > >that they have used. > > > > > >Cheers > >-- > >--------------------------------------------------------------------------- > ------------------ > > > >David Braendler http://gene.bsee.swin.edu.au/daveb/index.htm > >Centre for Intelligent Systems > >Swinburne University of Technology > >--------------------------------------------------------------------------- > ----------------- > > > > > > -- Bio-Inspired Architectures Department of Electronics University of York, UK 01904 432379 (office) http://www-users.york.ac.uk/~dwb105Article: 16846
Check the Open Directory, http://dmoz.org/Computers/Open_Source/Hardware/ --reto - Opinions are mine and not those of my companyArticle: 16847
I intend to do the same thing but have not yet implemented it in hardware. Did you implement a pull up at the EPCs TCK pin? Altera AN39 states on page 245 that if TCK is pulled high , power up conditions must ensure that TMS is pulled high *before* TCK. Pulling TCK low avoids this power up condition. I would appreciate if you could let me know if this solved the problem, or where the problem was in the end! Regards Tino Konschak Juergen Otterbach wrote in message <37621A9F.C636E818@t-online.de>... >Dear all, >I tried to program an Altera EPC2 serial EEPROM via the JTAG interface. >I used the Altera MAXPLUSII software and the byteblaster. But the JTAG >chain check did not find the EPC2 on the bus. >These is a simple 4 wire interface....and I checked the wires many >times. Pull ups are all connected as given by the AN of altera.. >without success.. >Did anybody of you have some experience and success doing this job?. >Please let me know if you use also an EPC2 in JTAG mode having similar >problems.... > >Kind Regards >Article: 16848
Hello World! I am currently looking for established companies who offer JTAG/Boundary Scan equipment to program CPLDs, FPGAs and Flash "In-System". We need a seamless product to take us through design, production, field-testing and upgrades. Of particular importance is a portable application for field use. The following companies offer solutions of varying price and specification: Acculogic, Asset Intertech, Corelis, Data I/O, Goepel and JTAG Technologies. All have home pages on the web. Does anyone know of any more companies who offer JTAG/BST? Has anyone experience of working with the above companies? Does anyone use JAM/STAPL yet? Best Regards Adrian Donegan British Aerospace Defence Systems Limited Cowes, Isle of Wight Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16849
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