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Altera has a DSP kit for the big FPGA including the common functions in integer. "Cemal Coemert (TIP)" wrote: > Hi everyone, > > I would like to implement some DSP functions in a FPGA ( with VHDL ). > Where can I get some examples? > > Have a nice day > CemalArticle: 16376
In short: FPGA's has many registers with small logic tables. The others has fewer registers with large input logic blocks given small delayes for functions with many input signals like address decoders and statemachines. kamath@ecn.purdue.edu wrote: > Hi, > > Where can I find a good explanation on the differences between these. I know > VHDL(ahdl) and have programmed all types but don't know the differences > (pretty pathetic huh). > > Thanks-Uday > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16377
You can't make a schmitt trigger by code as it is an analog function and the code is digital. Some devices may have schmitt trigger I/O's, but they are rare as they are slower as normal I/O. Open collector can be simulatet by tristate outputs. 0 is 0 (enabled) , and 1 is Z (disabled). I don't the 9536 cpld, see the datasheet. Hi Peter Uday Godbole wrote: > Hi, > > I need to use a schmitt trigger gate. Can it be made on a Xilinx 9536 cpld? > I have their starter kit, but the schematic capture software does not seem > to have one in the library.. Also, can an open collector output be simulated > on this device? > > TIA > > UdayArticle: 16378
My design currently consists of four entities. The four entities when synthesized and implemented independently have a CLB count of 10, 17, 4, and 9. When I combine the four entities the new CLB count is 156. The whole design is straight combinational logic. The first two entities are 8 functions of 8 variables each, they each use a case statement with 256 possibilaties. The third entity is a simple multiplexer which selects 1 of 2 8-bit vectors. The last entity is a 4-to-1 multiplexor along with some shifts. Is there any way to have FPGA Express synthesize an entity of a design without trying to optimize it with the components surrounding it? I think that FPGA Express is combining the logic used in the first two entities with the multiplexer which ruins the symetry within the logic of the first two entities. Any help or ideas on the matter will be greatly appreciated. Thanks in advance, DominicArticle: 16379
In article <37370ED0.12DDF8E5@usa.com>,
asap <asapd@usa.com> wrote:
> Hi all,
>
> I'm trying to do a post-synthesis
> simulation with Modelsim EE 5.2,
> using the VITAL lib of my ASIC vendor.
> I keep getting errors that some instances
> do not have one or two generics (e.g.: tpd_c_q_posedge).
> (I do not have errors of missing instances...)
> I don't think there is any error on the top instance
> I apply the sdf file, nor similar things...
> However, I don't know if i produce wrongly the sdf/vhdl files
> from Synopsys DC v1999.05 (I use the SDF v2.1 format).
> Is there any chance that the vendor ASIC VITAL models
> are not 100% VITAL compatible, as mentioned on the
> Modelsim user manual?
>
> Thanks,
The story has two sides. For an ASIC library used inside Synopsys
a Synopsys model needs to be described (.lib) which is compiled
into a binary format (.db) by Library Compiler (lc) of Synopsys.
Usually the ASIC vendor is already providing the .db format, so
you as customer do not need to have the lc license and do not need
to compile it yourself.
In this Synopsys model there is a delay defined from the rising
edge of 'c' to the output 'o' (for tpd_c_q_posedge). It looks
like follows in the .lib model (often not delivered by the ASIC
vendor):
pin(q) {
:
timing() {
timing_type : rising_edge;
timing_sense : "non_unate";
intrinsic_rise : 2.00;
intrinsic_fall : 2.00;
rise_resistance : 0.20;
fall_resistance : 0.20;
related_pin : "c";
}
}
Based on this model the delay calculator in Synopsys DC
is generating the SDF file. In your case you will find
there an entry like
IOPATH (posedge c) q (2.00:2.00:2.00)
The second part are the VITAL models of your standard cell
library. To be able to backannotate the values estimated
by Synopsys delay calculator, the VITAL timing generics
need to meet certain requirements. Only then the SDF
backannotator in the Simulator (like ModelSim) can map the
SDF entry with the VITAL generic correctly. In the assumed
SDF entry given above the generic needs to be like follows:
tpd_c_q_posedge
If you have the VHDL/VITAL source code of your standard cell
library (usually delivered by the ASIC vendor) you can check
the defined timing generics of the cell which makes trouble.
I guess, you will find either no definition or something like
tpd_c_q
The missing edge specifyer is enough to let the SDF backannotator
failing.
Have fun,
Alex
--== Sent via Deja.com http://www.deja.com/ ==--
---Share what you know. Learn what you don't.---
Article: 16380Italian Cowboy wrote: > > Personally, I'm working on dynamic reconfiguration (PoliMorph > Project, Politecnico of Milan), i.e. exactly what you guys are > talking about. Despite the loads of projects in this promising > field, though, I always notice that everybody neglects what I > deem the most important problem of all. > > Steve himself pointed out that "the SW IS the computer", but > maybe he forgot the implications: the biggest hurdle here is > *not* the reconfigurable array (today's Xilinx could already > provide us with outstanding results, were we able to use them > fully), but a suitable and overall automatic way to take > advantage of the beast. > > I mean, everybody can imagine a computer that goes on > reconfiguring the FPGA on the fly and boosting performance like > crazy, but as long as we don't have a sort of compiler that gets > a standard C++ code or whatever and understands what portions of > the code are to be implemented in Hardware and how, our vision > will just remain what it is... a vision. At one company that I worked for, we had the idea that pieces of hardware were analogous to threads. In other words, they work in parallel with other pieces of hardware and software threads. They also exchange information with other threads (of both kinds). So we were working on an "operating system" (we actually called it a "runtime environment") that understood which threads were to be executed in hardware and which in software. Like software threads, our hardware threads had priorities and could be pre- empted by more important work. I made a presentation about these ideas at DesignCon98/PLDCon98. The slides are available on the web for anyone who's interested: http://www.netrino.com/Papers/ControllingRC/ Perhaps these ideas will be valuable to someone reading this. I am, unfortunately, no longer working in this field. Though, I do still follow the work that's going on as much as I can. Cheers, MichaelArticle: 16381
In article <3738DDF1.9C804214@phoenix.dwe.co.kr>, Kyungjin Jang <sandrose@phoenix.dwe.co.kr> wrote: > I confronted similar problem. > I used Synopsys's DesignPower to estimate of power of the chip. > When I compiled the VITAL intenal memory libary of STM by VSS, such as lines > made errors. > > ==> VITAL Entity 'FIFO_94X16' has VITAL conformance error(s): > TPD_OE_Q : VitalDealyArrayType01z(7 downto 0) := (others => > ^ > **Error: vhdlan,2148 FIFO_94x16_ent.vhd(20): > The type of a scalar timing generic parameter 'TPD_OE_Q' does not match > the > type of the associated ports. > ...... > > Other man who compiled by Leapfrog said he didn't have such error. > I could escape the error by changing the name TPD_CK_Q => aTPD_CK_Q. > I don't kwow why such error, but after changing it compiled well. > Maybe the name was a reserved word of VSS? > So, in my opinion, you may avoid error by changing names... > > Is there a person who knows the reason of my case? please let me know!!! > > -- *************************************** > -- Kyungjin Jang > -- DIT 2R, Daewoo Electronics CO., LTD. > -- *************************************** > I guess, that something in your FIFO model is not correct. In the VITAL standard the width of the type is defined like follows (types as example): Case 1: at least one port is bus -------------------------------- tpd_<Input_Port>_<Output_Port> : VitalDelayArrayType01Z(0 to ((width_Input * width_Output)-1)) Case 2: both ports are pins --------------------------- tpd_<Input_Port>_<Output_Port> : VitalDelayType01Z(0 to (width_Output-1)) Please check in your FIFO model if the ports (in the entity) are defined correctly: OE : std_logic Q : std_logic_vector(7 downto 0) By changing the name TPD_OE_Q => aTPD_OE_Q you excluded the generic (it's no more a VITAL generic) from the conformance check of the VHDL compiler. Because of this you do not get any error anymore. BUT you excluded it from backannotation as well. When you try to read in a SDF file, you will get an error of missing generic as well. Have fun, Alex --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---Article: 16382
Uday Godbole wrote in message <7htv83$fkj$1@usenet50.supernews.com>... >Hi, > >I need to use a schmitt trigger gate. Can it be made on a Xilinx 9536 cpld? >I have their starter kit, but the schematic capture software does not seem >to have one in the library.. Also, can an open collector output be simulated >on this device? I created a Schmitt trigger once on a Lattice CPLD, using schematic entry. You can do it with a 2-input NAND and an inverter. LeonArticle: 16383
Peter Sørensen wrote: > You can't make a schmitt trigger by code as it is an analog function and the > code is digital. > Some devices may have schmitt trigger I/O's, but they are rare as they are > slower as normal I/O. It's not quite that bad.If you are really desperate to put hysteresis on a certain input, and you are willing to sacrifice an extra output, and use two external resistors, do the following: Drive the extra output with the signal ( uninverted) that you receive. Externally connect a 100 kilohm resistor from this output to the input. Then drive the input through a 10 kilohm resistor. The analog resistor divider is now outside the chip, and you can of course play with different resistor values and ratios. Not elegant, but better than giving up. Peter Alfke, Xilinx ApplicationsArticle: 16384
What files do realy need to be archived in a Foundation (1.4) project? If I use F1.4 archive facility, it zips the whole directory, which results in a big file I can't copy to a diskette. By the way, I am using it for XC95XX.Article: 16385
> > > > > Steve himself pointed out that "the SW IS the computer", but > > maybe he forgot the implications: the biggest hurdle here is > > *not* the reconfigurable array (today's Xilinx could already > > provide us with outstanding results, were we able to use them > > fully), but a suitable and overall automatic way to take > > advantage of the beast. > > > > I mean, everybody can imagine a computer that goes on > > reconfiguring the FPGA on the fly and boosting performance like > > crazy, but as long as we don't have a sort of compiler that gets > > a standard C++ code or whatever and understands what portions of > > the code are to be implemented in Hardware and how, our vision > > will just remain what it is... a vision. I have always said "its the tools." But really it is more than that. I believe that the right system has to be in place to me that means hardware and software built together from the ground up. It means making RPUs that have their I/O hardwired and committed in the system. It means having true relocatible hardware functions. I means having a mind set that includes the RPU/FPGA and tools at the beginning of the design cycle instead of trying to shoehorn a reconfigurable computer into a PCI bus Intel monster. It means .... But I digress, that would be a big job and would take more money than we can generate at this time. -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 16386
Sweet! I'll take a look immediately and I'll let you know. Thanx. Take care Guido Michael Barr <mbarr@netrino.com> wrote in message 3742B691.FFE98BCF@netrino.com... > Italian Cowboy wrote: > > > > Personally, I'm working on dynamic reconfiguration (PoliMorph > > Project, Politecnico of Milan), i.e. exactly what you guys are > > talking about. Despite the loads of projects in this promising > > field, though, I always notice that everybody neglects what I > > deem the most important problem of all. > > > > Steve himself pointed out that "the SW IS the computer", but > > maybe he forgot the implications: the biggest hurdle here is > > *not* the reconfigurable array (today's Xilinx could already > > provide us with outstanding results, were we able to use them > > fully), but a suitable and overall automatic way to take > > advantage of the beast. > > > > I mean, everybody can imagine a computer that goes on > > reconfiguring the FPGA on the fly and boosting performance like > > crazy, but as long as we don't have a sort of compiler that gets > > a standard C++ code or whatever and understands what portions of > > the code are to be implemented in Hardware and how, our vision > > will just remain what it is... a vision. > > At one company that I worked for, we had the idea that pieces of > hardware were analogous to threads. In other words, they work > in parallel with other pieces of hardware and software threads. > They also exchange information with other threads (of both kinds). > So we were working on an "operating system" (we actually called > it a "runtime environment") that understood which threads were to > be executed in hardware and which in software. Like software > threads, our hardware threads had priorities and could be pre- > empted by more important work. > > I made a presentation about these ideas at DesignCon98/PLDCon98. > The slides are available on the web for anyone who's interested: > > http://www.netrino.com/Papers/ControllingRC/ > > Perhaps these ideas will be valuable to someone reading this. I > am, unfortunately, no longer working in this field. Though, I do > still follow the work that's going on as much as I can. > > Cheers, > Michael > >Article: 16387
Try compiling without an fmax timing constraint. Then run timing analysis to see what frequency you got. In my experience compiles are much faster without an fmax constraint, (like 10 minutes instead of 9 hours!), and the resulting fmax is often good enough. Sometimes it is even better than with the constraint. -- JamieArticle: 16388
All, I've looked at all of the manuals and finally decided to ask the list. I want to assign the pads for my XCV1000 devices and assign I/O standards to those pads such as LVTTL, LVCMOS, drive strength and such. I am using Leonardo and cannot find an attribute to do this. I can find attributes to assign slew rate and such, but not what kind of pad it is!!! Help as I am tired of looking at the manuals. TBMArticle: 16389
Hi all, There have been 2 interesting topics posted: 4062XL problems and solutions and Post route simulation: EDIF or VHDL? So I thought with my knowledge on Synopsys' SmartCircuit models could provide other solutions for you. For those who are not familiar with this, SmartCircuit models are post place & route simulation models for programmable logic devices. Bill Kury wrote: > Problem #3 - High speed visibility > This isn't so much a problem but a question to ask how you do it. > When running at high speed internal to your fpga, how do you get > visibility into the device without changing the routing? I know you can > check the static timing and this will resolve 99.99% of your problems. > What I did was allowed some extra pins on the design to route signals > out to so that I could take a look. This worked well but, at the high > speeds, routing to pins will change your internal routing delays and > possibly mask the problem. Are there any other solutions out there? Visual SmartBrowse (GUI tool for your P&R design) and Windows feature from SmartCircuit allow the complete-internal visibility to the FPGA circuitry during post P&R simulation. I think there are other powerful features, e.g. Casual Tracing allows user to trace events and see where the problem is occurring or to trace the causes of a problem to their roots. On Mon, 17 May 1999 17:16:40 GMT, micheal_thompson@my-dejanews.com wrote: >I'm doing a timing simulation on a design fitted to an Altera Max7000 >device. I've used Altera's Maxplus2 for routing and have Viewlogic's >tools for simulation. >MaxPlus2 has given me a choice of output files: EDIF or VHDL. And this I also think the smooth simulation flow provided by SmartCircuit could easily answer Micheal's question. I don't have to worry about how I run my simulation (with QuickSim, VHDL, Verilog) or which simulator I am using. The simulation setups are transparent to me and save quite a lot of time and hassles. Has anyone else use this technology? Any comments? Peekay For those who are interested in learning more about this, see SmartModel Library User Manual, chapter 6 for SmartCircuit Models. http://www.synopsys.com/products/lm/docs/swift_r41/slum.pdfArticle: 16390
Anyone seen an M1.5 crash caused by a page faulting error? I seem to be running into it fairly often lately when the tools run the par executable. AdamArticle: 16391
I had a similar problem, It was advised that I upgrade my (early version)Windows 95 to the more recent 'B' version. I upgraded to Win 98 and the problems went away. David Adam J. Elbirt <aelbirt@nac.net> wrote in article <374354D7.63640FBD@nac.net>... > Anyone seen an M1.5 crash caused by a page faulting error? I seem to be > running into it fairly often lately when the tools run the par > executable. > > Adam > >Article: 16392
Adam J. Elbirt wrote in message <374354D7.63640FBD@nac.net>... >Anyone seen an M1.5 crash caused by a page faulting error? I seem to be >running into it fairly often lately when the tools run the par >executable. Crashing during the mapping? I had the same problem on NT. The Xilinx answer was that they thought there was an issue with Microsoft Visual Studio v6, but I didn't have that installed. Maybe one of Microsoft's "invisible" updates? The problem was the ordering of the parameters that the GUI sends to the map program. Running it from the command line with the parameters in a different order fixed the problem. There's also a patch that was available; I'm not sure if Service Pack 2 fixes the problem or overwrites the patch. I can send it to you if you like. -- a ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu "Space, reconnaissance, weather, communications - you name it. We use space a lot today." -- Vice President Dan QuayleArticle: 16393
Actually I am running 95 version B. It's in par, not map. I ended up having to run the tools manually from the command line which was incredibly painful. Guess I'll be using Altera for my next design. Adam Andy Peters wrote: > Adam J. Elbirt wrote in message <374354D7.63640FBD@nac.net>... > >Anyone seen an M1.5 crash caused by a page faulting error? I seem to be > >running into it fairly often lately when the tools run the par > >executable. > > Crashing during the mapping? I had the same problem on NT. The Xilinx > answer was that they thought there was an issue with Microsoft Visual Studio > v6, but I didn't have that installed. Maybe one of Microsoft's "invisible" > updates? > > The problem was the ordering of the parameters that the GUI sends to the map > program. Running it from the command line with the parameters in a > different order fixed the problem. There's also a patch that was available; > I'm not sure if Service Pack 2 fixes the problem or overwrites the patch. I > can send it to you if you like. > > -- a > ------------------------------------------ > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters@noao.edu > > "Space, reconnaissance, weather, communications - you name it. We use space > a lot today." > -- Vice President Dan QuayleArticle: 16394
Incredibly painful? You've never had to push very hard on an FPGA, have you?. Wean yourself from the GUI and learn the tools, you'll be better off. When you run into a design that you really have to grind on to fit and make speed you'll appreciate the power that the Xilinx tools give vs. Altera (where if it doesn't work there's just not much you can do about it). Blame the GUI problems on Microsoft not Xilinx. There's not a Windows application in existence that runs on all Windows machines. Bob Sefton "Adam J. Elbirt" wrote: > > Actually I am running 95 version B. It's in par, not map. I ended up having to > run the tools manually from the command line which was incredibly painful. > Guess I'll be using Altera for my next design. > > Adam >Article: 16395
Actually Bob I know the tools inside and out for Actel, Lucent, Xilinx, and Altera. I had to develop all of the flows for integration with Viewlogic tools a few years back so believe me when I say I know command line options a-plenty. However, I WILL blame GUI problems on Xilinx - in the end, they are the ones producing the product and if it has to rely on Microsoft tools then you had better make it work within the environment. Just because I use the GUI and its convenience has no bearing on my knowledge of the tools. Adam Bob Sefton wrote: > Incredibly painful? You've never had to push very hard on an FPGA, > have you?. Wean yourself from the GUI and learn the tools, you'll > be better off. When you run into a design that you really have to > grind on to fit and make speed you'll appreciate the power that > the Xilinx tools give vs. Altera (where if it doesn't work there's > just not much you can do about it). Blame the GUI problems on > Microsoft not Xilinx. There's not a Windows application in > existence that runs on all Windows machines. > > Bob Sefton > > "Adam J. Elbirt" wrote: > > > > Actually I am running 95 version B. It's in par, not map. I ended up having to > > run the tools manually from the command line which was incredibly painful. > > Guess I'll be using Altera for my next design. > > > > Adam > >Article: 16396
Teach me, I don't understand how? Leon Heller wrote: > Uday Godbole wrote in message <7htv83$fkj$1@usenet50.supernews.com>... > >Hi, > > > >I need to use a schmitt trigger gate. Can it be made on a Xilinx 9536 > cpld? > >I have their starter kit, but the schematic capture software does not seem > >to have one in the library.. Also, can an open collector output be > simulated > >on this device? > > I created a Schmitt trigger once on a Lattice CPLD, using schematic entry. > You can do it with a 2-input NAND and an inverter. > > LeonArticle: 16397
Sorry if I sound to pessimistic. I did meant it can't be solved, just tha= t you can't do it without external components as you say. Just remember this is a rat= her slow compared to max input rate. Hi Peter Peter Alfke wrote: > Peter S=F8rensen wrote: > > > You can't make a schmitt trigger by code as it is an analog function = and the > > code is digital. > > Some devices may have schmitt trigger I/O's, but they are rare as the= y are > > slower as normal I/O. > > It's not quite that bad.If you are really desperate to put hysteresis o= n a > certain input, and you are willing to sacrifice an extra output, and us= e two > external resistors, do the following: > Drive the extra output with the signal ( uninverted) that you receive. > Externally connect a 100 kilohm resistor from this output to the input.= Then > drive the input through a 10 kilohm resistor. The analog resistor divid= er is now > outside the chip, and you can of course play with different resistor va= lues and > ratios. > Not elegant, but better than giving up. > > Peter Alfke, Xilinx ApplicationsArticle: 16398
Right, god point Jamie, I have had the same experience, it took 1 hour instead of 8. Altera also state this their documentation somewhere. nb: I you have many constrains you can disable them instead of just deleting them. Hi Peter Jamie Lokier wrote: > Try compiling without an fmax timing constraint. > Then run timing analysis to see what frequency you got. > > In my experience compiles are much faster without an fmax constraint, > (like 10 minutes instead of 9 hours!), and the resulting fmax is often > good enough. Sometimes it is even better than with the constraint. > > -- JamieArticle: 16399
Dominic Reitman wrote: > My design currently consists of four entities. The four entities when > synthesized and implemented independently have a CLB count of 10, 17, 4, > and 9. When I combine the four entities the new CLB count is 156. The > whole design is straight combinational logic. The first two entities > are 8 functions of 8 variables each, they each use a case statement with > 256 possibilaties. The third entity is a simple multiplexer which > selects 1 of 2 8-bit vectors. The last entity is a 4-to-1 multiplexor > along with some shifts. > > Is there any way to have FPGA Express synthesize an entity of a design > without trying to optimize it with the components surrounding it? I > think that FPGA Express is combining the logic used in the first two > entities with the multiplexer which ruins the symetry within the logic > of the first two entities. > > Any help or ideas on the matter will be greatly appreciated. > Thanks in advance, > Dominic Hello I have never tried that but you can save your entities independently as macros. Instantiate them in the top level file. May an option permit to keep each of them as a routed block. Sorry, this is only a track. How was your P&R option: optimize for delay or area? Allow logic replication? Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm
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