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On Thu, 08 Oct 1998 04:50:37 GMT, allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) wrote: >Will it be 1076.6 compliant? forget it - 1076.6 is a total waste of paper (and will hopefully never be ratified). it is, to say the least, ambivalent about whether it's based on '87 or '93. for all practical purposes, it's a limited subset of '87 (and, in fact, FPGA express is already pretty close to being compliant anyway). >I got a rude suprise once when trying to port some code from Galileo >to FPGA Express. Couldn't convince the Synopsys tools to believe that >a two dimensional array of std_logic was a valid type for a generic >parameter. 1076.6 doesn't allow multi-dimensional arrays either. evanArticle: 12301
On Wed, 7 Oct 1998 14:55:00 -0700, "Andy Peters" <apeters@noao.edu.NOSPAM> wrote: >The "gotcha" with PERIOD is that you have to place it on the clock net AFTER >the BUFGx, so you're outta luck if you're using VHDL (unless you want to >look at the .xnf file and find out what the buffered clock net is called). >It's noted in the timing constraints presentation that that little "feature" >is a known problem that will be fixed eventually. or just instantiate your BUFGs, in which case it's easy. i personally prefer this - it's portable among all tools, and i don't like the synthesiser putting in BUFGs for me. evanArticle: 12302
here's a different spin on all this. (1) you've got two conflicting constraints: a period constraint at 25ns, and a FROM:TO (which you don't show) at 20ns. this isn't a good idea, and leads to your prioritisation problem and conflicting frequency results. in general, always use PERIOD, and just use FROM:TO to specify specific over-rides, ie. signals originating in a different clock domain, multi-cycles, or whatever. (2) there wasn't a specific problem with PERIOD in 1.4; just a generic problem with any timespecs being traced through a BUFG (i haven't got 1.5 yet, and i don't know if the generic problem has been fixed). (3) you create a timegroup which includes both the input to the clock buffer, and the output. this is again asking for problems - why not just: > NET clk* TNM = fsa_grp; > TIMESPEC TS01 = PERIOD fsa_grp 25ns; or just on the input clock assuming the 1.5 fix? and remove the FROM:TO spec. (4) i would have guessed that a design which fails timespecs will still run ok at the lower reported frequency, but it's just a guess (but maybe the stubs are the result of an inadequate cleanup after failing?) (5) i'm pretty sure that you can ignore the clock skew warning, as long as you're sure that there's no problem on that net. i've had the same warning on a design in which the offending net wasn't used as a clock anywhere. evanArticle: 12303
Has anyone noticed problems in re-compiling designs that worked in v8.0 of maxplus2 under v9.01 and found comilation times went throught the roof even to the point excess ( I aborted after 100 hours v9 vs 1 hour under v8 ). Eric Pearson - Focus SystemsArticle: 12304
Derek Palmer <derekp@synopsys.com> writes:
>Let's make rumor fact!
>FPGA Express 3.0 will have VHDL 93 support.
>Available on the Synopsys web site at the end of Oct.
>Derek Palmer
>FPGA Express Team
>Synopsys Corporation.
And it's only 1998. Talk about support!
Cheers,
Jake
>Andy Peters wrote:
>> Hans Lindkvist wrote in message <3614BD09.E32A0E14@ldecs.ericsson.se>...
>> Rickman wrote:
>> Jake Janovetz wrote:
>> One possibly big difference, depending on whether you have existing
>> code, is that Synopsys does not support VHDL-93. They seem to be
>> pretty
>> stuck in VHDL-87.
>> Otherwise, I can only stay that Synopsys is what comes with Xilinx
>> Foundation, so a lot of Xilinx users have it! ;)
>>
>> I've heard from a Synopsys representative that vhdl-93 support is close.
>> I just got the Xilinx Foundation 1.5 tools w/Synopsys FPGA Express, and
>> there's support for *some* VHDL'93 things, like rising_edge() and
>> falling_edge() and myprocess : process (yadda) IS.
>>
>> A start.
>>
>> -andy
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 12305Have a look at the Atlas section on Altera's site (www.altera.com) and if this doesn't help email your problem to sos@altera.com. AlunArticle: 12306
Schools can get them for free. Simon ================================================= "F. Arnold" <fa218@ural2.hszk.bme.hu> wrote: >Hi! > >Where or How can I free get Xilinx Foundation Base? > >Thanks, > Arnold > > Design Your Own MicroProcessor(tm) http://www/tefbbs.com/spacetime/index.htmArticle: 12307
At these "costs", the weak link is probably the design engineer. Hiring him or her away (or the whole team) at a fraction of the cost would be the easy solution. :) Also, if the devices are _really_ that secure, Actel should offer a big cash prize to "crack" a secured device. A $250,000 prize should be risk-free for Actel according to their arguments. Imagine the marketing messages they could make then. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- >Daniel K Elftmann wrote: > >> Some actual number of antifuses for the Actel devices are as follows: >> Arch Fuses Cost@$500 >> A1010 -> 112,000 $56,000,000 >> A1020 -> 186,000 $93,000,000 >> A1225 -> 250,000 $125,000,000 >> A1240 -> 400,000 $200,000,000 >> A1280 -> 750,000 $375,000,000 >> >> Still not prices that the typical hacker can afford in my opinion. >> > >> >Article: 12308
Hi!
Where or How can I free get Xilinx Foundation Base?
Thanks,
Arnold
Article: 12309Hello, I have been programming Altera FPGA's for several years using the altera HDL and graphic designs. We are considering transferring new and some existing designs to either VHDL or Verilog. I don't know anything about either language, and I would like a list of pro's and con's about each. Craig Jacobs Systems Engineer Advanced Product Development Automotive Systems Lab -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12310
ems@nospam.riverside-machines.com wrote in message <361ca485.10782062@news.dial.pipex.com>... >here's a different spin on all this. > >(1) you've got two conflicting constraints: a period constraint at >25ns, and a FROM:TO (which you don't show) at 20ns. this isn't a good >idea, and leads to your prioritisation problem and conflicting >frequency results. in general, always use PERIOD, and just use FROM:TO >to specify specific over-rides, ie. signals originating in a different >clock domain, multi-cycles, or whatever. Good idea. Now, I wish that the Synopsys constraint-entry spreadsheet knew from PERIOD (and TIG, and THRU, and TPSYNC...). It generates FROM:TOs for all possible combinations of clocking and inputs: input pads to rising edge clocks, input pads to falling edge clocks, rising-edge clocks to rising-edge, falling to falling, rising to falling, falling to rising, falling to output, rising to output, input to output (whew!). So you end up with about twenty FROM:TO constraints when all you'd need is one PERIOD constraint and your two-phase clock stuff is all taken care of. >(2) there wasn't a specific problem with PERIOD in 1.4; just a generic >problem with any timespecs being traced through a BUFG (i haven't got >1.5 yet, and i don't know if the generic problem has been fixed). I think the "fix" is the added TNM_NET which lets you trace from input pads through the BUFG. >(4) i would have guessed that a design which fails timespecs will >still run ok at the lower reported frequency, but it's just a guess >(but maybe the stubs are the result of an inadequate cleanup after >failing?) I always thought that it should run at the slower speed if it finishes P+R, but since we set timing constraints for a reason, I've never slowed my clock down to try it! -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 520-318-8191 apeters@noao.edu >Article: 12311
Kartheepan, Madasamy wrote in message <361C5B37.7ED02EF@t-three.com>... >Thank you for the last two informative emails. I definitely understand the need >to have a different design philosophy when tackling hardware implementations of >signal processing functions.A little off topic, I want to bounce this off you. >I have been thinking of putting Viterbi algorithm for finding MLS onto an >FPGA. Have you come across similar implementations and what is your take on the >feasibility of putting the algorithm handling 32 states (5 memory elements) on >a 100K FPGA?. I would appreciate any input from you, Just a comment: are you going to put the memory to store your search data on-chip or in off-chip RAM? I know that there are custom Viterbi decoder chips out there; not sure what they do for memory. -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 520-318-8191 apeters@noao.eduArticle: 12312
Hello, I am using F1.4 Xilinx Foundation Software to programm a XC95216 CPLD. The abel code has a pin assignment like name pin #; but the fitter report tells me a different assignment then I have written it down in the code. In the design manager, the option "Use Design Location Constrains" is ON (At the end, it is same assignment if its OFF). The edif-file look correct. It is like this option has no effect. Do anyone know this problem and how to solve it? Regards, Ingo FroehlichArticle: 12313
Hi all:
Does anyone know the delay time of one LCELL,
if I implement an VHDL statement
U1: LCELL(CLK1, CLK2);
the CLK2 will be delay how many ns?
John Huang
Article: 12314> > here's a different spin on all this. > > (1) you've got two conflicting constraints: a period constraint at > 25ns, and a FROM:TO (which you don't show) at 20ns. this isn't a good > idea, and leads to your prioritisation problem and conflicting > frequency results. in general, always use PERIOD, and just use FROM:TO > to specify specific over-rides, ie. signals originating in a different > clock domain, multi-cycles, or whatever. > What you suggested is exactly what I tried this morning before I checked the newsgroup. I simply removed the FROM:TO constraint and only kept one PERIOD constraint on the clock net that is attached at the output of the BUFG (which has been instantiated manually). I also had to increase the period to 30 ns in order to achieve an operating frequency of about 33MHz with no timing errors. > > (4) i would have guessed that a design which fails timespecs will > still run ok at the lower reported frequency, but it's just a guess > (but maybe the stubs are the result of an inadequate cleanup after > failing?) The new implementation does not report any stubs, fortunately! You are probably right that the cleanup might not have been done adequately after ppr. > > (5) i'm pretty sure that you can ignore the clock skew warning, as > long as you're sure that there's no problem on that net. i've had the > same warning on a design in which the offending net wasn't used as a > clock anywhere. I finally pinpointed the warning to a part of my design driven by a clock which is 1/8th of the fastest input clock. I guess this warning can't be avoided in this case since the 1/8 clock has to be implemented somehow in the chip (using F/G/H maps). But this is fine since the required frequency is much lower. It's odd though that F1.4 and previous don't produce this warning. If I have problems with skew, I'll just set a MAXSKEW attribute on that clock net and hope that it will fix them Thanks for your input. NestorArticle: 12315
A few more notes... > > > >What I did is use the xc4000 library from Synplify (I don't know what > >tool you are using) to instantiate the BUFG and connect it as: > > > >fsa -> BUFG -> clk_net > > Is Synplify smart enough to automatically insert clock buffers? FPGA Express > (which I use) does; so does Metamor. Synplify can insert them automatically, but given all the different types of small problems I have seen and read about when implementation in FPGAs, I always instantiate special components (BUFG's, or other) manual in the VHDL code or in the schematic. Also, the STARTUP block is also inserted automatically in Synplify, provided that option is selected. I still manually instantiate the STARTUP block because I like to see it in the schematic that Synplify generates. Components that Synplify instantiates automatically are not displayed on the RTL view it produces, but includes them in the edif or xnf it generates. > > >and use the following constraints to cover all the nets renamed to > >clk_net_c or something similar (luckily Synplify only appends characters > >to the VHDL net names): > > > >NET fsa* TNM = fsa_grp; > >NET clk* TNM = fsa_grp; > >TIMESPEC TS01 = PERIOD fsa_grp 25ns; > > > >I think I may need to use the new timing name net constraint as: > > > >NET fsa* TNM_NET = fsa_grp; > >NET clk* TNM_NET = fsa_grp; > >TIMESPEC TS01 = PERIOD fsa_grp 25ns; > > Try it and let us know what happens. Not much difference. The operating frequency still ended up being around 33MHz. Thanks again. NestorArticle: 12316
Hey, all:
I've been futzing with F1.5 and FPGA Express for about a week now...here's
some observations:
1) Supposedly there's a way to keep revs of source code with implementation
revs but I can't figure out how to do it.
2) In Synthesis Options for FPGA Express, when I checked the box labelled
"Export Timing Constraint," I got SIXTY-TWO timespecs, ranging from the
sublime (pads to pads) to the ridiculous (output tristate flipflops to
output tristate flipflops????).
3) After synthesizing, click on the implementation button and then choose
"Options" for physical implementation settings. It won't let you choose a
Simulation Program Template other than Foundation EDIF. Even if you select
Generic VHDL or ModelSim VHDL, once you start the implementation it throws
your choice away and chooses Foundation EDIF.
4) The could-be-nifty Constraints Editor GUI (not accessible from the
Project Manager; rather it's buried in the program manager/start menu under
Programs->Xilinx->Accessories->Constraints Editor) requires as input both a
.UCF AND a .NGD file. Unfortunately, the .NGD file isn't available until
after you do an implementation.
5) Something got into my .UCF file and changed my timing ignore for
bidirectional data bus pins
TIMESPEC "TS_FALSE" = FROM "FFS" THRU "ramthru" TO "FFS" TIG;
to
TIMESPEC "TS_FALSE" = FROM "FFS" TO "FFS" TIG;
which had the amusing-yet-useless effect of cause all timing constraints to
be ignored by PPR.
-andy
--------------------------------------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520-318-8191
apeters@noao.edu
"Stupidity is like hydrogen: it's universal. It's everywhere and in
everything."
-- Frank Zappa
Article: 12317LCell time depends on Component family and speed grade (10K, 10KA, 10KE, -4, -3, -2, -1). It is not a good design rule to use LCELL to implement delay. Use it only if you have no other solution Regards On Fri, 9 Oct 1998 01:08:15 +0800, "John Huang" <hungi@tpts4.seed.net.tw> wrote: >Hi all: > > Does anyone know the delay time of one LCELL, >if I implement an VHDL statement > > U1: LCELL(CLK1, CLK2); > > the CLK2 will be delay how many ns? > > John Huang > > --- Pour me contacter enlever "removethis." de mon adresse Email. To contact me, remove "removethis." from my Email address.Article: 12318
I have compared compilation times between version 8.14, 8.2, 8.3 and 9.01 and have seen no significative difference with one of my designs written in AHDL. (95% full 10K50A compiles in approx. 7' on a PII333 with 192MBytes of RAM and Win NT4). However I must point out that I have no timing constraints on my design. I think the compilation time can increase if you have timing constraints. Regards. E. JOLLY On 8 Oct 1998 13:07:26 GMT, "Eric Pearson" <ecp@focus-systems.nospam.on.ca> wrote: >Has anyone noticed problems in re-compiling designs that worked in v8.0 of >maxplus2 under v9.01 and found comilation times went throught the roof even >to the point excess ( I aborted after 100 hours v9 vs 1 hour under v8 ). > >Eric Pearson - Focus Systems > --- Pour me contacter enlever "removethis." de mon adresse Email. To contact me, remove "removethis." from my Email address.Article: 12319
Please help I want to design IP cores for FPGAs. Please can you point to where to start from, what should I read, where are the basics of IP cores design methods, what are the standards,where could I get the tools for this reason and anything related to this topic thanks in advanceArticle: 12320
I have a nifty - I think - tool for designing cores. Check out: Design Your Own MicroProcessor(tm) http://www/tefbbs.com/spacetime/index.htmArticle: 12321
Dear all, I am looking for a good VHDL development (compiling, simulation, gate-level sim/FSM support, Testbench generator) software tool. I need it to have a comfortable interface to maxplus2 for exporting compiled designs for synthesis in Altera's devices. I've been looking around lately and I've evaluated Aldec's "Active-VHDL" and quite happy with it, but I have a slow internet connection, therefore, before I start downloading tens of megabytes again, I would like to know if there are any other compact software tools worth looking at...? Anyone got any experience with Aldec's tool? Are the big ones (Synopsys, Examplar..) worth the investment? -- Ido Kleinman. kleinn@mail.biu.ac.ilArticle: 12322
Dear all, I am looking for a good VHDL development (compiling, simulation, gate-level sim/FSM support, Testbench generator) software tool. I need it to have a comfortable interface to maxplus2 for exporting compiled designs for synthesis in Altera's devices. I've been looking around lately and I've evaluated Aldec's "Active-VHDL" and quite happy with it, but I have a slow internet connection, therefore, before I start downloading tens of megabytes again, I would like to know if there are any other compact software tools worth looking at...? Anyone got any experience with Aldec's tool? Are the big ones (Synopsys, Examplar..) worth the investment? -- Ido Kleinman. kleinn@mail.biu.ac.ilArticle: 12323
Start with the Reuse Methodology Manual, you can get it from www.computerliteracy.com J. Khatib <jamil.khatib@pemail.net> wrote in article <361e229f.261872@news.planet.edu>... > Please help > > I want to design IP cores for FPGAs. Please can you point to where to > start from, what should I read, where are the basics of IP cores > design methods, what are the standards,where could I get the tools for > this reason and anything related to this topic > > thanks in advance >Article: 12324
Hi, Anyone knows how do I activate VHDL93 compiling ability in MaxPlus2? I wrote some code with direct component instanciation that would compile nice in Aldec, but won't in Maxplus... MaxPlus specifies many VHDL93 constructs in its help so I guess the VHDL93 compiling ability exists. (I have the full software, no "unavailable features"...) -- Ido Kleinman. kleinn@mail.biu.ac.il
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z