Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Jonathan Bromley <jsebromley@brookes.ac.uk> wrote: :David R Brooks wrote: :<snip count sequence for 6-bit twisted ring counter> :> This has of course, used 12 of the 64 states possible in 6 bits. All :> the other states are illegal. If inadvertently entered, the counter :> will usually continue cycling through illegal states. A clean reset :> will start it off right, but if your application must be sure to :> recover from faults, you'll need to trap those illegal states. : :Exactly so. To do this you need to :a) determine all the possible cycles of illegal states : (don't forget there may be multiple non-intersecting cycles) :b) invent some combinatorial gubbins that will identify : at least one state in EACH of these cycles, and NO states : in the wanted cycle :c) use that logic to force the counter into one of the legal : states and/or raise a fault flag : [snip] In the limited case of a Johnson counter, consider the waveform at any arbitrary bit position. It's a 50:50 squarewave, with period 2N (for N-bit counter). It's pretty simple to spot a departure from that (more than 1 rising & 1 falling edge per 2N clocks is probably enough) and trap it. This must work, since all illegal states contain more than 1 run each of zeros & 1's. -- Dave Brooks <http://www.iinet.net.au/~daveb> PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or serversArticle: 12251
In article <6vanlm$7dt$1@europa.frii.com>, "Darren File" <darrenfi@ftc2.aei.com> wrote: >I have a need for incorporating some interrupt controller functionality into >a Xilinx FPGA design (to replace an existing 82C59). I've looked at the >design which is available as part of the Xilinx CORE package (via a 3rd >party), but it is $3000 without source and $20,000 with source. In >addition, it still has the limitation that interrupts are globally >configured to be either edge-triggered or level sensitive, and this >limitation is causing some problems in my design. > >Does anyone have source or schematics for the bare-bones interrupt handler >functionality? I'd appreciate any help or any leads. > >Thanks, > >Darren > > Take a look at the core at http://www.macrocad.com I implemented this core originally in viewlogic schematics for a Toshiba ASIC, later I did the verilog port. Macrocad has since also converted it to VHDL. The core has been proven in silicon multiple times and comes with a full set of high coverage test vectors. I won't go beyond my bounds and discuss prices for the core, but I'm 99.9% certain that it has been implemented in a Xilinx device. In terms of global configuration of either edge-triggered or level sensitive that is the way it will come out of the box, but it is a trivial task to modify this to be controllable on a channel by channel basis controlled by a write/read register; I know this because I modified this exact core for an EISA implementation back in 1992-3. Hope this helps.Article: 12252
In article <361AA0CB.332F64F8@algotronix.com>, Tom Kean <tom@algotronix.com> wrote: >This is a multi-part message in MIME format. >--------------DDBDB1AB852CD888C58C5B70 >Content-Type: text/plain; charset=us-ascii >Content-Transfer-Encoding: 7bit > > > >Botond Kardos wrote: > >> ..... >> This paper claims that one needs to make an electron microscope shot >> to get every simple antifuse, and this photos are destructive and quite >> expensive, so breaking an Actel antifuse FPGA wich contains about 50,000 >> antifuses might cost $50 million. >> Is this true ? Aren't there other ways for reprogramming or >> eliminating the read-out protection (it also may be a single or more >> antifuses) for example with an ion-beam ? > >Here's my 2p worth: the Actel paper starts out as a reasonable if >superficialintroduction to design security. Then it gradually gets into the >realms of the >ridiculous as the marketing department takes over. Ah yes, marketing does have it's stamp all over this, but when they find an advantage one cannot hold them back nor blame them for trying to exploit this advantage. > >The figure on Actel's slide 33 is actually $500M to crack an antifuse FPGA >based on $1000 per picture and 500,000 antifuses. > >I bet you anything you like that if you ask for 500,000 pictures the lab >will give >you a price break :-) > Ok, a 50% price cut, and then there is the time for each picture which will also be a factor. Time is money. Some actual number of antifuses for the Actel devices are as follows: Arch Fuses Cost@$500 A1010 -> 112,000 $56,000,000 A1020 -> 186,000 $93,000,000 A1225 -> 250,000 $125,000,000 A1240 -> 400,000 $200,000,000 A1280 -> 750,000 $375,000,000 Still not prices that the typical hacker can afford in my opinion. I've not yet seen any documentation that tells me these numbers for the DX or SX devices. If I get them I'll post them later, if anyone is still interested. >More seriously I don't think anybody would ever try to take pictures of >every antifuse >to figure out the configuration of an FPGA. Using an Ion beam machine to >get at the programming circuitry would be a good first step: once the >programming circuitry >is active the antifuse is no safer than an SRAM. > >Tom. > Perhaps a study of the antifuse programming algorithms (which I won't go into here) would help you to understand this, but in short the state of each individual antifuse cannot be determined even from the programming circuitry once the entire device has been programmed, so take out your camera again. As it has been explained to me, each fuse is verified after it is programmed, but programming of subsequent fuses removes the capability to access inner device fuses, which is the reason the checksum is programmed into the device for later identification versus just reading out the state of each fuse and re-calculating the checksum. Guru note on the checksum: http://www.actel.com/apps/guru/sep97/rp237.html Just out of curiosity, what would the cost of an Ion beam machine be and are they readily available? As an applications engineer, I really don't know the answer to this. ************************************************************************************************** Tom, I don't see how antifuse devices have any application in reconfigurable computing? Is there still a bit of Xilinx left in you that just can't have an antifuse advantage being posted in this group? Don't mean to be smug. I'm just trying to understand your biases. Good luck to Algotronix, I wish you well. Daniel K. Elftmann Actel Corporation Northeast Field Applications EngineerArticle: 12253
O >> I would go for the FPGA over the DSP when DSP looks like an overkill >> for an embedded application. >I agree in your analysis. But I disagree with your conclusions. > Well it is my bad that I did not explain what I was trying to say. My comparison was against FPGAs with 100K gates, with a typical 50% utilization (although I have never seen that much utilization just by relying on synthesis, P/R tools). At Audio Rates ( atmost 48KHz) or Telephony rates (8KHz), say a full blown 7 band Equalizer or a Demodulator algorithm, would take only a handful of MIPS on any commercial DSP, say running at 40MHz. However, in hardware it can easily chew up significant part of the FPGA. I really find it difficult to realize more MIPS on FPGA than a DSP, atleast at audio/telephony sampling rates. But hey, I am willing to think otherwise and would like to learn your side of the story. Nevertheless, I can visualise FPGAs doing more work at higher sampling (data) rates. This is because there is no major difference in gate count(except for timing, p/r issues) between a sampling rate of 8KHz or 48 KHz for a prescribed design. The DSP's MIPS might not amount to anything at MHz rates but at lower sampling rates, a lot of processing can be crammed within the available MIPS. Recently we tried to put some signal processing stuff into FPGAs and soon ran out of gates. I am still comfortable with placing FPGAs between micro controllers and DSPs but like I said, willing to know more, Kartheepan, MArticle: 12254
kartheepan@t-three.com (M Kartheepan) wrote: >Well it is my bad that I did not explain what I was trying to say. My >comparison was against FPGAs with 100K gates, with a typical 50% >utilization (although I have never seen that much utilization just by >relying on synthesis, P/R tools). I have done an 8 bit micro-controller on a Flex 10K100 with %70 utilization with Verilog and MaxPlus2. Routing fails around %80. And this industry micro-controller core has very big decoders which make routing more difficult. muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12255
rk wrote: > > hi rick, > > we went through this a number of years ago, and again more recently. you do > need to have transitions from all of the states ... they really must be > handled. the state info + extra bit approach is not sufficient for all > cases. for example, suppose that you have an "upset" on the clock line, > giving a runt pulse, tossing you into an illegal state or sequence of > states. the edac schemes typically work based on the hamming distance of > the code implemented. other examples that can cause multiple upsets are > drop outs on the power bus, esd, certain man-initiated events, etc., etc. I guess my point is that fact that even if you handle the illegal state by transitioning into a legal state, you have had "incorrect operation" for at least one state. This can result in the loss of data, or damage to devices being controlled, or corruption of other parts of the electronic circuit. So the transition to correct states is not adequate. It would seem to me that if you can't tolerate ANY problems with a state machine, you should deal with the causes rather than the effects. Power problems, ESD, and bad clocking can all be handled by proper design of that part of the circuit. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12256
First, don't skimp on your simulator! We use Modelsim PE -VHDL- under Win95, and highly recommend it. We routinely simulate over a dozen good size structural models of FPGA's and CPLD's all running together in our system test bench. GREAT tool, don't know how I ever got along without it. We use Exemplar Galileo 4.2.2 and Synplicity Synplify 5.06 for synthesis. Of the two, I have to say that Exemplar is more robust. We've had quite a few problems with Synplify, although this new version seems better... Tom Meagher John Huang wrote in message <6uctfk$ht4$1@news.seed.net.tw>... >I want to buy a FPGA tool, do you recommand which >one is better, how about Accolade and Aldec? > >John Huang > > >Article: 12257
hi rick,
yes, i agree. and i'm trying to figure out, 'er, what to do about it?' some
state machines for critical systems can't stop. ever. no one there to hit a
reset button. etc., etc. and dealing with the causes and blocking all of them is
difficult and hard to "guarantee." trying to make the circuits immune as much as
possible rather than detect and correct is, i agree, in general the way to go.
however, a good state machine should do it's best and be robust - not lock up or
stay in an illegal condition, which was the point of my reply, EDAC would only
handle a subset of the class of errors that can occur.
for soft upsets, which someone said to start this thread, that's relatively
easy to fix by design (say TMR - and not gonna open up the antifuse-sram debate
again :-) or by technology choose a seu-hard fpga (of course, there are none in
existence, yet, but that's another story).
of course, if you can get a node upset in a flip-flop, you can get one upset
in a clock buffer too, which propagates runt pulses all over the chip, especially
with the newer, faster technologies. note this would be from environment, not a
bad oscillator. seen them, they make a mess. how do you deal with that? not
very easily, it's expensive. you can again do a circuit design fix (really messy)
or a technology based design fix. mission research corporation has done a design
for exactly that (patent submitted) which relies on a multi-phase hardened-clock
scheme built into the structure of the fpga, which will protect against short term
transients (i think on the order of a nanosecond). i worked (day job) on
improving an existing design to this effect, got over an order of magnitude
improvement, but hard to eliminate 100% w/out a complete overhaul.
partial power dropouts and recoveries, sudden large bursts of energy, etc.,
are harder to deal with.
my basic point, and your edac idea was a good one, was that there should be,
for critical systems, more than error detection and correction - and my concern is
that some of the synthesis methodologies make state machines less robust than a
human designer would and the structure of the machine is often not in plain view,
as it is with a schematic [yeah, i like schematics, i'm a geezer]. i do wish to
design circuits that never lock up and self-clear under any possible condition.
where possible and it can be made bulletproof, it should be done, with a good
example the implementation of JTAG 1149.1 tap controllers, with the optional hard
reset pin. w/out it, and an "oops" occurs, the ieee will guarantee that after no
more than 5 ticks of the TCK, you'll be safe home. bad plan and very avoidable.
can get ugly if you the tap controller goes through the UPDATE-IR state, with the
IEEE making the holding register's contents undefined in the TEST-LOGIC-RESET
state.
my apologies for typos, terseness, whatever, typed in from memory, it's late.
have a good evening,
rk
____________________________
Rickman wrote:
> rk wrote:
> >
> > hi rick,
> >
> > we went through this a number of years ago, and again more recently. you do
> > need to have transitions from all of the states ... they really must be
> > handled. the state info + extra bit approach is not sufficient for all
> > cases. for example, suppose that you have an "upset" on the clock line,
> > giving a runt pulse, tossing you into an illegal state or sequence of
> > states. the edac schemes typically work based on the hamming distance of
> > the code implemented. other examples that can cause multiple upsets are
> > drop outs on the power bus, esd, certain man-initiated events, etc., etc.
>
> I guess my point is that fact that even if you handle the illegal state
> by transitioning into a legal state, you have had "incorrect operation"
> for at least one state. This can result in the loss of data, or damage
> to devices being controlled, or corruption of other parts of the
> electronic circuit. So the transition to correct states is not adequate.
>
> It would seem to me that if you can't tolerate ANY problems with a state
> machine, you should deal with the causes rather than the effects. Power
> problems, ESD, and bad clocking can all be handled by proper design of
> that part of the circuit.
>
> --
>
> Rick Collins
>
> redsp@XYusa.net
>
> remove the XY to email me.
Article: 12258David R Brooks wrote: > In the limited case of a Johnson counter, consider the waveform at > any arbitrary bit position. It's a 50:50 squarewave, with period 2N > (for N-bit counter). It's pretty simple to spot a departure from that > (more than 1 rising & 1 falling edge per 2N clocks is probably enough) > and trap it. > This must work, since all illegal states contain more than 1 run each > of zeros & 1's. David, this is exactly the point I was trying to make, but from the other end: Of course your functional logic is correct. But let's see now.... you made a Johnson counter because you wanted the fastest possible logic for a modulo-2N counter.... and to verify it's not in an illegal state, you need another modulo-2N counter.... which of course must go as fast as the original Johnson counter. Sounds like a problem to me. Peter Alfke e-mailed me a very important point about how easy it is to use Xilinx CLBs to identify illegal states; that post hasn't hit the NG yet (at least not at my site) so maybe Peter forgot to post it to the group too; if so, Peter, could you re-post it? it was worth reading, especially for someone like me who is not a Xilinx user (confession of utter unemployability?). Other posters have pointed out that a screwed-up state machine (or anything) that subsequently recovers is, in a high-rel system, hardly any better than a screwed-up state machine that stays screwed-up. I beg to differ. OK, so the original problem may have corrupted some data or transaction somewhere, but at least your system is still running and you have a sporting chance of detecting and correcting the error at some higher level (maybe even software, if that isn't heretical here!) where it is easier to implement redundancy. And there are many situations (graphics systems, for example) where transient problems are unpleasant but far from catastrophic, whereas a locked-up state machine could mean effective total failure of the system. I wonder if there are any locked-up cycles in the state machines in my car's engine management? Probably not, it's implemented in software :-) Jonathan Bromley --Article: 12259
Rickman wrote: > > elmousa@my-dejanews.com wrote: > > I am now looking for an FPGA that supports in system programmability > > supported by software tools that can allow me to automate the design > > architecture of the FPGA with minimum lay i.e. not technical user > > intervention. > > The problem to this approach will be that you have to work within the > subset of VHDL supported for synthesis by your tool. But if you can > produce C code from your inputs, you should be able to produce VHDL > code. The trick will be producing GOOD VHDL code. You could consider Handel-C which is a parallel C-like language that knows how to target Xilinx FPGAs which of course are reconfigurable. I don't know much about ANNs but I have a feeling that Handel-C might be a lot less grief than VHDL. It's not cheap but if you are in academia you may be able to get big discounts. Have a look at www.embedded-solutions.ltd.uk for more info. The company is a spinoff from Oxford Univ's hardware compilation work. NG police please note: I have no commercial connection with either organisation! Jonathan Bromley --Article: 12260
Nestor Caouras wrote: > Hi everyone. > > I was wondering if anyone has tried Xilinx's FROM:TO user constraint. I > have a VHDL design that I would like to run at 40MHz (period of 25ns). > I read on Xilinx's homepage (on one of their online slide presentations) > that I can use the following user constraint to ensure that the design > will run at 25MHz from flip flop to flop: > > TIMESPEC TS04 = FROM FFS to FFS 25ns; > > I have a few questions about this constraint. > 1) From flip flop to flip flip assumes flip flops connected via the same > path? > > 25ns 25ns > FF1-------->FF2---------->FF3 > > 2) Does this mean that if the design meets this 25ns constraint then > that data from one flip to another arranged as in 1) will only have 25ns > delay between them? I'm assuming this is only true for the internal flip > flops, not connected to IO pads (IPAD to FF, or FF to OPAD). > > I tried compiling a design using this constraint, and I got some numbers > that I was not sure about. > The part I used was an xc4028EX-3 and I got the following results: > > Pre place-and-route timing under this constraint : 181.3MHz > Post place-and-route timing under this constraint : 41.3 MHz > > I had also used a 25ns PERIOD constraint on my main clock net > > Please post a reply to this newsgroup or email me if anyone knows more > about this constraint. > > Many thanks in advance. > > -- > Nestor Caouras > nestor@ece.concordia.ca > http://www.ece.concordia.ca/~nestor/addr.html > |-------------------------------------------| > | Dept. of Electrical and Computer Eng. | > | Concordia University | > | 1455 de Maisonneuve Blvd (West) | > | Montreal, Quebec, Canada H3G 1M8. | > | Tel: (514)848-8784 Fax: (514)848-2802 | > |-------------------------------------------| The From/To FFS->FFS constraint implies that in the following situation: FF1 ---> Combinatorial Logic ----> FF2 The sum of FF1's Tco + Comb Logic delay + FF2's Tsu < = 25 nsec. For post place & route 2 routing delays FF1->CL & CL->FF2 are also added in. Note that the PERIOD constraint on CLKx implies a From/To constraint of the type: TSxx: FROM FFS(Connected to CLKx):TO:FFS(Connected to CLKx): 25Article: 12261
In article <361A839D.7BC75B74@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > elmousa@my-dejanews.com wrote: > > > > I work in the field of neural network hardware implementation. I used the > > Lattice isp (in-system programmable) FPGAs with excellent results. > > > > I am now looking for an FPGA that supports in system programmability and is > > supported by software tools that can allow me to automate the design > > architecture of the FPGA with minimum lay i.e. not technical user > > intervention. Perhaps, the design software will allow complex scripting, > > and/or linking to a high level langauge > > > > The goal is to design a neural hardware system that is general purpose, > > mutliconfigurable and user friendly. I believe that FPGAs will allow me to do > > this when linked with a special neural processor. > > > > Any ideas, pointers, feedback will be appreciated. > > I think I understand what you are trying to do and it may be possible. > The most likely method would be to use your input program to analyze > your user requirements and produce VHDL as output. The VHDL can then be > compiled to a chip by means of any of the many VHDL compiliers > available. Thanks for your reply. You got me right. Do you happen to know anyone or do you have any pointers to places where I can find about more about your suggestion? Especially which FPGA and which tool will be easier to work with to accomplish your suggestion. I will definately need to analyze user input and somehow formulate the required architecture in the FPGA to suit the requirements of both the user and the neural processor. The main question will be which combination of FPGA family and software tool best suited to this job? Any Comments?? > The problem to this approach will be that you have to work within the > subset of VHDL supported for synthesis by your tool. But if you can > produce C code from your inputs, you should be able to produce VHDL > code. The trick will be producing GOOD VHDL code. > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12262
In article <361A839D.7BC75B74@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > elmousa@my-dejanews.com wrote: > > > > I work in the field of neural network hardware implementation. I used the > > Lattice isp (in-system programmable) FPGAs with excellent results. > > > > I am now looking for an FPGA that supports in system programmability and is > > supported by software tools that can allow me to automate the design > > architecture of the FPGA with minimum lay i.e. not technical user > > intervention. Perhaps, the design software will allow complex scripting, > > and/or linking to a high level langauge > > > > The goal is to design a neural hardware system that is general purpose, > > mutliconfigurable and user friendly. I believe that FPGAs will allow me to do > > this when linked with a special neural processor. > > > > Any ideas, pointers, feedback will be appreciated. > > I think I understand what you are trying to do and it may be possible. > The most likely method would be to use your input program to analyze > your user requirements and produce VHDL as output. The VHDL can then be > compiled to a chip by means of any of the many VHDL compiliers > available. Thanks for your reply. You got me right. Do you happen to know anyone or do you have any pointers to places where I can find more about your suggestion? Especially related to which FPGA and which tool will be easier to work with to accomplish your suggestion. I will definately need to analyze user input and somehow formulate the required architecture in the FPGA to suit the requirements of both the user and the neural processor. The main question will be which combination of FPGA family and software tool best suited to accomplish this job? Any Comments?? > The problem to this approach will be that you have to work within the > subset of VHDL supported for synthesis by your tool. But if you can > produce C code from your inputs, you should be able to produce VHDL > code. The trick will be producing GOOD VHDL code. Will I have to do the translation from C to VHDL myslef, or are there tools that do this for me? and if yes which ones would you recommend? > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. Thanks Ali elmousa@my-dejanews.com -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12263
Jonathan Bromley wrote:
< snip >
> Other posters have pointed out that a screwed-up state machine
> (or anything) that subsequently recovers is, in a high-rel system,
> hardly any better than a screwed-up state machine that stays
> screwed-up. I beg to differ. OK, so the original problem
> may have corrupted some data or transaction somewhere, but at
> least your system is still running and you have a sporting
> chance of detecting and correcting the error at some higher
> level (maybe even software, if that isn't heretical here!)
> where it is easier to implement redundancy. And there are many
> situations (graphics systems, for example) where transient problems
> are unpleasant but far from catastrophic, whereas a locked-up
> state machine could mean effective total failure of the system.
>
<snip s/w in the motor comment, resist temptation to discuss fuzzy logic in
the transmission>
i agree with jonathan here. for many systems, and sequencers at the core of
them, if they make a mistake as a result of some rather unpleasant and
unfortunate event that is bad. but to keep repeating a mistake forever is,
well, bad.
anyways, for fun, perhaps going back to basics, my very first logic design
book, "mo" [m. morris mano], who writes in the 1979 geezer edition:
... Or worse, what if, because of a noise signla or any other unforeseen
reason, the
circuit finds itself in one of its invalid states? In that case it is
necessary to ensure that
the circuit eventually goes into one of the valid states so it can
resume normal operation.
Otherwise, if the sequential circuit circulates among invalid states,
there will be no way
to bring it back to its intended sequence fo state transitions.
Although one can assume
that this undesirable condition is not supposed to occur, a careful
designer must ensure
that this situation never occurs.
:horowitz and hill weigh in on it, 1st edition:
it is easy to fall into the trap of designing a circuit with a lockup
state. suppose you
have some gadget with a number of flip-flops, all going through their
proper states.
everything seems to work fine. then one day it just stops dead. the
only way you
can get it to work is to turn the power off and back on again. the
problem is that
there is lockup state (an excluded state of the system that you can't
escape from).
and you got into it because of some power-line transient that sent the
system into
the forbidden state. it is very important to look for such states when
you design the
circuit and rig up logic so that the circuit recovers automatically. at
a minimum,
things should be arranged so that a RESET signal (generated manually, at
start-up,
etc.) brings the system to a good state. this may not requie any
additional
components.
rk
Article: 12264elmousa@my-dejanews.com wrote: > > In article <361A839D.7BC75B74@yahoo.com>, > Rickman <spamgoeshere4@yahoo.com> wrote: > > I think I understand what you are trying to do and it may be possible. > > The most likely method would be to use your input program to analyze > > your user requirements and produce VHDL as output. The VHDL can then be > > compiled to a chip by means of any of the many VHDL compiliers > > available. > > Thanks for your reply. You got me right. Do you happen to know anyone or do > you have any pointers to places where I can find more about your suggestion? > Especially related to which FPGA and which tool will be easier to work with > to accomplish your suggestion. I will definately need to analyze user input > and somehow formulate the required architecture in the FPGA to suit the > requirements of both the user and the neural processor. The main question > will be which combination of FPGA family and software tool best suited to > accomplish this job? Any Comments?? > > > The problem to this approach will be that you have to work within the > > subset of VHDL supported for synthesis by your tool. But if you can > > produce C code from your inputs, you should be able to produce VHDL > > code. The trick will be producing GOOD VHDL code. > > Will I have to do the translation from C to VHDL myslef, or are there tools > that do this for me? and if yes which ones would you recommend? I don't think I can help you with either request. I would suggest that you not generate C and then translate to VHDL. That may be a very problem filled extra step. For starters you might want to just generate behavioral, simulatable VHDL so that you can try to simulate your code. Then fine tune the code generator to produce synthesizable VHDL. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12265
Thanks for the various replies, it seems to be coming down to a choice between Silos III and ModelSim with Fintronics on the outside [don't know enough about it yet]. It seems that my $5K budget was a bit optimistic and the sim. will probably come in about $7K. Still not bad in comparison with a couple of years ago. Now there's the question of synthesis. Originally I was going to stick with the Synopsis Express (***)I have as part of the Foundation package but I do have the possible options of buying a synthesiser from Synplicity or Exemplar [Leonardo]. Anybody have any comments on their quality ? Particularly when Xilinx FPGAs are the target devices ? (***) BTW Does anybody know if a command line i/f has been added to Foundation Express for the 1.5 release ?Article: 12266
We are currently using Viewlogic for - schematics design entry for Xilinx FPGA's - VHDL simulation for Xilinx FPGA designs - board level simulation for boards including schematics or VHDL based Xilinx FPGA designs - we also use Core Generator and Logiblox and see it integrates rather well with Viewlogic For some reasons, we might be forced to switch to Veribest. Does anyone know if Veribest is able to do all these things ? Does anyone has proofs that Veribest will not able to do these things ? Any experiences on integration of Xilinx tools and Veribest ? Recommendation ? Any opinions on this switch ? Thanks for all help you can provide, Bruno FierensArticle: 12267
M Kartheepan wrote: > Well it is my bad that I did not explain what I was trying to say. My > comparison was against FPGAs with 100K gates, with a typical 50% > utilization (although I have never seen that much utilization just by > relying on synthesis, P/R tools). And therein lies the problem. Synthesis without using preplaced cores is a lousy way to do DSP or data path designs. Most of these designs will not perform well if not placed well, and the automatic placers do a mediocre job at best. If you must use synthesis, at least instantiate the pre-placed parameterized macros so you have a fighting chance of getting a reasonable layout. Even then, it helps to get into the floorplanning; there is still no better placement tool than the human brain. I frequently see utilizations of 80% and more, even in the larger Xilinx devices. > At Audio Rates ( atmost 48KHz) or Telephony rates (8KHz), say a full > blown 7 band Equalizer or a Demodulator algorithm, would take only a > handful of MIPS on any commercial DSP, say running at 40MHz. However, > in hardware it can easily chew up significant part of the FPGA. I > really find it difficult to realize more MIPS on FPGA than a DSP, > atleast at audio/telephony sampling rates. But hey, I am willing to > think otherwise and would like to learn your side of the story. > At audio and telephony rates, you can take advantage of bit serial algorithms for you processing. This greatly compresses the amount of logic required to perform a particular function. There is no need to construct a fully parallel filter (for example) that is capable of 50MHz sample rates if you are passing 50KHz data. By using bit serial forms, you don't waste gates on excess processing power you don't need. If you are unfamiliar with bit serial arithmetic, there are two papers on my website that deal with it: The first is an FIR filter implemented in '91 in an ATmel 6K part. This filter does not use distributed arithmetic (the atmel part does not implement tables easily), but does show how bit serial arithmetic is used to pack a large number of multipliers in a single part. The second paper is one that discusses bit serial design techniques for FPGAs. It uses a bit serial CORDIC vector magnitude computer as an example. > Nevertheless, I can visualise FPGAs doing more work at higher sampling > (data) rates. This is because there is no major difference in gate > count(except for timing, p/r issues) between a sampling rate of 8KHz > or 48 KHz for a prescribed design. The DSP's MIPS might not amount to > anything at MHz rates but at lower sampling rates, a lot of processing > can be crammed within the available MIPS. Recently we tried to put > some signal processing stuff into FPGAs and soon ran out of gates. Gate count is a function of the design. As I mentioned above, if the data rate is sufficiently low, there is no need to use a fully parallel design. The gate savings for a bit serial design are quite significant. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12268
In a previous article rk <stellare@NOSPAMerols.com> writes: : ; :more recently i've been looking at what vhdl synthesizers do to state ;machines and am feeding in simple examples of sequencers. for one hot state :machines, one compiler makes a structure that can either lose it's one-hot ;state or have two hot states chasing each other around. The ability of one-hot state machines to contain two or more hot states concurrently is a powerful feature to be exploited by the experienced. Soft-error problem can more easily be solved by (1) more robust flip-flops, and (2) redundancy at a higher architectural level.Article: 12269
Hi all, I desperately need some help. I am doing my final year engineering project where I am designing a 16 bit Microprocessor. I am using the student version of Altera for this project, which gives me the EPF10K20RC240-4 device. I have completed my design and I have been testing it as I go, so I know all the components are working properly. Here is my problem, and it is a big problem as the deadline is coming up very close and I am starting to panic. I was going along fine until I hit this problem. Okay, so when I was at my last step (I'm so close) when I was trying to compile the whole thing I got the following error about half-way through compilation: "Internal Error: (CMP) Fatal application error in Partitioner at 10%" Does anyone know what this means and what has caused it? I have done a LOT of fiddling around testing things and trying to figure out the problem. I was thinking maybe I have run out of room on the device. I broke the top level design up into 2 parts and compiled each one seperately with no problems. When I looked at the report file, it says I have used the following space: Mem bits Mem % LCs LCs % 4608 37% 597 51% First Half 4096 33% 110 9% Second Half 8704 70% 707 60% Total Looking at this, I have 30% of my memory bits free and 40% of my LCs free so I shouldn't be out of room. I am now thinking that maybe I have enough memory bits and LCs but not enough connections between them free. Would this seem reasonable to you? I was of the impression that you could use the memory bits without affecting the use of the LCs and vice vera. That is by using some memory bits you don't take room off the LCs. Is this right. As you can see I am in a horrible mess here and am in desperate need of a solution. Does anyone know what I am doing wrong, and any ways of perhaps fixing my problem? I would be eternally greatful. Perhaps there may be some way of changing the Global Logic Synthesis settings that might use less space and allow me to fit it all on, or am I completely on the wrong track here? If you have any suggestions at all, then can you PLEASE PLEASE send them to me, even if you're not sure it'll work I'm willing to try everything. I've tried all I can think of. Thanks so much, Bruce. PS: I also checked the number of inputs and outputs, and they are all okay too. PPS: Another thought, I wonder if there is a limit of the number of memory elements I can use. It will let me use 3 RAM elements, but as soon as I use a 4th (even if it is only 4 bits), it comes up with that error again. I have a very strong suspicion this could be what's causing the problem. Can anyone confirm this? -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12270
TENURE-TRACK FACULTY POSITION
The Electrical and Computer Engineering Department of
Worcester Polytechnic Institute (WPI) invites applications
for a tenure track faculty position in the areas of
(1) Computer Engineering (especially computer architecture,
HDL, logic synthesis, VLSI systems design), or
(2) Computer and Communications Networks.
Candidates must possess an earned doctorate, and will be
expected to have a strong commitment to high quality
undergraduate and graduate engineering education, as well
as to development of a research program. Experience in
industry is desirable. WPI is a technical university
offering project-oriented programs in Engineering, Science
and Management. WPI is located an hour west of Boston, in
the high-tech region of east-central Massachusetts. WPI has
an enrollment of 2,600 undergraduate and 1000 full- and
part-time graduate students. The ECE department has 21
full-time faculty, and strong BS, MS, Ph.D and research
programs. More information about the department can be
found at http://ee.wpi.edu
To enrich education through diversity, WPI is an
affirmative action, equal opportunity employer.
Please send a statement of research and teaching interests,
a resume, and list of three references with addresses and
telephone numbers to:
Dr. John A. Orr
Head, ECE Department
Worcester Polytechnic Institute
100 Institute Road
Worcester, MA 01609-2280
email: orr@ece.wpi.edu
Article: 12271Hello, I need for my new project (PWM Generator) a 100MHz 16-Bit Counter with 3 Comparators. Because, I have no experience with such a high frequency, I would like to know if this PWM-Generator works inside a XILINX XC4010XL FPGA or a 95108 CPLD? I can't find an answer for this question in my current databook. Thanks Detlef Justen ------------------------------------------------------------------ Dipl.-Ing. D.Justen ______| _____| ___| ___| Center for Sensor Systems (ZESS) __| __| __| __| Paul-Bonatz-Str. 9-11 __| ____| __| __| 57074 Siegen __| __| __| __| Germany ______| _____| ____| ____| Tel.: ++49271/ 740-2432 Fax.: ++49271/ 740-2336 E-Mail: justen@zess.uni-siegen.de Homepage: http://www.zess.uni-siegen.de ----------------------------------------------------------------Article: 12272
I have both synplify and exemplar spectrum (new tool replaces both galileo and leonardo). Spectrum is better than galileo although in the current version one of my largest modules increased %30 in size with spectrum. I like synplify better so far. I think version 5.06 is very nice. Extremely fast. Rick Filipkiewicz <rick@algor.co.uk> wrote: >Now there's the question of synthesis. Originally I was going to stick with >the Synopsis Express (***)I have as part of the Foundation package but I >do have the possible options of buying a synthesiser from Synplicity or >Exemplar [Leonardo]. Anybody have any comments on their quality ? >Particularly when Xilinx FPGAs are the target devices ? muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 12273
Let's make rumor fact! FPGA Express 3.0 will have VHDL 93 support. Available on the Synopsys web site at the end of Oct. Derek Palmer FPGA Express Team Synopsys Corporation. Andy Peters wrote: > Hans Lindkvist wrote in message <3614BD09.E32A0E14@ldecs.ericsson.se>... > Rickman wrote: > Jake Janovetz wrote: > One possibly big difference, depending on whether you have existing > code, is that Synopsys does not support VHDL-93. They seem to be > pretty > stuck in VHDL-87. > Otherwise, I can only stay that Synopsys is what comes with Xilinx > Foundation, so a lot of Xilinx users have it! ;) > > I've heard from a Synopsys representative that vhdl-93 support is close. > I just got the Xilinx Foundation 1.5 tools w/Synopsys FPGA Express, and > there's support for *some* VHDL'93 things, like rising_edge() and > falling_edge() and myprocess : process (yadda) IS. > > A start. > > -andyArticle: 12274
michael_23@my-dejanews.com wrote: > > Hi all, > I desperately need some help. I am doing my final year engineering > project where I am designing a 16 bit Microprocessor. I am using the student > version of Altera for this project, which gives me the EPF10K20RC240-4 device. > I have completed my design and I have been testing it as I go, so I know all > the components are working properly. Here is my problem, and it is a big > problem as the deadline is coming up very close and I am starting to panic. > I was going along fine until I hit this problem. Okay, so when I was at my > last step (I'm so close) when I was trying to compile the whole thing I got > the following error about half-way through compilation: > "Internal Error: (CMP) Fatal application error in Partitioner at 10%" > > Does anyone know what this means and what has caused it? ...snip... > PPS: Another thought, I wonder if there is a limit of the number of memory > elements I can use. It will let me use 3 RAM elements, but as soon as I use > a 4th (even if it is only 4 bits), it comes up with that error again. I have > a very strong suspicion this could be what's causing the problem. Can anyone > confirm this? > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own My suspicion is that you have found an internal error in the tools. Any time you get a "Fatal Error" that is a good sign that you have not done anything wrong. You have likely just done something that the tools don't like. You sound like you have a good indicator in the number of RAM blocks. There should be no limitation on that. I suggest that you try making changes to your design just to find what will and won't crash the tool. Or you can call Xilinx support at 800-624-4782. They may want you to send them your design files to solve this. -- Rick Collins redsp@XYusa.net remove the XY to email me.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z