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Dear all,
Is it possible routing a 32x32bits fast multiplier (partial product,
Booth recording, carry save adder and Wallace tree) on FPGA and ASIC (2
metal layer)? Thanks!
Article: 12676Ovidiu: What do yu design in Romania? We are lookin' for telcom designers. Are you in Iata? Gary Gary N. Lang Vice President of ACD,Inc. E-mail: garynlang@aol.com http://www.acdcon.com/Article: 12677
In article <3620133B.363F@actrix.gen.nz>, Jeff Graham <drjeff@actrix.gen.nz> wrote: > I haven't had the Foundation updates yet, but the Alliance updates came > through this week, and I wasn't totally unsuprised to find that M1.5 is > just as appallingly bad at placing/routing 5200 series parts as M1.4 > was. > - 5204 design with 65% utilisation when built with XACT6, 96% > utilisation in M1.5 and "unable to place design due to constraints > conflict" > > Ah well, look like I'm stuck with XACT6 for another year ... > > Jeff Graham > Hardware Team Leader > MAS Division > Digital Microwave Corp > Lower Hutt, New Zealand > I, too am still using XACT6 for my 5200 designs, mostly because of the floorplanner. This single tool probably at least doubles my design efficiency and device operating speed, over auto place-and-route. I tried implementing a design that I hand-placed and easily got routed (using XACT6) with M1.5, result about 450 nets unroutable. Not to mention meeting timespecs. I/O constrained to what I knew worked, or total freedom to change. Xilinx tells me that they probably will never put much emphesis in improving the newer tool set with regard to 5200 support. Ok, I guess, but sometimes its a little frustrating to have to use two year old software, with no hope of getting any of the bugs and annoyances ever fixed. Puzzling too, since the 5200 series is still the most economical family of logic (I just got a fresh quote from the rep) for a given I/O count device, despite all the hype about the Spartan series. Many times this is also true for a given CLB count device. Of course, this situation may change by next year... they say it will... Anyone else out there consider floorplanner as indespensible as I do? Contact Xilinx and let them know. And tell them to get off their "push-button" automatic non-guided design flow paradyme. Give us the tools we need to create and guide an efficient highest performance design. I still say a brain is the most highly advanced A.I. computer ever (amazingly portable and low power, too.). Let us use it, Xilinx! (OK, I'm off my soapbox now) Incidently, I realize there is now floorplanner support in M1.5 for 4000 and Spartan series. (At least its there.) But the way they implemented it, its pretty obvious they don't expect many people to use it. Non-intuitive and awkward! In XACT6 it was easy and natural. Paul Greaves Hardware Team Leader Play, Inc. -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 12678
Ray Andraka wrote: > > Le mer Michel wrote: > > > Ken Coffman wrote: > > > > > The conversion from binary to Gray code is not too bad. The best solution > > > might be to implement a fast binary counter, then convert the binary to > > > Gray. > > > > LFSR is a Linear Feedback Shift Register counter, which is also known as a > pseudorandom number generator. It consists of a shift register whose serial > input is fed with the one bit sum of selected taps off the shift register. > Careful selection of the taps will yield a (2^n)-1 long sequence. Does anybody know a way to make an _UP/DOWN_ lfsr counter? Now I'm using a binary counter + lookup table in a ram to simulate this for a ranging application, but the ram takes much more power than the 4013E & too many pins. Gerhard -- on the air: DK4XP in the air: D-8551, D-ESKAArticle: 12679
I'am seeking an FPGA design that realises an interface to a VME bus, i.e realises address decoding for an A32/D32 slave with IRQ capabilities. This kind of design exist in the logicore library for the PCI bus but not for VME. Any idea ? -- Kind regards --- David Guyard _______________________________________________________________ David Guyard Philips Consumer Communications Tel.: +33/(0)2 43 41 19 11 Route d'Angers Fax.: +33/(0)2 43 41 11 26 F-72081 Le Mans GSM : +33/(0)6 08 45 80 31 France E-Mail: david.guyard@pcc.philips.com _______________________________________________________________Article: 12680
Austin Franklin wrote in message <01bdfd45$be60fd40$25f65ecf@drt1>... >> >> >> > Try doing a functional simulation....I believe the underlying >> >> >simulation >> >> >> > libraries are not there.... >> >> >> >> >> >> >>I believe that is because the Virtex timing files were not in >place >> >> >when they >> >> >> shipped F1.5 however, the timing models are coming. >> >> > >> >> >That was the point. The FAEs said that Xilinx has NO plans on >providing >> >> >these, or supporting ANY schematic tools for Virtex. >> >> >> >> I do not understand how anyone would make a big deal about this. >> >> Mentor Graphics uses vhdl models to simulate their schematic >> >> capture tool and it works great. >> > >> >Then you don't understand what the problem is. If you did, then you'd >> >> I remember you. You are the guy who claims viewsim supports concurrency >> because you can generate a clock signal right? > >Something tells me you 1) don't understand what you really mean by >concurency, and 2) how one can easily do what it is you were claiming one >can't do in Viewsim. > >> You are also the guy who does not know what a vhdl testbench is, probably >the >> only person n this newsgroup. > >Funny, I guess for all the designs I've done, and used 'test benches' for, >I just blindly poked at the keys (and nudged my mouse), and by magic, my >designs work (er, once simulated, debugged and timed), are shipping in >thousands upon thousands, without any problems....and I did ALL that by >dumb luck! > >Gee, Rita, how many designs do YOU have shipping in REAL products? Hum? > >Austin > Austin, A couple of weeks ago Rita posted something to the effect of 20 or so modifications of a design to get it right. I think that speaks for itself. Hope she never designs an ASIC! All I can say is her name is definitely on one of my lists and its not the list where your name is Austin.Article: 12681
Hi Look at the following homepage. You might find something of interest. http://www.acte.no/freecore/modules.htm All the designs available are written in AHDL which means that they are for Altera devices only. If your target is other products you will at least get some ideas. Regards Uffe Toft FAE for Altera distributor Hagen Ploog skrev i meddelelsen <362F8971.9C43E6BE@e-technik.uni-rostock.de>... > > >madaan@my-dejanews.com wrote: > >> Hi, >> I am working on a I2C synthesizable core, simulation models and bus monitor in >> verilog. Anyone aware of any shareware/freeware source (preferably in verilog) >> or other related stuff at any site then please let me know. >> >> -- >> Ashok Madaan >> > >I2C is very easy (about 20 CLBs) to implement as long as you don't care about >possible erros (spike, glitches..., timeouts). >Things getting worser if you start detecting erros. >Some things to remind: > - oversampling > - synchronizing > - edge-detection > - low-pass-filtering (if you dont't want glitches) > - 3-state output vs. 3 outputs > - interrupt generation > - .... > >Implementing these options makes the design more complex, so if >one is given away his i2c-model for free, look what you realy got!! >We have (of course) build a i2c-model which detect nearby the most of the >thinkable erros. You can enable most of the feature, depending on if you want a >small (but insecure) or a bigger design. > >Hagen >Article: 12682
In article <01bdfdfe$b7094340$4f62e2c1@timteh.dnttm.ro>, "ovilup" <ovilup@hotmail.com> wrote: > Hi everyone ! > > I am looking for some EDA tools that are running under Win 95/ Win NT PC's. > > The tools should have : > - VHDL compiler & simulator > - FPGA synthesis > - some way to check that what goes out from synthesis is what you > need We are using Synario for this. I like the schematic generator of the synthesized code, but cation is applied, because you usually end with a mess of and, or and FF that are displayed, and it is really difficult to understand the output. What I like from Synario in general is the integration of the tool, the possibility to mix freely VHDL(or Verilog/one of them) and schematics as well as Abel (someone still uses it). If you are not happy with the synthesis and would like to spend big bucks you can buy the Synopsys option too. > Thank you, everybody. Bye Matija > Ovidiu Lupas > TimTeh Electronics Ltd. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12683
This is a multi-part message in MIME format. --------------70F431E7E58BA9052BADC56B Content-Type: multipart/alternative; boundary="------------A3EED11DA8FE928E236F0D85" --------------A3EED11DA8FE928E236F0D85 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dear all, I'm beginer of Xilinx FPGA using. When I implement FIFO memory in Xilinx FPGA(XL4000 series), I wonder that how many CLB used as FIFO memory. Assume that my FIFO memory size is 128 x 16(depth x data width). Please, tell me calulation method about this. Thanks! --------------A3EED11DA8FE928E236F0D85 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Dear all,</FONT></FONT> <BR><FONT FACE="Arial,Helvetica"><FONT SIZE=-1> I'm beginer of Xilinx FPGA using.</FONT></FONT> <BR><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>When I implement FIFO memory in Xilinx FPGA(XL4000 series),</FONT></FONT> <BR><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>I wonder that how many CLB used as FIFO memory.</FONT></FONT> <BR><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Assume that my FIFO memory size is 128 x 16(depth x data width).</FONT></FONT> <BR><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Please, tell me calulation method about this.</FONT></FONT> <BR><FONT FACE="Arial,Helvetica"><FONT SIZE=-1>Thanks!</FONT></FONT></HTML> --------------A3EED11DA8FE928E236F0D85-- --------------70F431E7E58BA9052BADC56B Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Sang-Kwon Lee Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: Sang-Kwon Lee n: ;Sang-Kwon Lee email;internet: lacoste@lgsemicon.co.kr x-mozilla-cpt: ;0 x-mozilla-html: FALSE version: 2.1 end: vcard --------------70F431E7E58BA9052BADC56B--Article: 12684
Hi, ovilup wrote: > Hi everyone ! > > I am looking for some EDA tools that are running under Win 95/ Win NT PC's. > > The tools should have : > - VHDL compiler & simulator > - FPGA synthesis > - some way to check that what goes out from synthesis is what you > need > > Anyone knows some tools like that please let me know. I heard about > PeakVHDL, > but I need some other, for comparison. Price/quality is the issue here. For a list of VHDL compilers (some of them with synthesis tools available) take a look at Part 3 of the VHDL FAQ (http://www.vhdl.org/comp.lang.vhdl/). For FPGA development systems see http://www.optimagic.com/ . Especially take a look at the free/low-cost/demo software list. Bye,... EdwinArticle: 12685
It is possible to drive the Foundation Express tools from the command line/script file in the 1.5 release ? This couldn't be done in M1.4 . If not then I'll seriously consider buying in another synthesis tool that can be integrated into the rest of our FPGA/board compilation - simulation - version control setup. How do the Exemplar/Synplicity synth. tools compare with F-Exp when the targets are XC4K/Spartan/Virtex ?Article: 12686
Daniel K. Elftmann wrote:
> Austin Franklin wrote in message <01bdfd45$be60fd40$25f65ecf@drt1>...
< snip >
> >Gee, Rita, how many designs do YOU have shipping in REAL products? Hum?
> >
> >Austin
> >
> Austin,
>
> A couple of weeks ago Rita posted something to the effect of 20 or so
> modifications of a design to get it right. I think that speaks for itself.
>
> Hope she never designs an ASIC! All I can say is her name is definitely on
> one of my lists and its not the list where your name is Austin.
more than 20. here's the actual quote in part of a letter i sent to her which i
never got a response back.
rita says:
> Antifuse are a nightmare when it comes to prototyping. A designer
> will probably burn 20 or 30 parts before getting to the final design.
> FAEs will probably be nice and supply the designer with 2 or 3 parts
> for the average oportunity design but I bet they will never give 30
> or 40 spares to any ACTEL designer.
rk responded:
in my applications i do use the actel parts and have been using them
continually for quite a while and so have some experience
with them. could you please cite a source for the estimate of probably
burning 20 or 30 parts before getting to the final
design? this is quite inconsistent with my experience. even in systems
where the requirements had to change, i would say that
your estimate is an order of magnitude high. most systems i design burn
an intial engineering model device (an inexpensive, low-rel, commercial
device) and the system is checked out. after verification is complete,
a
single hi-rel device is programmed and installed.
[end part of letter quote]
rk now finishes up:
i think the key word is "ACTEL designer." if the parts are designed by an
engineer, it doesn't take 20 or 30 revisions to get it right. if it does take
that many revisions, then it's not engineering by definition [perhaps we need to
re-start the evolvable-genetic computer thread here]. independent of what
technology you are using [sram-based, antifuse-based, eeprom-based, or just a
pile of gates].
also, i don't ask nor expect to get prototype devices from a FAE. they are
fairly inexpensive and part of the cost of doing business. while sometimes i'm
not thrilled about the cost of some products [see my recent post asking a
tool-fan to add up the cost of his synopsys packages] as a small business owner,
most ACTEL FPGAs can be obtained for a few 10's of $'s. easy enough to just buy
a tray of whatever parts you need for prototypes and pre-production versions of
systems. on the other side of the equation, i couldn't afford the time
necessary to debug a system 20 or 30 times - it's a lot more efficient to just
turn it on and watch it work.
rk
Article: 12687
Gerhard Hoffmann wrote:
> > > > The conversion from binary to Gray code is not too bad. The best solution
> > > > might be to implement a fast binary counter, then convert the binary to
> > > > Gray.
> > > >
Problem with converting like this is you wind up with glitches because more than
one register is changing at a time. Kind of misses the point of using gray code in
the first place.
> Does anybody know a way to make an _UP/DOWN_ lfsr counter?
>
> Now I'm using a binary counter + lookup table in a ram to simulate this
> for a ranging application, but the ram takes much more power than the
> 4013E & too many pins.
yes. It really is rather straight forward. The direction of shift is reversed,
so you need a mux in front of each flip flop. The input for the reversed LFSR is
essentially the previous bit instead of the next bit, so the taps are just shifted
with respect to where they were for the forward lfsr. For example, a 16 bit LFSR in
the forward direction looks like:
+ -> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
| | | | |
+---------------+--------------------------+-----+-+
to reverse it, you reconnect like:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<-+
| | |
| |
+------------+--------------------------+-----+-+
So, what you are doing is grabbing the bits that would have produced the previous
input to reconstruct the previous input.
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 12688Yes it is. However, you can reduce the size and routing complexity by using smaller multipliers (eg 16x16) and cmbining the results using partial products. Francis wrote: > Dear all, > Is it possible routing a 32x32bits fast multiplier (partial product, > Booth recording, carry save adder and Wallace tree) on FPGA and ASIC (2 > metal layer)? Thanks! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12689
>I am looking for some EDA tools that are running under Win 95/ Win NT PC's. > >The tools should have : > - VHDL compiler & simulator > - FPGA synthesis > - some way to check that what goes out from synthesis is what you >need > Here is a set of tools which we recommend you evaluate as the complete solution for FPGA synthesis: VHDL Editor: =========== http://www.silicon-systems.com ED4W-HDL or ED4W-HDL EXPERT Simulator: ======== http://www.model.com ModelSim Synthesis: ======== http://www.synplicity.com Synplify and HDL Analyst (for schmatic viewing) All the tools above have evaluation periods of about 1 month. Regards. JohnArticle: 12690
I have this problem when trying to compile vhdl source with Orcad Express 7.01: - NO POSSIBLE REGISTER IMPLEMENTATION with clock 'clk' What's mean? I need to write code in vhdl for a memory (50*24; for a specific application) which is synthetizable: i tried several ways ... I hope you can help me suggesting the code that i can use. I'm a student and this is my first vhdl program! Thank you <<<AN e-mail: andnas@tin.it>>>Article: 12691
If I care about the state encoding, I don't use enumerated types. I
use three different synthesis tools, two different simulators, and
target FPGA's and ASIC's. Just the differences in '87 and '93 are
enough to drive me nuts. I stay away from all tool specific constructs.
For portability, I prefer the following structure:
...
signal grants: std_logic_vector(3 downto 0);
constant NO_GRANTS: std_logic_vector(3 downto 0) := "0001";
constant VIDEO_GRANT: std_logic_vector(3 downto 0) := "0010";
constant AUDIO_GRANT: std_logic_vector(3 downto 0) := "0100";
constant CPU_GRANT: std_logic_vector(3 downto 0) := "1000";
...
variable next_grant: std_logic_vector(3 downto 0);
...
case grants is
when VIDEO_GRANT =>
...
if(expression) then
next_grant := VIDEO_GRANT;
else
next_grant := NO_GRANTS;
end if;
...
when AUDIO_GRANT =>
...
when CPU_GRANT =>
...
when others => -- NO_GRANTS case
...
end case;
Of course, if the case statement is inside a clk'event, you don't need
the variable.
Todd
Article: 12692
In article <01bdfdfe$b7094340$4f62e2c1@timteh.dnttm.ro>, "ovilup"
<ovilup@hotmail.com> wrote:
>I am looking for some EDA tools that are running under Win 95/ Win NT PC's.
>
>The tools should have :
> - VHDL compiler & simulator
> - FPGA synthesis
> - some way to check that what goes out from synthesis is what you
>need
>
>Anyone knows some tools like that please let me know. I heard about
>PeakVHDL,
>but I need some other, for comparison. Price/quality is the issue here.
Don't forget to look at "Electric". This is a full EDA package with VHDL
compilation. Source code is available a the Free Software Foundation
site. For the latest version, download:
ftp://ftp.gnu.org/pub/gnu/electric-5.4g3.tar.gz
(although version 5.4g4 will be out soon...fixes BSD compilation, among
other things).
Although this free version of Electric has no specific FPGA code in it,
the system was used by the DynaChip corporation as the basis of their FPGA
software. Therefore, you can get technology mappers as well as FPGA
architecture and layout facilities.
To repeat an earlier message, here are some of the features of Electric:
> Platform independence. This source release compiles under UNIX, Windows
and Macintosh.
> Design both Schematic circuits and ASICs (has many IC design rule sets
including the latest quad-metal MOSIS submicron rules).
> Many built-in tools (DRC, Simulation, Routing, Silicon Compilation, VHDL
interface, Network Consistency Checking, Compaction, Compensation, PLA
Generation, and much more).
> Built-in constraint system provides powerful design assistance.
> Flexible database and tool control make this an ideal workbench for CAD
tool development.
If you want further information, see the GNU web page at:
http://www.gnu.org/software/electric/electric.html
And if you want further information from the folks who wrote Electric, see
their web page at:
http://www.electriceditor.com
-Steven Rubin
Article: 12693>I think that the future of computing is chips optimised for languages. >This is somewhat true now. With FPGAs to experiment with it will >become very true in the future(2-3 years). >Lisp chips, FORTH chips, Java chips, C chips, etc. With RAM based >FPGAs its a new chip every second (more or less). [Snip..Snip..Snip] The future personal computer as seen through a (10GHz) xtal ball: VERY Large programmable logic blocks tied together via *standard* bus/interface set( of >>1 paths I hope...) ASICs/flash CPLDs for the bus interface & routing controllers. Add-in more logic blocks (like todays RAM SIMMs) Local RAM resources for the logic blocks and shared (global) RAM (?) PCI bridge for video cards, HDD, FDD, USB (kbd,mouse) etc. Caretaker processor to boot the thing (use some cranky old CPU like a Merced) VHDL displaces C(++) , inherently concurrent processing ;) ISR (JTAG) mini-bus/interface. (forget self modifying code, self modifying hardware!) All we need now is an OS for all those state machines chugging away.. TTFN GJP PS: Hope Micro$oft is NOT listening. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12694
This *is* an interesting thread ... and I wonder if anyone else shares the following experience. I like HDLs because I find it is usually faster to produce a final result (for all but trivial design leafs) and allows me to construct and express control conditions without then having to go through the step of translating into a gate structure. This speed advantage is usually due to the shorter redesign time when design misbehaviors (my euphemism for bugs) are encountered. I like schematics because (most of the time, IMO) they provide a clearer view of design structure and hierarchy. All the HDL code I've seen (including the code I've written, which is not much) tends to obscure the hierarchical relationships; that is, it's difficult for me to follow which blocks connect where with what signals. This is especially true for designs with lots of blocks, lots of hierarchy, and/or blocks with high port counts. The listings get so long, I sometimes have to "page down" two times before I get to the end of the port listing for a single block instantiation. In other words, I can't see enough at once to follow or figure out the design structure. The information density is much higher in a schematic diagram than a code listing. One design team I know of got so frustrated with its inability to comprehend the hierarchical structure of a device's HDL that they recast the design into a top-level schematic of "black boxes" and put the HDL implementation code under those, a technique that can obviously be extended as deeply into a hierarchy as one desired. My desire is for some way to make HDL code as comprehensible as schematics. One possible help is an editor that allows an outline mode, like what is available in word processors (the Transputer code development tools work this way), to allow collapsing of structure so that modules are listed at the same level of indentation, but that still does not show what is connected to what. Better is something like the hierarchical architectural view provided by Synplicity (I don't know if other tools have this) but the "information density" there is still a little too low, and Synplicity's net-naming convention is, well, obscure. Having said that, it also seems to me that what we as hardware designers are doing is thinking like schematic designers when we write our HDL. I'm starting to think this is not the best way to go about writing HDL. Rather than focus on tools, maybe we could gain improved clarity by changing the way we think about the structure or partitioning of designs. Can we devise a design analysis/partition/capture technique or method that highlights or exposes rather than obscures the relationships of HDL hierarchy? Is the hybrid schematic-for-higher-levels with HDL underneath good enough? Does the nature of the underlying hardware implementation preclude or hinder this? (Since structure is imposed by the designer primarily, though not always entirely, for the conceptual benefit it provides, I suspect it does not.) Does anyone else have this difficulty? Does anyone know of anything like this offered or planned by anyone? Am I out in the woods here? Looking for insight, Glenn PS: I, too, have a cents-less keyboard, and have found them to be that way for years. Sorry, like Mel Brooks, I am unable to pass up the obvious joke, even when I'm sure others have seen it before me. :-} I find schematics useful for certain low-level functions and necessary for some timing-critical functions which I don't yet trust a synthesis tool to do properly. Since synthesis tools provide for netlist instantiation of user-defined inviolable elements (sort of user-defined primitives or library macros), I am able to indulge this preference when I prefer, making the underlying implementation of the black box a schematic-based netlist or a vendor-targeted structural HDL-based netlist. Both are equally unportable, which is something I don't recall seen being brought up, though it may have been earlier in the thread. And may not be as important to FPGA targeted designs. OTOH, FPGAs sometimes migrate to gate arrays or ASICs, sooo... ram wrote in message ... >Interesting thread you guys have going here. > >My $0.02 worth (Wow! I finally realized there is no "cents" character on my >keyboard - that only took 15 years of keyboard pecking... :) > >1. The better FPGA HDL tools are just recently getting to the point where >you can wring out a decent, medium performance design entirely in HDL. >Witness a statement in EE Times by Stephen Wasson at Highgate Design (guys >who did Xilinx PCI core - we used them before for other stuff) who said he >might actually start using the VHDL tools once Synplicity got their next >release of tools out (it allows you to guide the architectural mapping in >some ways I don't recall). > >2. It's interesting to see (at times) that the software guys think pictures >will be their saviors (e.g. Labview, Rational Rose, Software through >Pictures, some DSP tools, etc.) and the hardware guys think that languages >will be their saviors (various HDLs). >To me, I think that a picture is worth a thousand words, AND vice versa, >depending on the context it's used in. > >Having spent a fair bit of time in system design (radar systems and such), I >prefer the top level in pictures with some words around it. As I go down >through the heirarchy, pictures or text are used as appropriate. For >instance, a state machine is easier for me to comprehend as a diagram. But >there are times when an HDL (or pseudocode) conveys the meaning better (in >an algorithm description, for example). Or maybe a schematic gives a higher >performance result. > >The bottom line is that, if you view the choice of HDL vs. schematics vs. >state diagrams vs ... as a religious choice one must make, then sooner or >later there will be a downside. Hopefully we can convince the tool vendors >that we'd like to slide back and forth between all these modes of >description as seemlessly as possible, and WE decide what's appropriate. > >Regards, Rick > >ps. as to somebody's comment in a later thread about just making the >algorithm more efficient (instead of it's implementation). If you do "hard" >stuff, you typically have to do both. I'm very good at efficient algorithms >(you try and figure out how to resample 3 billion 1 bit data elements per >second on a 300 Mhz. Alpha...), yet I still seem to end up looking at CLBs >and checking prop delays and doing the low level mapping so I can get this 1 >critical piece of the design to work. > > >Article: 12695
In article <01bdfdfe$b7094340$4f62e2c1@timteh.dnttm.ro>, "ovilup" <ovilup@hotmail.com> wrote: > Hi everyone ! > > I am looking for some EDA tools that are running under Win 95/ Win NT PC's. > > The tools should have : > - VHDL compiler & simulator > - FPGA synthesis > - some way to check that what goes out from synthesis is what you > need > > Anyone knows some tools like that please let me know. I heard about > PeakVHDL, > but I need some other, for comparison. Price/quality is the issue here. > > Thank you, everybody. > > We have been using Synplicity for Xilinx designs for about a year now and are very happy with it. It has a feature called HDL analyst (costs extra) that generates a hierarchical schematic of the synthesized code. This is called the "RTL view" and it has the same hierarchy as your code and it shows components like registers, adders, muxes, and gates. A counter, for example, will be shown as an adder feeding a register with the register output feeding one input to the adder and the other adder input is a "1" (previous value + 1). This is great to verify that the synthesis interpreted your code the way you intended. You can also generate a schematic called "Technology view" that shows the same design mapped to Xilinx primitives like CLB flip flops, LUTs, TBUFs, carry logic, global buffers, etc. You can push into an FMAP and see a gate level representation of that LUT. This is nice for checking how your code is mapped to Xilinx resources. There is no guessing as to what the synthesis tool did. I recently completed a 100MHz histogrammer in Verilog using Synplicity and I know I couldn't have done any better using schematics (which I've used for the previous seven years). Hope this helps. -- Rob Weinstein Memec Design Services - Phoenix rob_weinstein@memecdesignDOTcom -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 12696
Sang-Kwon Lee wrote: > Dear all, > I'm beginer of Xilinx FPGA using. > When I implement FIFO memory in Xilinx FPGA(XL4000 series), > I wonder that how many CLB used as FIFO memory. > Assume that my FIFO memory size is 128 x 16(depth x data width). > Please, tell me calulation method about this. > Thanks! The dual-port sram in the 4000-XL series requires both LUT's in the CLB. There are 16 dual-port bits per CLB. You will need to stack 8 CLB's per column to get 128-bit depth (128/16=8). 8 CLB's per column times 16 bits wide = 128 CLBs. For muxing out the result, I assume that tri-states will be used so the muxing is CLB "free". The read/write pointers will require 2 7-bit counters for 7 more CLBs. The control is much harder for me to estimate since I haven't done a schematic based design in almost two years. However, you can see from the above that you will have at least 135 CLBs plus a handful more in this FIFO. If you don't need simultaneous read/write operation, you can forgo the dual-port and use a single port SRAM with a mux on the address bus. That will reduce you SRAM array by half at the expense of more control logic and an address mux. What is the target operating frequency for the FIFO? Also, what design approach you will use (HDL or schematic), and what speed grade FPGA? A 128 x 16 FIFO is somewhat large for a xilinx FPGA. You will sacrifice a good deal of speed if you plane to use an HDL.Article: 12697
Sang-Kwon Lee wrote: > Dear all, > I'm beginer of Xilinx FPGA using. > When I implement FIFO memory in Xilinx FPGA(XL4000 series), > I wonder that how many CLB used as FIFO memory. > Assume that my FIFO memory size is 128 x 16(depth x data width). > Please, tell me calulation method about this. > Thanks! The dual-port sram in the 4000-XL series requires both LUT's in the CLB. There are 16 dual-port bits per CLB. You will need to stack 8 CLB's per column to get 128-bit depth (128/16=8). 8 CLB's per column times 16 bits wide = 128 CLBs. For muxing out the result, I assume that tri-states will be used so the muxing is CLB "free". The read/write pointers will require 2 7-bit counters for 7 more CLBs. The control is much harder for me to estimate since I haven't done a schematic based design in almost two years. However, you can see from the above that you will have at least 135 CLBs plus a handful more in this FIFO. If you don't need simultaneous read/write operation, you can forgo the dual-port and use a single port SRAM with a mux on the address bus. That will reduce you SRAM array by half at the expense of more control logic and an address mux. What is the target operating frequency for the FIFO? Also, what design approach you will use (HDL or schematic), and what speed grade FPGA? A 128 x 16 FIFO is somewhat large for a xilinx FPGA. You will sacrifice a good deal of speed if you plane to use an HDL.Article: 12698
FPGA Express 2.x does not have scripting. Xilinx is still using 2.x, therefore, no scripting. Synopsys claims scripting support in 3.0. According to their web site, they are looking for beta testers too. =:0 Rick Filipkiewicz wrote: > It is possible to drive the Foundation Express tools from the command > line/script file in the 1.5 release ? This couldn't be done in M1.4 . If > not then I'll seriously consider buying in another synthesis tool that > can be integrated into the rest of our FPGA/board compilation - > simulation - version control setup. > > How do the Exemplar/Synplicity synth. tools compare with F-Exp when the > targets are XC4K/Spartan/Virtex ?Article: 12699
In article <362fad3b.1270854@news.megsinet.net>, msimon@tefbbs.com wrote: > People have been doing source control of dwgs for at least a hundred > years (that I know of). No reason we can't do it with schematic files. > > Do it all the time for PC Boards. (No paper changes hands except for > the check). > > Simon > ================================================================================ === > Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >Watching this seemingly eternal schematics vs. HDL argument I find myself, > >typically, agreeing with both sides. Schematics for their intuitive nature, > >at least for datapath stuff - state machines are more problematic. HDL for > >speed of writing & modifying random logic. What wins it for me is that the > >text nature of HDLs make them amenable to source code revision control, > >difficult or impossible with schematics [Correct me if I'm wrong here]. Also > >, using lots of instantiation, you can treat HDLs as text based schematics > >but the reverse process is awkward. > > > > > > Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm > We use Visual Source Safe (Microsoft) for source control of Viewlogic schematics. Works great. -- Rob Weinstein Memec Design Services - Phoenix rob_weinstein@memecdesignDOTcom -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
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