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Told you! Get free web based email and newsgroup sending from http://www.dragoncon.netArticle: 13026
My ISP's news reader is temporarily broken, so I'm doing my best with dejanews In article <NRZz7CAfxKS2EwwE@edmoore.demon.co.uk>, Edward Moore <edmoore@edmoore.demon.co.uk> wrote: > > A few of points: > > 1. One of the improvements to Par/v1.5 is that ram blocks are recognised > as such, and are supposedly placed in a sensible manner. This should > remove the need for RLOC'ing. should, but it doesn't! > > 2. It sounds like Xilinx have suggested the -ir map option to get round > some mapping bug's in version 1.5. However, if the -ir option is used > relative placement information is lost, so RLOC'ing wouldn't get you > anywhere. I suggest getting the M1.5 service pack anyway. > And then get 1.5i, which should be out any day now. 1.5 service pack is available on the xilinx website. !.5i should be there in a day or two. > 3. If the clb's with rams are intended to also have flip-flops, it might > be worth while checking in EPIC that they are both going in the same > clb. Be careful here. If the Rams and ffs are parts of separate RPMs, 1.5 won't let you put them in the same CLB. > > 4. Contrary to popular belief, structured hierarchical relative > placement is possible with VHDL too. In fact it's easier and quicker. Show me. -- Ray Andraka, P.E. president Andraka Consulting Group, Inc. +1 401-884-7930 FAX +1 401-884-7950 email randraka@ids.net http://users.ids.net/~randraka -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13027
Has anyone got a use for a synthesizable implementation of DES in VHDL? I've done it as a learning exercise working from John Savard's description and could bung it on my web site if anyone is interested. Naturally, no warranty etc. I assume it is legal to post crypto code on a web site in the UK, AFAIK there are no export control laws here. Preliminary testing for the fully unrolled version using Orcad and Xilinx tools for gave a throughput of 320mbps in a XC40250XV-09 FPGA chip. It doesn't use any of the Xilinx chip features and could probably be synthesized on any suitably sized device. I'm going to look into using select-RAM next. It checks out OK against the validation data in the des-linux package. Has anyone got some test vectors with stronger provenance? I check FIPS46-2 and FIPS74 but there wasn't any test data. Someone has borrowed (and I think lost) my AC2 so that is out for now. Any comments, ideas? I think I'll have a go with one of the AES candidates next, probably Twofish, once I've figured out using testbenches for automated validation. Chris -- Chris Eilbeck mailto:chris@yordas.demon.co.ukArticle: 13028
i used to use able macros. I found that they are nothing more than a waste of time. Anything you do in abel can be done in the schmatic graphical design. My advice to you is to find a way to implement your idea in the schematic. Think of your function in a hierarchial fashion and make macros of small sizes. After some time you will find that you can do things much easier and faster. Xilinx has a 1800 hotline to solve problems. Also, upgrade to 1.5 because it works 1000 times better.Article: 13029
Chris Eilbeck wrote: > > Has anyone got a use for a synthesizable implementation of DES in VHDL? > I've done it as a learning exercise working from John Savard's > description and could bung it on my web site if anyone is interested. > Naturally, no warranty etc. I assume it is legal to post crypto code on > a web site in the UK, AFAIK there are no export control laws here. I for one, would be interested in seeing your code. I can't comment on any legal issues of posting it. But I believe even in the US, DES has been declared to be OK to export now. I guess they finally figured that DES is small potatoes compared to the other things running around out there. Did I read correctly that your algorithm took a 250K gate chip for implementation? That seems like a lot! I take it that your implementation is fully pipelined rather than sequential like a standard CPU. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 13030
To all on this newsgroup, I have a old Atari 8bit computer (1450XLD model) that uses two 40 pin LSI chips for a good portion of the memory management and timing. Both of these chips appear to be prototype. Both are in ceramic packages with gold cover and pins. The cover is held on by scotch tape, which when removed exposes the die inside. Neither chip has even one sort of marking of any kind at all. I have manage to trace out the connections to the rest of the computer to get a idea of some of the signals going to/from the chips. But I'm at a lost now of wether or not these are programmable logic array chips. My questions are as follows: During the 1982-1984 time frame, were there any programmable logic chips made that came in a 40 pin package? If there was, what companies would have been making them? Could these chips be PAL, GAL, or FPGA? I'd appreicate any leads someone could give me to go by to try and identify these chips. I'm looking to find out if I can duplicate these chips to preserve this rare Atari computer that I have. Thanks, -- ****************************************************** Glenn Bruner Email: brunergs@pcisys.net Visit my web page of images of rare Atari items http://www.pcisys.net/~brunergs/Atari/ ******************************************************Article: 13031
Hi:
I need Workview office library files, such like viewdraw and viewsim
Article: 13032mzurlo4054@aol.com (MZurlo4054) wrote: >i used to use able macros. I found that they are nothing more than a waste of >time. Anything you do in abel can be done in the schmatic graphical design. >My advice to you is to find a way to implement your idea in the schematic. >Think of your function in a hierarchial fashion and make macros of small sizes. Hmm, IMHO it's easier to write an address decoder in ABEL than draw a schematic, but it seems to be the only workaround until the upgrade comes. > After some time you will find that you can do things much easier and faster. >Xilinx has a 1800 hotline to solve problems. Also, upgrade to 1.5 because it >works 1000 times better. I'm already waiting for this upgrade. The nearest hotline in Germany was very helpfull, but they don't have solution for this problem. The only way to solve it is an upgrade. Thanks for your help -- Jaroslaw Cichorski Jr. E-mail cichy@amart.JUNKMAILPROTECTION.com.pl WWW http://www.amart.com.pl UWAGA Adres email niewazny! Prosze usunac JUNK MAIL PROTECTION. zeby otrzymac prawidlowy adres. Kto to jest General Failure i dlaczego czyta z mojego dysku twardego ?Article: 13033
Hi I'm looking for a survey dealing with the FPGAs' evolution - density - cost per function - reconfiguration time - speed I would be realy pleased to get help from the net. LoicArticle: 13034
Chris Eilbeck wrote in message <364A3F47.F077FE6C@yordas.demon.co.uk>...
>Has anyone got a use for a synthesizable implementation of DES in VHDL?
>I've done it as a learning exercise working from John Savard's
>description and could bung it on my web site if anyone is interested.
>Naturally, no warranty etc. I assume it is legal to post crypto code on
>a web site in the UK, AFAIK there are no export control laws here.
I think it is at the moment but the UK government is thinking about making
it illegal. I have crypto code on my web site at:
http://www.seven77.demon.co.uk/aes.htm
Brian Gladman
Article: 13035In article <364A3F47.F077FE6C@yordas.demon.co.uk>, Chris Eilbeck <chris@yordas.demon.co.uk> wrote: >Has anyone got a use for a synthesizable implementation of DES in VHDL? I would be interested in seeing this. ... >Naturally, no warranty etc. I assume it is legal to post crypto code on >a web site in the UK, AFAIK there are no export control laws here. The UK does have export controls. On paper they are much the same as the US version but in practice there are a couple of major differences. Firstly, the DTI, at least at the implementation (as opposed to policy) level are rational people so getting an export license only takes a finite amount of work (as opposed to the apparently unbounded work factor in the USA). Secondly, and more important to your comment, at the moment the UK export controls do not cover intangible exports so currently is it legal to export crypto over the net. Furthermore, if you put your design in the public domain another set of laws kick in and it is not export controlled at all as far as I understand it. You should be aware, if you do put the VHDL on your web site but do not make it truly public domain, that the DTI have some rather poorly drafted proposals outstanding which, among other effects, will remove the loophole for intangible exports. They will also violate basic human rights with respect to free speech and completely destroy the ability of British academics to cooperate in international research, but that's another story. Nicko -- -- Nicko van Someren Fax: (+44)(1223)723601 Vox: (+44)(1223)723600 Mailto:nicko@ncipher.com http://www.ncipher.com/Article: 13036
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> johnd1489@my-dejanews.com wrote: <blockquote TYPE=CITE>As I told You - Ignore! <p>-----------== Posted via Deja News, The Discussion Network ==---------- <br><a href="http://www.dejanews.com/">http://www.dejanews.com/</a> Search, Read, Discuss, or Start Your Own</blockquote> Bandwith?</html>Article: 13037
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> johnd1489@my-dejanews.com wrote: <blockquote TYPE=CITE>As I told You - Ignore! <p>-----------== Posted via Deja News, The Discussion Network ==---------- <br><a href="http://www.dejanews.com/">http://www.dejanews.com/</a> Search, Read, Discuss, or Start Your Own</blockquote> Last test</html>Article: 13038
Chris Eilbeck <chris@yordas.demon.co.uk> writes:
>Has anyone got a use for a synthesizable implementation of DES in VHDL?
>I've done it as a learning exercise working from John Savard's
>description and could bung it on my web site if anyone is interested.
>Naturally, no warranty etc. I assume it is legal to post crypto code on
>a web site in the UK, AFAIK there are no export control laws here.
The EFF's Deep Crack implementation is available both in book form ("Cracking
DES") and online, there are links from the EFF home page, http://www.eff.org.
Posting the code from the UK is perfectly OK.
>It checks out OK against the validation data in the des-linux package.
>Has anyone got some test vectors with stronger provenance? I check
>FIPS46-2 and FIPS74 but there wasn't any test data. Someone has
>borrowed (and I think lost) my AC2 so that is out for now.
You can get a copy of the NBS/NIST test vectors (along with C code to apply
them if that's useful) as part of cryptlib,
http://www.cs.auckland.ac.nz/~pgut001/cryptlib/ - look at lib_des.c.
Peter.
Article: 13039In article <910869470.13339.0.nnrp-02.c2de6a96@news.demon.co.uk>, "Brian Gladman" <gladman@demon.co.uk> wrote: > > Chris Eilbeck wrote in message <364A3F47.F077FE6C@yordas.demon.co.uk>... > >Has anyone got a use for a synthesizable implementation of DES in VHDL? > >I've done it as a learning exercise working from John Savard's > >description and could bung it on my web site if anyone is interested. > >Naturally, no warranty etc. I assume it is legal to post crypto code on > >a web site in the UK, AFAIK there are no export control laws here. > > I think it is at the moment but the UK government is thinking about making > it illegal. I have crypto code on my web site at: > > http://www.seven77.demon.co.uk/aes.htm > > Brian Gladman Dr Gladman is quite correct - the current export laws do not cover the intangible export of goods from the UK. Tangible export is currently covered by the primary legislation "Import, Export and Customs Powers (Defence) Act 1939". The government has a white paper entitled STRATEGIC EXPORT CONTROLS available at: http://www.dti.gov.uk/export.control/stratex/ This details the governments worrying proposals. Regards, Sam Simpson Comms Analyst -- See http://www.hertreg.ac.uk/ss/ for ScramDisk, a free virtual disk encryption for Windows 95/98. PGP Keys available at the same site. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13040
There should be a 2nd CD in your jewel box that contain the library files. John Huang wrote in message <72dt1i$qm0$1@news.seed.net.tw>... >Hi: > I need Workview office library files, such like viewdraw and viewsim > > >Article: 13041
************
Here are the headlines from the latest ZEN News. For the
complete copy, see our web site at http://www.zen-news.com
***********
ZEN News - Vol. 4, No. 8 November 10, 1998
* Microprocessors
+ Next Gen processors from Intel, AMD and Cyrix
Quick overview of new chips in the works - Intel's Merced,
Foster and McKinley; AMD's K7; Cyrix's Jalapeno; and the
new chip from Rise.
+ Alpha pushing multiprocessing
Alpha's new chip will speed up multiple processor servers.
* Graphics
+ Who's hot (ATI and Nvidia) and who's not (3Dfx, Cirrus)
ATI is #1 and getting bigger - it just bought Chromatic;
Nvidia's RIVA TNT is doing well, but faces numerous patent
infringement suits; 3Dfx reported an operating loss due to
lower than expected sales of its Voodoo chip; Cirrus is out
of the graphics market.
* Disk Drives
+ Syquest suspends operations
Gamble on a cheap removable disk drive didn't work out.
* Networking & Telecommunications
+ G.Lite standard gets preliminary approval
Now the waiting start for local exchange carriers to start
offering it.
* Memories
+ Intel invests in Micron
Intel puts up $500 million to ensure supply of Rambus Direct
RAM memory chips. With the Korean and Japanese companies
cutting back their expansion plans, Micron is poised to become
the largest DRAM maker.
* Electronic Design Automation
+ Mentor succeeding in Quickturn takeover
Mentor claims it has over 50% of Quickturn stock tendered, but
faces a long wait for shareholder approval.
+ Synopsys buys Everest to move into physical design
Keeps apace of Cadence and Synopsys in race to build "virtual
RTL prototyping."
+ Cadence announces layoffs
Cadence to layoff one third of its design consulting staff.
* Bottom Lines
+ Is the slump over? Maybe, just maybe!
Intel is reporting revenues higher than last year. So is
Microsoft. DRAM prices are inching upwards and consolidation
continues as Siemens pulls out of the semiconductor business.
Article: 13042In article <NRZz7CAfxKS2EwwE@edmoore.demon.co.uk> Edward Moore <edmoore@edmoore.demon.co.uk> writes: > etc, etc.. >4. Contrary to popular belief, structured hierarchical relative >placement is possible with VHDL too. In fact it's easier and quicker. >Edward Moore This is an amazing (to me at least) claim. Please give an example of how you do structured hierarchical relative placement in VHDL. Philip FreidinArticle: 13043
Rickman wrote: > > Did I read correctly that your algorithm took a 250K gate chip for > implementation? That seems like a lot! I take it that your > implementation is fully pipelined rather than sequential like a standard > CPU. It is fully pipelined taking 4700 logic blocks on a Xilinx 4000 FPGA (60000 gates). I haven't done any optimisations and it may be possible to drop the gate count with a bit of work. This is just a first cut as a learning exercise to date and doesn't have any useable interfaces, 64 bit parallel I/O. A full duplex single round implementations would probably fit on a XC4028 for about 200 quid per chip but with an associated drop in throughput. Chris -- Chris Eilbeck mailto:chris@yordas.demon.co.ukArticle: 13044
> Did I read correctly that your algorithm took a 250K gate chip for > implementation? That seems like a lot! I take it that your > implementation is fully pipelined rather than sequential like a standard > CPU. We sell a sequential version.Straight unconstrained synthesis from ASIC VHDL resulted in 239 CLBs on a xcs30 -4 and a speed of about 72 Mbits/sec. I got 124 Mbits/sec on some Altera part (again no constraints, a straight synthesis from VHDL). The same code in 0.5 u will run at 400Mbits/s and about 3.5 Kgates. This assumes both encryption and decryption functionality. Encryption only it's probably smaller and possibly faster. > Rick Collins > > redsp@XYusa.net My real email address it's in my web page (see below). Enzo ------------------------------------------------------------------------------- Vincenzo Liguori Ocean Logic Pty Ltd PO BOX 768 Manly NSW 1655 Australia Ph : +61-2-99054152 Fax : +61-2-99050921 WWW : http://www.bigfoot.com/~oceanlogicArticle: 13045
i have a problem of taget size of my VHDL project. i try to minimize a number of Altera Device's and Delay. but my synthesized VHDL Source is larger than Altera's compiled AHDL source and Top gdf. i wanna know Altera FloorPlan Editor and using method. thank you in advance.Article: 13046
Hello I think that a 16-bit x 16-bit binary multiplier will be quite challenging. After you implemented your project, would you place on the web site or give me to have a look? Leslie Yip In article <3ej22.1081$4S.3996@weber.videotron.net>, "Stephane Marcouiller" <mars02@gel.usherb.ca> wrote: > I have to find a suitable VHDL project for my course Computer Architecture > II > Suggestions are welcome > > Currently I have a couple of ideas like : branch prediction buffer, > pipelined CPU, L1 et L2 cache,... > > Do you have other ideas ? > > P.S. It must be possible to do it whitin 3 weeks * 5 hours/week = 15 hours > approx. > > Thx > > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 13047
Philip Freidin wrote: > > In article <NRZz7CAfxKS2EwwE@edmoore.demon.co.uk> Edward Moore <edmoore@edmoore.demon.co.uk> writes: > > etc, etc.. > >4. Contrary to popular belief, structured hierarchical relative > >placement is possible with VHDL too. In fact it's easier and quicker. > >Edward Moore > > This is an amazing (to me at least) claim. Please give an example of how > you do structured hierarchical relative placement in VHDL. Synplicity has such a HDL floorplanner in the works. I've played with it a little. It is a cool idea, as a large part of making a fast design is controlling the placement of the parts of the design. I have no connection to Synplicity other than using their products. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 13048
Alex Protasiewicz ¼¶¼g©ó¤å³¹ <72f4l5$b6q@bgtnsc03.worldnet.att.net>... >There should be a 2nd CD in your jewel box that contain the library files. > >John Huang wrote in message <72dt1i$qm0$1@news.seed.net.tw>... >>Hi: >> I need Workview office library files, such like viewdraw and viewsim But my version is signle CdArticle: 13049
Hi,
> Has anybody found any affordable(?) JTAG interconnect testing software?
no we looked for something that way, too and did not find anything.
> We are a small company producing equipment in low volume for medical
> research. It seems that nobody has a marketing strategy that covers us
> (low budget!). I figured there must be lots of other companies in a
> similar position wanting to use JTAG but can't afford to?
We are a university's institute and are in a similar situation.
However, we use BSCAN mor for debugging than small-series production
test.
What we did was writing our own JTAG software interface.
Is is more a quick-and-dirty solution specific to our board (one ALTERA
CPLD),
but if you are interested, I could send you the program (GFORTH).
Andreas
--
---------------------------------------------------------------
Andreas Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Ratzeburger Allee 160
D-23538 Luebeck
Germany
Tel.: +49 451 500-3741
Fax: +49 451 500-3687
Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
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