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Messages from 120625

Article: 120625
Subject: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
From: Pablo <pbantunez@gmail.com>
Date: Tue, 12 Jun 2007 07:43:18 -0700
Links: << >>  << T >>  << A >>
On 12 jun, 16:30, "sjulhes" <t...@aol.fr> wrote:
> Just start with the heap in the sdram, experiment with a little firmware for
> test.
>
> "Pablo" <pbantu...@gmail.com> a =E9crit dans le message de news:
> 1181635173.201211.44...@a26g2000pre.googlegroups.com...
> On 12 jun, 07:43, "sjulhes" <t...@aol.fr> wrote:
>
> > Yes It works fine, I've used it several times, just dispatch things in the
> > linker script.
> > But be we have a problem, when we reset the firmware, heap gets full and
> > heap initialization get false as the heap pointer reaches memory upper
> > limit. For now we can't get the to reset the heap pointer, so if you have
> > a
> > solution please let me know !
>
> > "Pablo" <pbantu...@gmail.com> a =E9crit dans le message de news:
> > 1181575038.650482.31...@q66g2000hsg.googlegroups.com...
>
> > > Hi, I have a program which needs to allocate high memory with calloc,
> > > but I want to load the app on the BRAM, so I wish to configure linker
> > > script so heap resides on the SDRAM. Is it possible?. Does anyone try
> > > to do this?
>
> If I configure Heap and Stack for SDRAM in linker script, the program
> doesn't run.

Xilinx doesn't allow to place heap and stack in separate memories. So
I have to place both in Sdram. Any test run with this configuration in
my Spartan 3E starter kit.


Article: 120626
Subject: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
From: bart <bart.borosky@latticesemi.com>
Date: Tue, 12 Jun 2007 09:24:09 -0700
Links: << >>  << T >>  << A >>
On Jun 8, 11:31 am, Antti <Antti.Luk...@googlemail.com> wrote:

> gosh,
>
> this online store is just doing database query into mouser !
>
> so there is no such thing as "latticeonline store", it just means
> thatlatticeis not selling anything (same as Xilinx) but instead
> redirects to mouser

Antti, the major operational difference between the Xilinx and Lattice
store is that there is NO MINIMUM ORDER QUANTITY on the Lattice site.
You do not have to buy a full tube, tray, or a $XXX order minimum. On
the Lattice store, you can purchase one part if you want to.
Mouser is specialized in a very high service level for small order
quantities, and can even ship orders the same day if they have stock
of the product!
As for the LatticeXP2 not being available on the online store, the
device is currently in engineering sample mode. Thus, if you want to
get parts, you have to work with our sales team or FAEs. When the
device moves to the next phase, it will be available on Lattice store.
~bart


Article: 120627
Subject: Re: Unused clock pins tied inactive?
From: Paul Leventis <paul.leventis@gmail.com>
Date: Tue, 12 Jun 2007 16:42:39 -0000
Links: << >>  << T >>  << A >>
Hi,

You do not need to connect unused general or clock inputs to ground if
you configure them as "inputs tri-stated with weak pull-up" or as
"outputs driving ground" in Quartus.  We do recommend that if your
unused inputs are set to "inputs tri-stated" that you connect them to
VCC or GND external to the device for better noise immunity.

With some of our FPGAs, there can be signal integrity advantages of
physically connecting your unused I/Os to ground (regardless of
internal setting), primarily because this provides better ground
return current paths in the PCB under the FPGA (assuming you are using
through vias).  Even if your outputs are set to "outputs driving
ground", you won't get much return current through the I/O buffer
itself -- but the act of adding the via will reduce the size of
inductive loops in the PCB via region, reducing your inductive
coupling.

Regards,

Paul Leventis
Altera Corp.


Article: 120628
Subject: Re: Pin Capacitance Quartus 6.0
From: Paul Leventis <paul.leventis@gmail.com>
Date: Tue, 12 Jun 2007 17:01:14 -0000
Links: << >>  << T >>  << A >>
Hi,

Output pin load capacitance is used to roughly model the impact to
timing and power that the load of downstream chips and your board
trace have on the buffer.  The reality is that the timing impact of a
PCB trace depends a lot on its length relative to your edge rate.  The
most simplistic and pessimistic appraoch is to add the PCB trace
capacitance and your far-end load caps and set this as your output pin
load.  If your I/O timing (such as Tco and Tpd) still meet your specs,
you are probably ok.

In the absence of any information on your board and loadings, 10 pF is
as good a guess as any, and 20 pF is likely pessimistic.

If you are using Quartus II v6.1 with Stratix II or II GX devices, or
Quartus II v7.1 with Stratix III, you can enable "Advanced I/O Timing"
under the TimeQuest settings.  This feature of Quartus allows you to
enter the parameters of the PCB -- near- and far-end loading,
termination resistors, and PCB trace properties -- and Quartus will
figure out the true impact that this has on your delay to both the
near-end (FPGA pin) and far end (load).  Quartus will also compute
various signal integrity metrics (such as ringing) to see if you have
any problems.  See http://www.altera.com/literature/hb/qts/qts_qii52013.pdf
for details on Advanced I/O Timing.

Or if you are very ambitious, you can run an IBIS or HSPICE simulation
of your I/O.  If you do, you will need to be careful how to combine
the delay estimates from your tool with Quartus delays to avoid
missing or double-counting delay -- see Application Note 424 --
http://www.altera.com/literature/an/an424.pdf.  Better yet, just get
Quartus to write out the HSPICE netlist for your I/Os using the HSPICE
Writer feature -- this will setup everything for you to avoid double-
counting issues.

Regards,

Paul Leventis
Altera Corp.


Article: 120629
Subject: Re: Apart from IEEE, is there some another journals for publishing
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Tue, 12 Jun 2007 11:08:06 -0600
Links: << >>  << T >>  << A >>
Colin Paul Gloster wrote:
> Pablo <pbantunez@gmail.com> posted:
>      "Hi, I would like to know if someone could recommend me some journal
>      for publishing my article about FPGA."
> 
> If you search for
> FPGA
> on
> HTTP://Portal.ACM.org
> you can find such journals.

If you can make it Xilinx-centric, you might be able to get it into 
Xilinx's XCELL rag.  I think it's a pretty well-read forum, but the 
articles have to be fairly short and readable; i.e., not heavy on the 
differential equations.  -Kevin

Article: 120630
Subject: xilinx spartan3e kit ddr sdram
From: emu <emu@ecubics.com>
Date: Tue, 12 Jun 2007 10:10:01 -0700
Links: << >>  << T >>  << A >>
Hi all,
is there any open source DDR SDRAM controller IP available (VHDL) for
the DDR SDRAM on this kit ?


Article: 120631
Subject: Re: EDK Simulation Problem
From: motty <mottoblatto@yahoo.com>
Date: Tue, 12 Jun 2007 10:44:13 -0700
Links: << >>  << T >>  << A >>
You tried using the EDK to generate the compilation libraries?  With
all the correct options set?  That should at least get you the folders
needed with the files that I suppose the EDK looks for when generating
sim files (modelsim.ini, etc).  My EDK errored out on both the ISE
compilation and the EDK compilation.  I don't know what the ISE error
was...it sure wasn't in the log file.  The EDK error was related to
not being able to find the unisims_ver library.

I then went into the ISE GUI and compiled the ISE libraries from
there...into the same folder that I pointed the EDK to.  That worked
with no error.  I then went back to the EDK and ran the compedklib
from the command line (shell).  See the documentation for details on
what to put in there.  So that worked with no errors.  After all of
that, I was able to run the Generate Simulation Files with no problem.

I do not know why the library compilation has NEVER worked for me
through the EDK (from 7.1 to 9.1).  Maybe it has something to do with
install directories or moon-sun-planet alignment.  I've learned to
just accept it and be happy that I've found a workaround.


Article: 120632
Subject: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
From: Antti <Antti.Lukats@googlemail.com>
Date: Tue, 12 Jun 2007 10:52:59 -0700
Links: << >>  << T >>  << A >>
On 12 Jun., 18:24, bart <bart.boro...@latticesemi.com> wrote:
> On Jun 8, 11:31 am, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > gosh,
>
> > this online store is just doing database query into mouser !
>
> > so there is no such thing as "latticeonline store", it just means
> > thatlatticeis not selling anything (same as Xilinx) but instead
> > redirects to mouser
>
> Antti, the major operational difference between the Xilinx and Lattice
> store is that there is NO MINIMUM ORDER QUANTITY on the Lattice site.
> You do not have to buy a full tube, tray, or a $XXX order minimum. On
> the Lattice store, you can purchase one part if you want to.
> Mouser is specialized in a very high service level for small order
> quantities, and can even ship orders the same day if they have stock
> of the product!
> As for the LatticeXP2 not being available on the online store, the
> device is currently in engineering sample mode. Thus, if you want to
> get parts, you have to work with our sales team or FAEs. When the
> device moves to the next phase, it will be available on Lattice store.
> ~bart

bart

Xilinx does use digikey, so they also have NO MINIMUM order.

I see no  difference here, BOTH ARE BAD in that sense that the latest
and greatest silicon is NOT AVAILABLE.

not from Xilinx online, not from Lattice online.

Lattice could do an example here, and OFFER IMMEDIATE 1 OFF XP2
example ONLINE orders

I bet most people would instanlty order.

just 1 per customer, GIFT PACKAGED XP2 sample. One click order, no
questions, just PAY and get it.

but eh, one can always dream... I do

well, while dreaming that Xilinx/Lattice would improve their online
store to include ES silicon, guess what I am designed in? Actel PA3,
gee the QFN132 package is real nice one, glad to see XP2 includes this
package as well. To Lattice, I would have preferred XP over PA3, but
there was no tiny package available. Xilinx, same words: S3AN in
QFN132 would win many designs over MAX2,machXO,PA3,XP2... but S3AN
only has big ugly packages :(

Antti



















Article: 120633
Subject: TDM stream multiplex/demultiplex
From: "jai.dhar@gmail.com" <jai.dhar@gmail.com>
Date: Tue, 12 Jun 2007 18:04:47 -0000
Links: << >>  << T >>  << A >>
Would anyone know if there is a core out there that can multiplex 4
2.048MHz TDM streams onto 1 8.192MHz stream? (and inverse). I'm having
a hard time trying to write it on my own since I'm not that familiar
with domain-crossing techniques.

Thanks!


Article: 120634
Subject: Programming Question
From: Rohan <rohan.jyrm@gmail.com>
Date: Tue, 12 Jun 2007 11:19:26 -0700
Links: << >>  << T >>  << A >>
S/w used : Xilinx WebPack
Chip : Spartan - XC2S200PQ208C

I have configured a bus as a bi-direction by declaring it as 'inout'
However on synthesizing the verilog files, the constraints editor
shows some of the bus lines of the bus as BiDir and some as Tri Output

Is there any reason all the lines are not BiDir?
What could have forced some of the line to become TriOutput?


Article: 120635
Subject: Programming Question
From: Rohan <rohan.jyrm@gmail.com>
Date: Tue, 12 Jun 2007 11:19:28 -0700
Links: << >>  << T >>  << A >>
S/w used : Xilinx WebPack
Chip : Spartan - XC2S200PQ208C

I have configured a bus as a bi-direction by declaring it as 'inout'
However on synthesizing the verilog files, the constraints editor
shows some of the bus lines of the bus as BiDir and some as Tri Output

Is there any reason all the lines are not BiDir?
What could have forced some of the line to become TriOutput?


Article: 120636
Subject: Re: Programming Question
From: "John_H" <newsgroup@johnhandwork.com>
Date: Tue, 12 Jun 2007 11:37:15 -0700
Links: << >>  << T >>  << A >>
If you never use the input of the bidir signal, it will be configured as a 
tristate output.


"Rohan" <rohan.jyrm@gmail.com> wrote in message 
news:1181672366.609438.249860@d30g2000prg.googlegroups.com...
> S/w used : Xilinx WebPack
> Chip : Spartan - XC2S200PQ208C
>
> I have configured a bus as a bi-direction by declaring it as 'inout'
> However on synthesizing the verilog files, the constraints editor
> shows some of the bus lines of the bus as BiDir and some as Tri Output
>
> Is there any reason all the lines are not BiDir?
> What could have forced some of the line to become TriOutput?
> 



Article: 120637
Subject: Re: adaptive filter FPGA
From: "cutemonster" <ckh827@hotmail.com>
Date: Tue, 12 Jun 2007 14:54:42 -0500
Links: << >>  << T >>  << A >>
Thanks for the info, Lakkos.  There are similar projects.  However, they
transfer the logics into fpga instead of digitizing the analog x and y
inputs.  Dealing with analog signal really give me a headache. 

thanks again.


Article: 120638
Subject: Re: Power consumption problem
From: Amine.Miled@gmail.com
Date: Tue, 12 Jun 2007 13:28:01 -0700
Links: << >>  << T >>  << A >>
On 12 juin, 04:05, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> Amine.Mi...@gmail.com wrote:
> > Hi,
>
> > when i implemented my architecture using ACTEL AFS600 (Fusion family)
> > i noticed that over 16MHz there is a gap in consumption, in fact when
> > i was changing my frequency from 1 kHz to 16 Mhz the power consumption
> > is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
> > and the power consumption jump directly to 30 mW,
> > anyone has any reason to explain this gap?
>
> > my speed grade is -2,
>
> Is it operating normally over that threshold ?
> Normally, such a current discontinuity, also infers
> an operational discontinuity.
>
> Does the slope continue at just under 0.5mW/Mhz above that threshold ?
>
> I'd test again with some simpler code, that you know has a very high Fmax.
>
> -jg

that's the problem: the FPGA is still working good.
Yes the slope continue at just 0.5mW/Mhz above that threshold,
i tested the FPGA with other code and what s strange is that this
discontinuity still exist but for higher frequency (again the fpga is
still working good)

A.


Article: 120639
Subject: XIlinx tools question - how to quickly identify unconstrained paths
From: johnp <johnp3+nospam@probo.com>
Date: Tue, 12 Jun 2007 14:07:12 -0700
Links: << >>  << T >>  << A >>
I trying to integrate an IP block from a client and it has a ton of
clock crossing, most of which are probably OK.  Up to now, I've
run the Xilinx tools in an iterative mode - set constraints, run
Translate, Map, P&R, then look at the timing report to find
*some* unconstrained paths.

Is there a Xilinx tool that will look at the Xst output and the UCF
file and report the unconstrained paths without going through
the time required to run (and rerun) Translate, Map, PAR?

Thanks!

John Providenza


Article: 120640
Subject: Re: XIlinx tools question - how to quickly identify unconstrained
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 12 Jun 2007 14:35:16 -0700
Links: << >>  << T >>  << A >>
johnp wrote:
> I trying to integrate an IP block from a client and it has a ton of
> clock crossing, most of which are probably OK. 

Maybe. For a clean fix, consider
using a separate module for each clock domain
and run STA on those. Then use "known good"
synchronization techniques between the modules.

        -- Mike Treseler

Article: 120641
Subject: Re: XIlinx tools question - how to quickly identify unconstrained paths
From: johnp <johnp3+nospam@probo.com>
Date: Tue, 12 Jun 2007 14:45:20 -0700
Links: << >>  << T >>  << A >>
On Jun 12, 2:35 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> johnp wrote:
> > I trying to integrate an IP block from a client and it has a ton of
> > clock crossing, most of which are probably OK.
>
> Maybe. For a clean fix, consider
> using a separate module for each clock domain
> and run STA on those. Then use "known good"
> synchronization techniques between the modules.
>
>         -- Mike Treseler

Mike -

The IP comes from a client - I can't modify the code to that extent.
They
control the hierarchy and it's a mess.  Hence the need for the
unconstrained
report.

John P


Article: 120642
Subject: Virtex-4 pre-configuration pull-ups
From: Nobody Here <nobby@invalid.invalid>
Date: 12 Jun 2007 21:53:27 GMT
Links: << >>  << T >>  << A >>

I can't seem to find any data on the value of the "weak" pull-ups
on the IO pins during configuration if the HSWAPEN pin is configured
to give them.  Does anyone know approximately what value the pull
is?  I need to counter it for some logic - needs pulling down during
configuration.

Also, I'm confused about the direction of the HSWAPEN pin - one
set of documentation says pull down to enable pullups, but another
implies pull down to disable pullups.  Which is correct?

-- 
Thanks in advance.
Nobby Anderson

Article: 120643
Subject: Re: xilinx spartan3e kit ddr sdram
From: Kishore <kishore2k4@gmail.com>
Date: Tue, 12 Jun 2007 15:06:01 -0700
Links: << >>  << T >>  << A >>
On Jun 13, 1:10 am, emu <e...@ecubics.com> wrote:
> Hi all,
> is there any open source DDR SDRAM controller IP available (VHDL) for
> the DDR SDRAM on this kit ?

Opencores has one, check it out http://www.opencores.org/projects.cgi/web/ddr_sdr/overview


Article: 120644
Subject: Re: Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
From: bart <bart.borosky@latticesemi.com>
Date: Tue, 12 Jun 2007 15:26:37 -0700
Links: << >>  << T >>  << A >>
On Jun 12, 10:52 am, Antti <Antti.Luk...@googlemail.com> wrote:

> Xilinx does use digikey, so they also have NO MINIMUM order.
>
> I see no  difference here, BOTH ARE BAD in that sense that the latest
> and greatest silicon is NOT AVAILABLE.
>
> not from Xilinx online, not fromLatticeonline.
>
> Latticecould do an example here, and OFFER IMMEDIATE 1 OFF XP2
> example ONLINE orders
>
> I bet most people would instanlty order.
>
> just 1 per customer, GIFT PACKAGED XP2 sample. One click order, no
> questions, just PAY and get it.

Antti,
Mouser has been a Lattice distributor for quite some time. However,
now they are fulfilling our online store. This is new for Lattice. In
theory, it should make it easier for people to order small quantities
of Lattice devices right off the Lattice website, without having to go
to another website.
In contrast, all I see on the Xilinx website is purchase through Avnet
and NuHorizons, which my understanding, requires a minimum order. Of
course you could go off on your own to the Digikey website. Then find
the right part, etc...
We are trying to make the process easier and more straightforward,
that's all.

As for getting gift packaged samples of the LatticeXP2... I don't
think Lattice will offer any gift packaging to the general public.
However, once the LatticeXP2 product is in the next phase and we begin
to offer the parts through normal distribution channels, the
LatticeXP2 devices will be available on the online store. If you need
them now, please contact a Lattice sales person. Maybe ask a
salesperson nicely, and they will put a gift wrap on it for you?

~bart


Article: 120645
Subject: Re: XIlinx tools question - how to quickly identify unconstrained paths
From: nico@puntnl.niks (Nico Coesel)
Date: Tue, 12 Jun 2007 22:40:12 GMT
Links: << >>  << T >>  << A >>
johnp <johnp3+nospam@probo.com> wrote:

>I trying to integrate an IP block from a client and it has a ton of
>clock crossing, most of which are probably OK.  Up to now, I've
>run the Xilinx tools in an iterative mode - set constraints, run
>Translate, Map, P&R, then look at the timing report to find
>*some* unconstrained paths.
>
>Is there a Xilinx tool that will look at the Xst output and the UCF
>file and report the unconstrained paths without going through
>the time required to run (and rerun) Translate, Map, PAR?
>
>Thanks!
>
>John Providenza
>

A previous post in this group:

Phil Hays <spampostmaster@comcast.net> wrote:

>Nico Coesel wrote:
> 
>> In my experience this is always due to not properly constraining the
>> timing for the design somewhere. Which just makes me wonder if the tools
>> from Xilinx can produce a list with paths which are not covered by a
>> timing constraint.
>
>Yes. A few examples of how to produce timing reports with a list of
>unconstrained paths follow.
>
>
>From the command line:
>
>trce -v 10 -u 1000 design.ncd -o design.twr
>(the -u option is for list unconstrained paths)
>
>
>From Tcl:
>
>timing_analysis new analysis -name $reportname
>timing_analysis set $reportname analysis_type timing_constraint
>timing_analysis set $reportname report_datasheet true
>timing_analysis set $reportname report_timegroups true
>timing_analysis set $reportname analyze_unconstrained_paths 1000
>timing_analysis set $reportname paths_per_constraint 10
>timing_analysis set $reportname report_name $reportname
>timing_analysis set $reportname report_format ascii
>timing_analysis run $reportname
>
>
>From the GUI:
>
>In the process window
>  implement design
>    place and route
>      post place and route static timing properties:
>report uncovered paths      | 1000

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 120646
Subject: Re: Power consumption problem
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 13 Jun 2007 11:02:52 +1200
Links: << >>  << T >>  << A >>
Amine.Miled@gmail.com wrote:
> On 12 juin, 04:05, Jim Granville <no.s...@designtools.maps.co.nz>
> wrote:
> 
>>Amine.Mi...@gmail.com wrote:
>>
>>>Hi,
>>
>>>when i implemented my architecture using ACTEL AFS600 (Fusion family)
>>>i noticed that over 16MHz there is a gap in consumption, in fact when
>>>i was changing my frequency from 1 kHz to 16 Mhz the power consumption
>>>is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
>>>and the power consumption jump directly to 30 mW,
>>>anyone has any reason to explain this gap?
>>
>>>my speed grade is -2,
>>
>>Is it operating normally over that threshold ?
>>Normally, such a current discontinuity, also infers
>>an operational discontinuity.
>>
>>Does the slope continue at just under 0.5mW/Mhz above that threshold ?
>>
>>I'd test again with some simpler code, that you know has a very high Fmax.
>>
>>-jg
> 
> 
> that's the problem: the FPGA is still working good.
> Yes the slope continue at just 0.5mW/Mhz above that threshold,
> i tested the FPGA with other code and what s strange is that this
> discontinuity still exist but for higher frequency (again the fpga is
> still working good)

Yes, that does sound strange - what was the higher freq in the other test ?
16MHz should be 'low' by FPGA standards - were you using (or had 
enabled?) any of the PLL/Clock multiplier resources ?

Did you ask Actel ? - those symptoms suggest they might not
be disabling everything they should, in the SW process ?

-jg


Article: 120647
Subject: Re: adaptive filter FPGA
From: Marlboro <ccon67@netscape.net>
Date: Tue, 12 Jun 2007 16:54:24 -0700
Links: << >>  << T >>  << A >>
On Jun 10, 2:38 pm, "cutemonster" <ckh...@hotmail.com> wrote:
> >So you want to display a stroke signal on monitor?
> >Why you need to sample the X? Is it time dimension? Is it a constant
> >ramping, or ramping with retrace, or random?
>
> I have to sample x and y because it doesn't work like raster signal.  It's
> voltage varies in time. There is another signal input called Unblank(TTL).
> It turn on and off of XY signal.  

Have you tried to lock the sampling clocks to the unblank?


Article: 120648
Subject: Re: XIlinx tools question - how to quickly identify unconstrained paths
From: johnp <johnp3+nospam@probo.com>
Date: Tue, 12 Jun 2007 17:08:44 -0700
Links: << >>  << T >>  << A >>
On Jun 12, 3:40 pm, n...@puntnl.niks (Nico Coesel) wrote:
> johnp <johnp3+nos...@probo.com> wrote:
> >I trying to integrate an IP block from a client and it has a ton of
> >clock crossing, most of which are probably OK.  Up to now, I've
> >run the Xilinx tools in an iterative mode - set constraints, run
> >Translate, Map, P&R, then look at the timing report to find
> >*some* unconstrained paths.
>
> >Is there a Xilinx tool that will look at the Xst output and the UCF
> >file and report the unconstrained paths without going through
> >the time required to run (and rerun) Translate, Map, PAR?
>
> >Thanks!
>
> >John Providenza
>
> A previous post in this group:
>
>
>
> Phil Hays <spampostmas...@comcast.net> wrote:
> >Nico Coesel wrote:
>
> >> In my experience this is always due to not properly constraining the
> >> timing for the design somewhere. Which just makes me wonder if the tools
> >> from Xilinx can produce a list with paths which are not covered by a
> >> timing constraint.
>
> >Yes. A few examples of how to produce timing reports with a list of
> >unconstrained paths follow.
>
> >From the command line:
>
> >trce -v 10 -u 1000 design.ncd -o design.twr
> >(the -u option is for list unconstrained paths)
>
> >From Tcl:
>
> >timing_analysis new analysis -name $reportname
> >timing_analysis set $reportname analysis_type timing_constraint
> >timing_analysis set $reportname report_datasheet true
> >timing_analysis set $reportname report_timegroups true
> >timing_analysis set $reportname analyze_unconstrained_paths 1000
> >timing_analysis set $reportname paths_per_constraint 10
> >timing_analysis set $reportname report_name $reportname
> >timing_analysis set $reportname report_format ascii
> >timing_analysis run $reportname
>
> >From the GUI:
>
> >In the process window
> >  implement design
> >    place and route
> >      post place and route static timing properties:
> >report uncovered paths      | 1000
>
> --
> Reply to nico@nctdevpuntnl (punt=.)
> Bedrijven en winkels vindt U opwww.adresboekje.nl


My local FAE has suggested doing a post-Map but pre-PAR timing
extraction.  I'll
give that a try tomorrow.

John P


Article: 120649
Subject: Re: DVI-D Tx directly from FPGA?
From: Brian Davis <brimdavis@aol.com>
Date: Tue, 12 Jun 2007 18:24:09 -0700
Links: << >>  << T >>  << A >>
Eric Smith wrote:
>
> Can you get TMDS drivers that aren't part of a DVI
> transmitter chip (which also does the encoding)?
>
 The only thing I've spotted are the HDMI mux chips,
which do TMDS -> TMDS ( e.g. AD8190 )

>
> It doesn't appear that DVI transmitter chips cost much,
> so is it really worthwhile to try to avoid using one?
>
and MikeJ wrote:
>
> I looked into this, then realised you can buy a small chip
> which not only had a decent DAC to give you RGB analogue
> outputs, it also drives DVI.
>
 I think that makes great sense for a larger board,
especially if you also want the analog outputs.

 However, once someone writes a DVI Tx encoder and works
out a driver scheme for the S3E (or uses TMDS on S3A),
DVI is only a connector away...

 Beyond than the really important home projects,
like hi-def Asteroids, I also have some homebrew
RF test equipment in mind.

 In that case, if I'm doing several functions in one
small FPGA, I'd much rather have only 4 LVDS pairs
switching at my reference frequency, as contrasted
to 12-24 CMOS lines, driving another chip, switching
at its' own variable reference clock.

 I hopefully will have an S3E board set up for other
purposes in the next month or few, I'll try to look
at some LVDS -> TMDS biasing schemes when I do.

Brian




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