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jleslie48 wrote:
> why did the wizard that
> made up this testbench create a 100ms delay on the
> start, when that delay automatically puts me in a memory overrun
> error?
It was trying to encourage you to write your own code ;)
-- Mike Treseler
Article: 137626On Jan 23, 5:24 am, Florian Stock <st...@esa.informatik.tu- darmstadt.de> wrote: > rickman <gnu...@gmail.com> writes: > > Did HP claim that it would reduce the size of the interconnect by > > 95%? They have to provide ways of controlling each crossbar > > interconnect. That is not free in terms of real estate. Also, if > > they are going to design with local routing, there will need to be a > > way to control each segment individually. I am sure it will be more > > compact than the current configuration storage/pass transistor, but I > > doubt that it will be 95% smaller. A lot of the routing is just that, > > routing, and that does not get any smaller at all. > > This is the paper describing the process: > > http://www.iop.org/EJ/article/0957-4484/18/3/035204/nano7_3_035204.pdf I don't seem to have access. > It is a hyprid approach, logic is still CMOS (45nm), the routing is > nanotech. > > They compared such a FPNI (their name of the hybird) with pure CMOS only > (also 45nm) FPGA, and their results/estimations are: > > FPNI 30 (= 30nm nano routing) 1/8 area of cmos 22% slower than cmos only > FPNI 9 (= 9 nm nano routing) 4% area of cmos ~6 times slower than cmos I guess one could claim that the nano connects are 95% smaller, but I still don't know if this is a measurement of just the connects or how the measurement was made. More important is that the nano connects are 6 times slower!!! There is also the question of whether this was just a test of the connection, or if it was a realistic comparison of equivalent functions in a design that can do what current FPGAs can do in terms of the flexibility of the routing and degree of interconnect. > (of course this stuff is all conceptual, so do not trust their numbers > until you hold on of those in your hands (or you see at least a real > working prototype )). Exactly! As I often heard as I was growing up, "Don't believe anything you hear and only half of what you see." The trouble is knowing *which* half! RickArticle: 137627
On Jan 24, 4:21=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rickman <gnu...@gmail.com> wrote: > > (snip) > > > We are not talking about traces on a PCB, we're talking about the > > diameter of a wire in free space. =A0On a PCB the width affects the > > capacitance and therefore greatly affects the impedance. =A0In free > > space it has much less effect. > > Compared to a PC trace with a ground plane, yes. > > But if you have a wire of a given length and distance from > other wires through space and you need to reduce its impedance, > the only way is to increase the diameter. =A0 You need to consider context. There is nothing that Whygee can do with the width of his wires that will make a noticable difference in the way the free space wired SDRAM chip will work, other than possibly support it better. > > I told Whygee to limit the length of the wires in the power circuit > > and his reply was that he would keep the impedance of the power wires > > down by using fat wires. =A0With the power loop being a literal loop in > > the air, the length of the wire will by far outweigh the diameter of > > the wire in determining the impedance of the circuit. =A0I doubt that > > you would ever be able to measure the difference in impedance from > > changes in the width of the wires. > > Assuming that the inductance is much more important than series > resistance, probably true. =A0It isn't hard to get small enough > that resistance dominates, though. That makes no sense to me. He could use 30 gauge wire and still not have *any* noticeable resistance in this circuit. What sort of circuit are you picturing? RickArticle: 137628
http://www.xilinx.com/member/gbe_kit_ref/index.htm what i get is :( Message from the NSAPI plugin: No backend server available for connection: timed out after 10 seconds or idempotent set to OFF. Build date/time: May 1 2006 12:12:04 Change Number: 755164 looks like webmaster did take vaccation in 2006 and hasnt returned ? AnttiArticle: 137629
On Jan 24, 12:48=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > http://www.xilinx.com/member/gbe_kit_ref/index.htm > > what i get is :( > > Message from the NSAPI plugin: > > No backend server available for connection: timed out after 10 seconds > or idempotent set to OFF. > > Build date/time: May 1 2006 12:12:04 > > Change Number: 755164 > > looks like webmaster did take vaccation in 2006 and hasnt returned ? > > Antti I think you meant to say "broken still" I had trouble logging into the website yesterday. It kept redirecting me to account information. Today I see the same message you got. It's the secure server that has problems, not the public website. Regards, GaborArticle: 137630
On Jan 23, 5:57=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > <nna...@terra.es> wrote in message > > news:ab3f226a-9695-456d-b60b-fcd08cda835a@35g2000pry.googlegroups.com...>= I have a new design with a XCS05 based on a well proved design where > > the fpga runs during few minutes and then fails while expulses an > > extrange substance from inside the VCC and GND pins, in some pads is > > like spounge-white in other is black, the chip runs cold, never warms > > up. I have a lot of experience on this chip and I have never seen > > that. Then the chip appears to have a few inputs crossed to GND and > > worked never more. We crossed all the VCC pads with wire-wrapping with > > no results, no current loops. The prototype worked well (this is the > > first series PCB). Any Idea? > > Did you buy the parts off Ebay? > Syms. It doesn't necessarily have to be eBay. There are a number of non-franchised distributors who are not very careful about the source of their chips. If you have the working prototype, check to see if there are obvious differences in the part markings that might indicate that the new part is counterfeit. If you have more parts from the new batch you could also use an ohm-meter to check if the VCC and ground pins are in the right place. One standard counterfeiting method is to take some much cheaper chip in the same package and re-mark it. Regards, GaborArticle: 137631
Spoken (or written in this case) like an engineer: Great information, poor delivery. Thanks ... for the good info that is :-). "BobW" <nimby_GIMME_SOME_SPAM@roadrunner.com> wrote in message news:n9ydnU9yDP6Y7efUnZ2dnUVZ_hSWnZ2d@giganews.com... > > > > > "Rodo" <noway@youwish.com> wrote in message > news:Dvtel.1551$Aw2.414@nwrddc02.gnilink.net... >>I looked at the DDS info in the Altera site but I didn't see any mention >>that it was for the CPLDs. They talk about a megacore function and FPGAs. >>Can this be used in a MAX3000? >> >> I'm not doing anything fancy but cost and current consumption are an >> issue. I'd like to use as low a frequency I can to run the CPLD. Do you >> have any info on implementing a DDS? >> >> Thanks >> >> > > Do a web search for DDS. You'll find all the info you need. > > I used info from Google to design a DDS generator for a microcontroller. > You can do the same. If you can't then you should try a different career. > > Bob > -- > == All google group posts are automatically deleted due to spam == > > >Article: 137632
Antti <Antti.Lukats@googlemail.com> wrote: > http://www.xilinx.com/member/gbe_kit_ref/index.htm > what i get is :( > Message from the NSAPI plugin: > No backend server available for connection: timed out after 10 seconds > or idempotent set to OFF. > Build date/time: May 1 2006 12:12:04 > Change Number: 755164 > looks like webmaster did take vaccation in 2006 and hasnt returned ? There is a scheduled website update today (Jan 24) on the Xilinx site -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 137633
On Jan 24, 11:41=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: -> For lowest cost, probably the BCD rate multiplier is -> favourite. =A0But it's very jittery. The jitter can be mitigated with a post-divider - eg at 1MHz you miss pulses giving edge uncertainties in the 1-2us region, at 10MHz that becomes 100-200ns Depends on what the final application is, and what low power really means. Building an Oscillator with lower power than the CPLD, is likely to be a challenge. The post divider can include a Sine DAC if the OP wishes. -jgArticle: 137634
On Jan 24, 3:20=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Antti <Antti.Luk...@googlemail.com> wrote: > >http://www.xilinx.com/member/gbe_kit_ref/index.htm > > what i get is :( > > Message from the NSAPI plugin: > > No backend server available for connection: timed out after 10 seconds > > or idempotent set to OFF. > > Build date/time: May 1 2006 12:12:04 > > Change Number: 755164 > > looks like webmaster did take vaccation in 2006 and hasnt returned ? > > There is a scheduled website update today (Jan 24) on the Xilinx site > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Ah... you need to go to the home page to find that out: System Maintenance Notice Site registration and parts of Xilinx.com and International sites will be temporarily unavailable between 7:00AM - 7:00PM PST on Saturday, January 24th 2009. It's too bad the main forums page didn't have the notice. Also this doesn't explain why I had trouble logging in last night...Article: 137635
Now when xilinx web is back online, well they do no have not a single reference design for the ethernet using SFP optical links all the demos are for the marvell SGMII phy only i tried to change the TEMAC PHY form SGMII to 1000base-x but unfortunatly the system did not work after that. well all phy registers readback 0, so maybe there is some major problem with some clocking, and there are no other changes required, but i kinda can not belive that xilinx has not ever made a base1000-x based system for some of their board (ml405/ml505..) AnttiArticle: 137636
I am using 16 ISERDES primitives in 1:4 Networking mode. They all use the same clock. But in timing simulation the upper 8 ISERDES generate unknown output as soon as the clock is fed to it. At this time the D input to ISERDES is static. So I am bit puzzled as to why the 8 upper ISERDES generate unknown output. Any suggestions will be great. Thanks.Article: 137637
On 24 ene, 19:38, Gabor <ga...@alacron.com> wrote: > On Jan 23, 5:57=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > > > <nna...@terra.es> wrote in message > > >news:ab3f226a-9695-456d-b60b-fcd08cda835a@35g2000pry.googlegroups.com...= >Ihave a new design with a XCS05 based on a well proved design where > > > the fpga runs during few minutes and then fails while expulses an > > > extrange substance from inside the VCC and GND pins, in some pads is > > > like spounge-white in other is black, the chip runs cold, never warms > > > up. I have a lot of experience on this chip and I have never seen > > > that. Then the chip appears to have a few inputs crossed to GND and > > > worked never more. We crossed all the VCC pads with wire-wrapping wit= h > > > no results, no current loops. The prototype worked well (this is the > > > first series PCB). Any Idea? > > > Did you buy the parts off Ebay? > > Syms. > > It doesn't necessarily have to be eBay. =A0There are a number of > non-franchised distributors who are not very careful about > the source of their chips. =A0If you have the working prototype, > check to see if there are obvious differences in the part > markings that might indicate that the new part is > counterfeit. =A0If you have more parts from the new batch > you could also use an ohm-meter to check if the VCC > and ground pins are in the right place. =A0One standard > counterfeiting method is to take some much cheaper > chip in the same package and re-mark it. > > Regards, > Gabor No, I don't have any photo now and extrangelly there was no smoke, never in a lot of tests we did, holding my finger over the chip during the process I cannot dectect any temperature increment. Yesterday we tried to do an "incremental insertion" by inserting the fewest numbrer of chips and the problems came before inserting the XCS05. The cpu H83003 stops working in few minutes and a +1.5V -1V glitch appeared every 4ms in one of the 5V VCC lines lasting 40ns. One hypothesis is there were a current loop witch destroyed the weakest part, but for me is difficult to accept the idea of destroying a chip with this so little glitch. I am in the process of eliminating that glitch, not easy. Thanks to all Narcis NadalArticle: 137638
Hi All, I am trying to understand how to use the picoblaze soft-core. I have a verilog program that uses a counter and stops at a predicted value ( positive or negative). The value of this counter I would like to display on the LCD display of my SPARTAN 3AN. Is there a more simple way to do this than the picoblaze route ? If picoblaze is the best way to go, can someone please explain to me, step-by-step, how I would change the picpblaze code to display the value of the register. Please note that the 32'bit register value can be either presented as a negative value or positive decimal value. Thanks!Article: 137639
Hi All, We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory controller. Does anybody know how to create UCF constraints for dual memory controller in MIG 2.3? Dual memory controllers are only supported for Virtex 4&5. Cheers, AlesArticle: 137640
Hi, for such an application as controlling a display, a programmable solution like using a picoblaze is much more flexible than designing a dedicated FSM. There is an application note (at least for the Spartan 3E Starter Kit) that should work for you. Give it a try first. When it works continue like this: Expand the design with four Input ports to read in your counter value Write an assembler routine that converts your binary value to the code representation needed by the display ( maybe ASCII). Change the existing code to read in the ports and call your converting routine at a certain time. (Maybe your counter has a Ripple Output or EndCount Signal that you can feed to the Interrupt input of the picoblaze.) Have a nice synthesis Eilert uraniumore238@gmail.com schrieb: > Hi All, > > I am trying to understand how to use the picoblaze soft-core. I have a > verilog program that uses a counter and stops at a predicted value > ( positive or negative). The value of this counter I would like to > display on the LCD display of my SPARTAN 3AN. Is there a more simple > way to do this than the picoblaze route ? If picoblaze is the best way > to go, can someone please explain to me, step-by-step, how I would > change the picpblaze code to display the value of the register. Please > note that the 32'bit register value can be either presented as a > negative value or positive decimal value. > > Thanks!Article: 137641
>Hi Daniele, > >> WHAT'S WRONG? > >I am not sure but I think that the compiler is "case sensitive" ... >then: > >"xio_out32" --> "Xio_Out32" >"xio_in32" --> "Xio_In32" > >Kappa. > Ok, thanks. (ti ho aggiunto tra i contatti msn, grazie)Article: 137642
On 9 Gen, 16:20, sundeep <sundeep.bhan...@gmail.com> wrote: > On Jan 8, 5:26=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > sundeep wrote: > > > hello, > > > > I am looking to create amaccontroller which includes tcp/ip/dhcp. > > > Where can I get information on how to do this? > > >http://groups.google.com/groups/search?q=3Dfpga+arp+udp+dhcp > > so it seems tcp/ip/dhcpwould take up too many resources using anfpga > and a microcontroller would be a better approach for this. > > I wasn't able to find information on how to simulate a mac controller. > Where can I find flow charts/block diagrams for this? Hi, I have develop a UDP sender and Receive core in VHDL. I have a spartan3e and ths core uses only 8 % of resources...but with some tuning it can be lower. The main problem (now) is ARP management. if you are interested contact me at alexgiul@hotmail.com.Article: 137643
On Jan 25, 11:51=A0pm, ales.gor...@gmail.com wrote: > Hi All, > > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory > controller. > Does anybody know how to create UCF constraints for dual memory > controller in MIG 2.3? Dual memory controllers are only supported for > Virtex 4&5. > > Cheers, > > Ales I guess Xilinx did not see why should anyone want to connect dual bank DDR2 memories to S3 Maybe the 11.1 do provide support for S3 too, but need wait til may :( AnttiArticle: 137644
I am using RAMB4_S4 to handle some data. But when I use this as a component, a new ram is created for each gate. How can I make this ram common?Article: 137645
On Jan 26, 2:36 pm, Antti <Antti.Luk...@googlemail.com> wrote: > On Jan 25, 11:51 pm, ales.gor...@gmail.com wrote: > > > Hi All, > > > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and > > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory > > controller. > > Does anybody know how to create UCF constraints for dual memory > > controller in MIG 2.3? Dual memory controllers are only supported for > > Virtex 4&5. > > > Cheers, > > > Ales > > I guess Xilinx did not see why should anyone want to connect dual bank > DDR2 memories to S3 > > Maybe the 11.1 do provide support for S3 too, but need wait til may :( > > Antti May??? I cannot wait untill May. alesArticle: 137646
On 25 Jan, 21:51, ales.gor...@gmail.com wrote: > Hi All, > > We are developing a custom borad with Spartan 3A DSP 1800 (FG676) and > dual x16 DDR2 SDRAMs. Address lines shoud be separated for dual memory > controller. > Does anybody know how to create UCF constraints for dual memory > controller in MIG 2.3? Dual memory controllers are only supported for > Virtex 4&5. > > Cheers, > > Ales I've had to do the exact same thing, I did it by generating 2 seperate MIG cores, and for the second one I use the ucf from the first to prohibit the pin placements. The generation of the second MIG core was purely to get a second ucf file. It then involved a bit of manual playing around with the VHDL to instantiate the second controller, and then changing the signal names in the second ucf file to those for the second controller. It was a little while ago that I did this, but I think that was what I did. NeillArticle: 137647
Hello, I am getting the following map error. ERROR:MapLib:979 - LUT3 symbol "vio_inst/U0/I_VIO/GEN_SYNC_IN[16].SYNC_IN_CELL/ ASYNC_F_MUX" (output signal=vio_inst/U0/I_VIO/GEN_SYNC_IN[16].SYNC_IN_CELL/ async_mux_f_out) has input signal "vio_inst/U0/I_VIO/GEN_SYNC_IN[16].SYNC_IN_CELL/ falling_out" which will be trimmed. See Section 5 of the Map Report File for details about why the input signal will become undriven. I am getting a total of 96 such errors. As per one of the Xilinx answer records http://www.xilinx.com/support/answers/30477.htm it asks to turn off the read cores Synthesis option. I am still getting the same error after turning off the read cores option. Please suggest a solution for this as soon as possible. ThanksArticle: 137648
Ok finally,
I've got a working UART. I initially had it monitor the receive line
and echo back out the character that it received.
I then changed it so that just sent the the letter 'U' by stuffing the
hex code in the TX_DATA_IN buffer:
TX_DATA_IN( 7 DOWNTO 0 ) <= x"55";
so
1) instead of manually coverting 'U' to x'55', how do I use a
string literal to do the job.
for instance in C, I would simply write:
tx_data_in = 'U';
which is the same as the c code:
tx_data_in = 0x55;
my point is, I want to be able to use the ascii character instead of
the hexidecimal code.
2) I want a scheduler so that I can put out whole messages. I want to
be able to write on the uart, "I got it\n"
I can see a language element in VHDL called string:
constant char_sequence : string := "I got it";
but I'm not sure if that is the right way to do it. in addition, I
don't now how to send the characters of char_sequence out
sequentially.
here is my transmit process:
-------------------------------------------------------------------------------------------------
-- LATCHING NEW TRANSMIT DATA FROM RECEIVE UART ( TX_DATA_IN
[ 7-0 ] )
-------------------------------------------------------------------------------------------------
P7: PROCESS ( CLK_16_6MHZ, UART_RESET_BUFFER, RX_READ_BUFFER_STB,
RX_DATA_OUT( 7 DOWNTO 0 ) )
BEGIN
IF ( CLK_16_6MHZ = '1' AND CLK_16_6MHZ'EVENT ) THEN
IF ( UART_RESET_BUFFER = '0' ) THEN
IF ( RX_READ_BUFFER_STB = '1' ) THEN
TX_DATA_IN( 7 DOWNTO 0 ) <= x"55";
END IF;
END IF;
END IF;
END PROCESS P7;
now the x"55"; is gonna have to change, but I imagine that this
process will need
to an entity in another process that is aware of the characters "I got
it" and schedule the
8 characters (I, ,g,o,t, ,i,t) to go out.
Sincerely,
Jon
Article: 137649On Jan 26, 8:52=A0am, "malavica" <malav...@gmail.com> wrote: > I am using RAMB4_S4 to handle some data. But when I use this as a > component, a new ram is created for each gate. How can I make this ram > common? Since you are using it as a component, instantiate it only once, and interface to that instance from everywhere it is needed. Andy
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