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On 7 Mai, 22:13, "Xin Xiao" <s...@spam.com> wrote: > Hi! > > I've heard that FPGAs are good for doing some cryptography... Do any of you > have experience in cryptography projects and FPGAs? > > What tools are available? (better if they are free). > I suppose I have to code in C/C++ and then synthesize that code to the > hardware using a tool? > > Thanks, Hi Xin, yes, cryptographic hardware in FPGAs has the advantage of performance, compared to any software solution. There are papers that give some numbers like AES in a 100MHZ clocked FPGA can acheive about 10 times more data througput than on a 3GHz Pentium processor. (While consuming less energy!) Almost any vendor has a free tool to begin with, but they are all based on VHDL/Verilog. Digital circuit design is different from programming algorithms. Be aware of that. Read some datasheets, to get the idea of FPGAs. Then proceed with learning a Hardware Description Language. Then you can try to express your algorithms in hardware. Have a nice synthesis EilertArticle: 140301
Hi .. I'm working on a project which involves a design that has NiOS II processor, DDRSDRAM, SSRAM, a custom Ethernet MAC and other components and I've to run an application on it.. I use NiOS II embedded Evaluation board(Cyclone III), quartus 8.1 web edition. Since I'm new to Altera, I would like to start with a simple design with an ethernet MAC , then send and recieve packets through it. I'm not strong in Ethernet concepts too. I feel that the design with TSE MAC and socket server example are too high at this level of me to understand. So can anyone send me a design which has a MAC and also tell me how to send and recieve packets over it? If possible, can you send me supporting documents for mastering the concepts of ethernet. Thanks and Regards RenuArticle: 140302
On May 8, 12:53=A0am, Jukka Marin <jma...@pyy.embedtronics.fi> wrote: > Dear All, > > I'm wondering whether to use 10/100 Ethernet and CAN controller chips > (two of each) in a new design or just put cores from OpenCores inside > an FPGA (which we will need in both cases). =A0I'm (still) new to FPGA's > and have never used cores from OpenCores. =A0Has anybody used these cores= ? > Are they reliable and ready for production use? > > The third alternative is to buy commercial IP blocks, but I'm afraid > they might cost more than the old-fashioned way (the production volumes > will be relatively small). > > I'd appreciate any facts and/or opinions. :) > > =A0 -jm You can look at the ehternet cores from MANTARO NETWORKS (http:// www.mantaro.com/services/fpga.htm). They have very good costs for there cores as they have developed them from there partners in low costsArticle: 140303
On May 7, 12:25=A0pm, recoder <kurtulmeh...@gmail.com> wrote: > Hi FPGA Gurus, > =A0I need to get a Gigabit Ethernet message, change its destination > IP,change some bits in the message(process) and send it out. I figure > out that I need 2 GigE ports to do that. I don't want to pay for the > MAC, so the board should be built with the Virtex 5 FPGAs or Altera > alternatives. > =A0Does a board like this exists? Hello, Yes, this dual GigE board exists at Sundance. Have a look at the SMT945 from Sundance Multiprocessor Technology? It features a dual Gigabit Ethernet ports (i.e. 2 GigE ports) and you can use it with the SMT900 EVM that has a Virtex-5. You would then be able to implement your logic in the Virtex-5 FPGA. SMT945 Dual GigE mezzanine card: http://www.sundance.com/web/files/productp= age.asp?STRFilter=3DSMT945 SMT900 Virtex-5 EVM: http://www.sundance.com/web/files/productpage.asp?STRF= ilter=3DSMT900 Best Regards, - SebastienArticle: 140304
http://www.fpga4fun.com/10BASE-T.htmlArticle: 140305
On May 7, 9:13=A0pm, "Xin Xiao" <s...@spam.com> wrote: > Hi! > > I've heard that FPGAs are good for doing some cryptography... Do any of y= ou > have experience in cryptography projects and FPGAs? > > What tools are available? (better if they are free). > I suppose I have to code in C/C++ and then synthesize that code to the > hardware using a tool? > > Thanks, You have have a look at the Xilinx application note about encryption: http://www.xilinx.com/support/documentation/white_papers/wp261.pdf - Sebastien www.sundance.comArticle: 140306
On Thu, 7 May 2009 20:52:47 -0700 (PDT), rickman wrote: >On May 7, 9:06 pm, Peter Alfke wrote: >> Here is a short Xilinx tutorial: >I don't think anyone has a problem understanding how the parts work. >The issue we are having is how to specify the hardware we want in the >HDL. Rick is right, but Peter's explanation is perhaps timely. It's comparatively easy to describe both write-first and read-first behavior in HDL if there is only one write port, but it's a lot more tricky (especially in VHDL) if there are two write ports with independent clocks. But the main problem is as Peter pointed out: there are some corner cases (for example, simultaneous write to the same location from both write ports) whose behavior is ill-defined. Of course, sensible designers will ensure that their memory controller never allows those ill-defined cases to occur. But you can't easily explain to your synthesis tool that you have done so. As a result, the synth tool must take your HDL description at face value, and do whatever it takes to ensure that the finished hardware obeys that description *in all cases* - hence the nonsense with logic (which wouldn't work right anyway) to avoid conflicting writes to the same address, because your HDL says that the behavior is well-defined but the memory doesn't work quite like that. As promised, I'll take this offline, do some work on it over the weekend, and report back. I haven't yet seen a concise description of the right way to cope with this across a range of synth tools, so it's something I'd like to do anyway. If all else fails, I can grudgingly go back to instantiation of wizard-generated components. But I don't like doing that; it screws up my design's portability, makes simulation tiresome and slow, and makes the HDL code butt-ugly. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140307
This question is Quartus II specific but I figured since this would the proper place to find at least one person with this problem. I want to use the fixed point package provided here: http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=vhdl I can compile the library and use the files, but a problem arises when I create a schematic file and try to synthesize. To use the fixed point numbers I have to declare the bus width like so: var_name sfixed (1 downto -30) When I create a block out the file and try to synthesize it, I get an error about illegal bus width "-30". Is there a way to get around this? Or I cannot use negative numbers as a bus width? ThanksArticle: 140308
"Chico" <jcuello@gmail.com> wrote in message news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com... > This question is Quartus II specific but I figured since this would > the proper place to find at least one person with this problem. > > I want to use the fixed point package provided here: > http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=vhdl > > I can compile the library and use the files, but a problem arises when > I create a schematic file and try to synthesize. Don't create a 'schematic file' to synthesize. Just use the VHDL packages directly. I've used them with Quartus and not had any problems. KJArticle: 140309
On May 8, 9:04=A0am, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Chico" <jcue...@gmail.com> wrote in message > > news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com... > > > This question is Quartus II specific but I figured since this would > > the proper place to find at least one person with this problem. > > > I want to use the fixed point package provided here: > >http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=3Dvhd= l > > > I can compile the library and use the files, but a problem arises when > > I create a schematic file and try to synthesize. > > Don't create a 'schematic file' to synthesize. =A0Just use the VHDL packa= ges > directly. =A0I've used them with Quartus and not had any problems. > > KJ I was thinking of doing that, but I need to assign a PIN to my inputs/ outputs. Is there a way to do that without using a schematic file through VHDL? I am using Quartus II 8.0.Article: 140310
On Thu, 07 May 2009 22:13:52 +0200, Xin Xiao wrote: > Hi! > > I've heard that FPGAs are good for doing some cryptography... Do any of > you have experience in cryptography projects and FPGAs? "Cryptography projects and FPGAs" describes aspects of my job. FPGAs aren't necessarily the best approach though. If you are using (or breaking!) standard algorithms, then there are off-the-shelf ASICs that compete favourably with FPGAs for development time, speed and power. E.g. google for Cavium Nitrox. As an example of performance, some years ago I was able to generate 20Gb/ s of AES256 CTR mode keystream in a Xilinx Virtex2Pro part. That design was I/O limited. *Much* higher performance would be achievable in a more modern part or with a design that wasn't I/O limited. (BTW, I've done more interesting things since that design, but I can't talk about them in a public forum.) I imagine that past about 100Gb/s, the performance would be limited by thermal constraints rather than chip area or clock speed. Newer FPGA families are better in this regard. > What tools are available? (better if they are free). I suppose I have to > code in C/C++ and then synthesize that code to the hardware using a > tool? I recommend HDLs (e.g. VHDL or Verilog) over languages that weren't designed for hardware description (e.g. C/C++). The tools that come from the FPGA vendors are cheap or free and effective. You can get open source cores (in VHDL or Verilog) for many of the commonly used cryptographic primitives (e.g. block ciphers like AES or DES). I am not going to claim that the open source cores are efficient or achieve good performance, but they might be a good place to start. I haven't found any good free cores for things like GCM or ECC or factoring. Regards, AllanArticle: 140311
Hi, The argument of getting a FPGA to replace a DSP is similar to the =93Chicken & Egg=94 story. Not worth having! I have on many occasion been involved with potential customers that were =91sold=92 the idea that a FPGA could do everything and a DSP was not needed. Similar, the DSP semiconductors suppliers, like TI, Analog Device, etc. has been praising the level of integration that can be found on =91Generic=92 DSP device and stated that a FPGA is surplus to requirement. My general feeling is that a DSP + FPGA offers everything. The DSP is cheap, easy to program, runs cool and offers a lot of integration, whereas the FPGAs are expensive, hard to program (compared to a processor) =96 but offer much faster performance, support for any kind of I/O interface, re-programmable, etc. =96 and if you really have a high-quantity product, then you would surely want to prototype on a DSP + FPGA, before moving to a custom ASIC device. A number of suppliers can be found on the Web that offers development boards with DSP + FPGAs and a growing number of software package can be bought that makes it possible to use Model-based design for BOTH the FPGA and the DSP. I suggest some R&D and watching YouTube clips. Happy reading Rgds Flemming ChristensenArticle: 140312
Hello guys, I am working on a virtex 5 and trying to read out data from internal distributed ROM at 250MHz. Then in order to increase data rate, I choose use ODDR which is followed by OBUF. But in the MAP I have this kind of errors at all the output of ODDR as following, "ERROR:Pack:1569 - The dual data rate register QPSK_wave/LOOP_DDR_A[6].ODDR_A failed to join an OLOGIC component as required." I don't have any idea to solve this error. Is there someone can give me some hint? Another question, I have also tried to use OSERDES which is parallel-to-serial converter before OBUF. Then the design pass the map but in place and route it came out the warning as following, "Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement or unroutable placement constraints." and occured in all the output pin of OSERDES. How to solve this? Is there any other method to increase data rate? When I reached to 500MHz, the timing problem was always with me in post route simulation. Thank you for help!!Article: 140313
Jonathan Bromley wrote: > I haven't > yet seen a concise description of the right way to > cope with this across a range of synth tools, so > it's something I'd like to do anyway. I long ago gave up trying, so I will be interested to see your results. > If all else fails, I can grudgingly go back to > instantiation of wizard-generated components. > But I don't like doing that; it screws up my > design's portability, makes simulation tiresome > and slow, and makes the HDL code butt-ugly. I agree with the downside, but I stick with Peter's "simple dual-port" block rams which are portable across vendors and tools, with the same template. This is all I need for fifos. I use multiple instances and my own synchronous controllers to make more complicated memories. -- Mike TreselerArticle: 140314
http://lmgtfy.com/?q=instantiate+oddr+virtex+5+site:xilinx.com ;-)Article: 140315
"Chico" <jcuello@gmail.com> wrote in message news:713706ae-f03d-439c-97c5-591e2a804fb1@z19g2000vbz.googlegroups.com... On May 8, 9:04 am, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Chico" <jcue...@gmail.com> wrote in message > > news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com... > > > This question is Quartus II specific but I figured since this would > > the proper place to find at least one person with this problem. > > > I want to use the fixed point package provided here: > >http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=vhdl > > > I can compile the library and use the files, but a problem arises when > > I create a schematic file and try to synthesize. > > Don't create a 'schematic file' to synthesize. Just use the VHDL packages > directly. I've used them with Quartus and not had any problems. > > KJ I was thinking of doing that, but I need to assign a PIN to my inputs/ outputs. Is there a way to do that without using a schematic file through VHDL? I am using Quartus II 8.0. I don't know how VHDL would look, but the following works in Quartus for Verilog code: input SYNC_IN /* synthesis altera_chip_pin_lc = "5"*/; output SYNC_OUT /* synthesis altera_chip_pin_lc = "39"*/; input SW_2 /* synthesis altera_chip_pin_lc = "18"*/; input SW_1 /* synthesis altera_chip_pin_lc = "21"*/; output LED1 /* synthesis altera_chip_pin_lc = "37"*/; output LED2 /* synthesis altera_chip_pin_lc = "22"*/; Look in the Help file under Synthesis Attributes Wade HasslerArticle: 140316
>http://lmgtfy.com/?q=instantiate+oddr+virtex+5+site:xilinx.com > >;-) > > > Thank you for reply. But I have already read the library and the template of the ODDR. However my problem is in the map. The unit cannot be mapped. I want to figure out how to solve this situation.Article: 140317
On May 8, 6:39 am, Chico <jcue...@gmail.com> wrote: > On May 8, 9:04 am, "KJ" <kkjenni...@sbcglobal.net> wrote: > > > > > "Chico" <jcue...@gmail.com> wrote in message > > >news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com... > > > > This question is Quartus II specific but I figured since this would > > > the proper place to find at least one person with this problem. > > > > I want to use the fixed point package provided here: > > >http://www.accellera.org/apps/group_public/documents.php?wg_abbrev=vhdl > > > > I can compile the library and use the files, but a problem arises when > > > I create a schematic file and try to synthesize. > > > Don't create a 'schematic file' to synthesize. Just use the VHDL packages > > directly. I've used them with Quartus and not had any problems. > > > KJ > > I was thinking of doing that, but I need to assign a PIN to my inputs/ > outputs. Is there a way to do that without using a schematic file > through VHDL? I am using Quartus II 8.0. Yes. This is well documented in the manual. And the tutorial. And in several download-able examples. ALArticle: 140318
Flemming@Sundance <Flemming.C@sundance.com> wrote: > The argument of getting a FPGA to replace a DSP is similar to the > ?Chicken & Egg? story. Not worth having! > I have on many occasion been involved with potential customers that > were ?sold? the idea that a FPGA could do everything and a DSP was not > needed. Similar, the DSP semiconductors suppliers, like TI, Analog > Device, etc. has been praising the level of integration that can be > found on ?Generic? DSP device and stated that a FPGA is surplus to > requirement. If the DSP can't do everything, and you need an FPGA, and the FPGA with a soft processor can do what is needed, then the FPGA is likely a good choice. > My general feeling is that a DSP + FPGA offers everything. The DSP is > cheap, easy to program, runs cool and offers a lot of integration, I won't disagree, though not so obvious. > whereas the FPGAs are expensive, The prices are coming down pretty fast for the smaller ones. > hard to program (compared to a processor) Well, you can design a simple (or not so simple) processor into the FPGA and then program that. There are a few specifically designed for efficient FPGA implementation. > but offer much faster performance, support for any kind > of I/O interface, re-programmable, etc. ? and if you really have a > high-quantity product, then you would surely want to prototype on a > DSP + FPGA, before moving to a custom ASIC device. FPGAs offer much higher performance if you can do many operations in parallel. That is often easier in an FPGA, but it is not automatic. The actual clock rate is likely slower in the FPGA, but if you can do many more operations per clock cycle the throughput can be very high. > A number of suppliers can be found on the Web that offers development > boards with DSP + FPGAs and a growing number of software package can > be bought that makes it possible to use Model-based design for BOTH > the FPGA and the DSP. -- glenArticle: 140319
Allan Herriman <allanherriman@hotmail.com> wrote: > On Thu, 07 May 2009 22:13:52 +0200, Xin Xiao wrote: >> I've heard that FPGAs are good for doing some cryptography... Do any of >> you have experience in cryptography projects and FPGAs? > "Cryptography projects and FPGAs" describes aspects of my job. > FPGAs aren't necessarily the best approach though. If you are using (or > breaking!) standard algorithms, then there are off-the-shelf ASICs that > compete favourably with FPGAs for development time, speed and power. > E.g. google for Cavium Nitrox. For normal use, I might agree. It is not so obvious that it is the best way to build code breakers. Also, it seems that encryption is a small part of the Cavium Nitrox. A dedicated ASIC (if one exists) might be faster/cheaper. > As an example of performance, some years ago I was able to generate 20Gb/ > s of AES256 CTR mode keystream in a Xilinx Virtex2Pro part. That design > was I/O limited. *Much* higher performance would be achievable in a more > modern part or with a design that wasn't I/O limited. The other advantage to FPGA is that you can reprogram it when new algorithms appear. > (BTW, I've done more interesting things since that design, but I can't > talk about them in a public forum.) > I imagine that past about 100Gb/s, the performance would be limited by > thermal constraints rather than chip area or clock speed. Newer FPGA > families are better in this regard. > >> What tools are available? (better if they are free). I suppose I have to >> code in C/C++ and then synthesize that code to the hardware using a >> tool? > I recommend HDLs (e.g. VHDL or Verilog) over languages that weren't > designed for hardware description (e.g. C/C++). > The tools that come from the FPGA vendors are cheap or free and effective. (snip) The implementation is likely very different in serial C than in an appropriately parallel HDL implementation. (I believe systolic arrays would work in this case.) -- glenArticle: 140320
"lioncat" <dominghang@hotmail.com> wrote in message news:gI2dnYJKlIWPz5nXnZ2dnUVZ_oGdnZ2d@giganews.com... >> > Thank you for reply. But I have already read the library and the template > of the ODDR. However my problem is in the map. The unit cannot be mapped. > I > want to figure out how to solve this situation. So, even if you use the exact template they suggest, maybe with a really simple experimental design, the map doesn't work? Did you also try looking at XAPPs with DDR? What about the FDDRRSE part, did you try that? HTH., Syms.Article: 140321
On May 8, 8:20=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > Jonathan Bromley wrote: > > I haven't > > yet seen a concise description of the right way to > > cope with this across a range of synth tools, so > > it's something I'd like to do anyway. > > I long ago gave up trying, so I will be interested > to see your results. > > > If all else fails, I can grudgingly go back to > > instantiation of wizard-generated components. > > But I don't like doing that; it screws up my > > design's portability, makes simulation tiresome > > and slow, and makes the HDL code butt-ugly. > > I agree with the downside, > but I stick with Peter's "simple dual-port" block rams > which are portable across vendors and tools, > with the same template. > > This is all I need for fifos. > I use multiple instances and my own synchronous > controllers to make more complicated memories. > > =A0 -- Mike Treseler This is not a Xilinx or Altera circuit design problem, nor is it a VHDL problem. It is a systems design issue. My favorite solution is to clock the two ports on opposite clock polarity edges. "If you cannot solve it, avoid it." Peter AlfkeArticle: 140322
On Fri, 08 May 2009 16:06:37 +0000, glen herrmannsfeldt wrote: > > The other advantage to FPGA is that you can reprogram it when new > algorithms appear. Good point. The field is quite dynamic as old algorithms are discovered to be broken and new algorithms are developed to replace them. The timescale is such that there's a good chance that an algorithm might need to be replaced during the lifetime of a product. Some examples: MD5 is now known to be not collision resistant, and it probably shouldn't be used. Sha-1 is broken in the cryptographic sense (but still has useful security). IIRC it is no longer allowed for certain secrecy levels. Sha-3, a new US hash standard is due in 2012, however (as with AES) we will know the details well in advance. One of the DRNGs (the one developed by NSA that uses EC) in the NIST spec SP800-90 has a suspected backdoor that was discovered in 2007. Regards, AllanArticle: 140323
peter@xilinx.com wrote:
> This is not a Xilinx or Altera circuit design problem, nor is it a
> VHDL problem.
> It is a systems design issue.
Some existing FPGA structures like PLLs and dpram arbiters
can't be described by a synchronous process.
My synthesis code can either instance the netlist or use something else.
> My favorite solution is to clock the two ports on opposite clock
> polarity edges.
If I couldn't avoid two write ports, I would time slice one clock.
> "If you cannot solve it, avoid it."
True. But I can't avoid talking about it ;)
... and what is the time limit on 'cannot solve it'?
-- Mike Treseler
Article: 140324On May 8, 8:42 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Thu, 7 May 2009 20:52:47 -0700 (PDT), rickman wrote: > >On May 7, 9:06 pm, Peter Alfke wrote: > >> Here is a short Xilinx tutorial: > >I don't think anyone has a problem understanding how the parts work. > >The issue we are having is how to specify the hardware we want in the > >HDL. > > Rick is right, but Peter's explanation is perhaps > timely. It's comparatively easy to describe both > write-first and read-first behavior in HDL if there > is only one write port, but it's a lot more tricky > (especially in VHDL) if there are two write ports > with independent clocks. But the main problem is > as Peter pointed out: there are some corner cases > (for example, simultaneous write to the same location > from both write ports) whose behavior is ill-defined. > Of course, sensible designers will ensure that > their memory controller never allows those ill-defined > cases to occur. But you can't easily explain to > your synthesis tool that you have done so. As a result, > the synth tool must take your HDL description at face > value, and do whatever it takes to ensure that the > finished hardware obeys that description *in all > cases* - hence the nonsense with logic (which > wouldn't work right anyway) to avoid conflicting > writes to the same address, because your HDL says > that the behavior is well-defined but the memory > doesn't work quite like that. > > As promised, I'll take this offline, do some work > on it over the weekend, and report back. I haven't > yet seen a concise description of the right way to > cope with this across a range of synth tools, so > it's something I'd like to do anyway. > > If all else fails, I can grudgingly go back to > instantiation of wizard-generated components. > But I don't like doing that; it screws up my > design's portability, makes simulation tiresome > and slow, and makes the HDL code butt-ugly. I don't like the instantiation approach either. But I don't pretend to expect that inference is just a matter of finding the right way to describe a dual port memory. If the chip makers and the tool vendors can't tell us how to do it, then I can only assume that is because it doesn't work. I think the way to solve this problem is not by trying to be creative in writing code, rather a direct conversation with the vendors is needed. I tried looking in all sorts of Xilinx docs and the only one that has example code for write first dual port block ram is the XST manual, equivalent to the Verilog code shown earlier in the thread. I tried that and got the following error... ERROR:Xst - You are apparently trying to describe a RAM with several write ports for signal <Mram_RAM>. This RAM cannot be implemented using distributed resources. --> So it clearly understands what I am trying to do, but still wants to use distributed ram! One thing I find odd is that they are using a variable for the RAM and perform the write before the read. But then they give two examples for write first memory, one that has direct logic to mux the input data and the memory data. The other uses the sequence of the assignments to infer the write first behavior. Either way gives the same error. I guess I would have expected the vendors to know how to use their own software. Rick
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