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Hi, first off, this subject keeps bugging me since i work with (Xilinx) FPGAs. So,..there is an OFFSET OUT constraint to specify for Outputs. So far i understand from timing reports, PAR evaluates OFFSET OUT as a maximum value. But...design i'm currently doing restricts me also for suppliying a minimum clock-to-output constraint. Seems like this is currently not possible with xilinx tools...am i right? I need to specify an maximum and minimum value for OFFSET OUT. All i can do is...after PAR finishes...do timing anaylsis with "Report fastest paths/verbose hold paths" check box selected. This gives me the setup/hold paths for all timing paths avaliable in the design, right? So at least i can check what my current min. clk-to-out delay is. And, i found also something like Speedgrade -0 for checking best case timing results. (referring to http://www.xilinx.com/support/answers/4506.htm) Do someone know the difference. ThanksArticle: 140126
Hi How do I tell quartus that a signal has a propergation delay of 2 clocks? That is to say the value does not have to become valid for 2 clocks, instead of the usual 1 clock. You geussed this is the current fmax path, and so all other timing is being affected. The 2 clock limit is correct as far as operation is concerned, but the fmax result is adversly wrong. cheers jackoArticle: 140127
Hello there, I want use a GCLK pin in a Xilinx CPLD as a regular input. Unfortunatelly the fitter designates it to global clock. How can I tell to the fitter that this input is a regular data signal? I've tried the BUFG constraint in the UCF file, but didn't success. GCLKs can operate as regular output so I think they have to able to work as regular input too.. Am I wrong? Many thanks in advance David FejesArticle: 140128
"jleslie48" <jon@jonathanleslie.com> wrote in message news:89daa806-4c77-4677-8e2f-c1c9f2426060@d25g2000prn.googlegroups.com... > > So I'm perfectly fine having the two 3.3 volts values on both wires. > I just wanted to make sure. My first two years with the company I > earned a reputation for smoking equipment (I toasted easily $70,000 > worth of stuff,) and I'm determined this year to not fry anything. > Maybe you should take a basic course in electronics. /MikhailArticle: 140129
Hi I'm considering the option of converting an FPGA design into ASIC, but have no experience with that. My questions are: 1) Cost savings, how do ASICs compare to FPGAs? 2) Given VHDL that works on FPGA, will there be considerable risk associated with the ASIC conversion? 3) How long can it take to have working chips? 4) Who can do it? Do you have any recommendation? Thanks a lot! Regards, MarcArticle: 140130
There is a SD socket module that fits a a number of our boards. outline details http://www.enterpoint.co.uk/moelbryn/modules/mmc_sdcard.html. John Adair Enterpoint Ltd. On 24 Apr, 13:37, muthu...@gmail.com wrote: > Hello, > > I am planning to evaluate a SD/SDHC Host Controller. Do Xilinx has any > suitable evaluation boards? From the Websearch, I couldn't find any > Xilinx board with SD/SDHC card interface. > > Best regards, > MuthuArticle: 140131
On Wed, 29 Apr 2009 08:20:19 -0700 (PDT), jacko <jackokring@gmail.com> wrote: >Hi > >How do I tell quartus that a signal has a propergation delay of 2 >clocks? > >That is to say the value does not have to become valid for 2 clocks, >instead of the usual 1 clock. You geussed this is the current fmax >path, and so all other timing is being affected. The 2 clock limit is >correct as far as operation is concerned, but the fmax result is >adversly wrong. set_multicycle_path is what you need. Check out http://www.altera.com/literature/an/an481.pdf -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140132
jacko wrote:
> How do I tell quartus that a signal has a propergation delay of 2
> clocks?
> That is to say the value does not have to become valid for 2 clocks,
> instead of the usual 1 clock. You geussed this is the current fmax
> path, and so all other timing is being affected. The 2 clock limit is
> correct as far as operation is concerned, but the fmax result is
> adversly wrong.
Because I find timing constraints tedious,
I generate synchronous clock enable strobes
at just the right tick.
If the strobe isn't used otherwise,
the register gets optimized away.
For example, a_v'left, below becomes
an asynch carry out.
-- Mike Treseler
_________________________________________
if a_v(a_v'left) = '1' then -- a carry?
a_v(a_v'left) := '0'; -- clear carry
b_v := b_v + 1;
...
Article: 140133On Wed, 29 Apr 2009 10:08:31 -0700 (PDT), jetmarc@hotmail.com wrote: >Hi > >I'm considering the option of converting an FPGA design into ASIC, but >have no experience with that. My questions are: > >1) Cost savings, how do ASICs compare to FPGAs? > ASICs are very high NRE and low incremental unit cost so to get any cost saving at all you have to get a large number of chips made. As a first approximation you can assume that you'll have to spend $1M to get an ASIC made and say $1 per chip after that. To get any cost savings you need to buy ~1M/X (where $X is per fpga you're buying now). If you're buying $50 FPGAs, you need 20K of them just to break even (barely). Are you close to that number? >2) Given VHDL that works on FPGA, will there be considerable risk >associated with the ASIC conversion? > Yes. See my answer to the first question before asking for a list. >3) How long can it take to have working chips? > Depending on the size of the design 6 to 9 months (3+ months from tape-out to packaged chips, the rest for porting and verification) >4) Who can do it? Do you have any recommendation? Lot companies do this for a living. We have done it a couple of times. Try: http://www.google.com/#hl=en&q=fpga+to+asic+conversion -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140134
> > Your message subject says "Soft FIFO Controller" but the A3P family has > hardware FIFO : use them, don't bother with FIFO softcore (particularly > if you're not a specialist). It's faster, safer, and smaller. > Hi whygee, Initially this is what I was thinking, but I need a few FIFOs of an odd depth (not a power of 2) and the docs gave me the impression that the FULL flag will only be activated when an entire block is full. The other night I went ahead and tried simulating the hard FIFO with a depth of 10 (not my final required depth, just an arbitrary short and non-power-of-two value), the FULL flag did not go active until 512 writes had been executed. So based on that I figured it would be easier to leave everything to the Soft FIFO controller.. I'm not going to be tight on logic resources or timing, so I don't mind using a little extra on this. The simulation of the soft FIFO brought to my attention the fact that data will not be ready on the read port until two read clocks after the read enable is asserted, which is a bit of an inconvenience, so I think I will also try using the ALMOST FULL flag two cycles early to keep the FIFO going such that I can start reading out exactly as the FIFO fills up. In that case I suppose it may also be feasible to use the ALMOST FULL flag with the hard FIFO, though. At any rate, thanks for the advice! SteveArticle: 140135
d <=fn(c,din); if(rising_edge(clk) and second_cycle = '1') then c <= d; end if; if(rising_edge(clk) and second_cycle = '0') then -- din <= din; -- self held assignment programmer knowledge end if; is there anyway to specify that the combinational fn is two cycle? the register retiming options seem to remove the carry bit, and replace it with and implicit signal. Maybe the retiming does an eval of the state machine order and realizes?? It seems that because the synthesis tool does not realize the data in port remains constant, because the address bus remains constant, it freaks a little and routes accordingly. As a latch is totally un- necessary. I don't have timing quest money or time. Fair enough if din did change then it would be a mistake, but it don't. cheers jackoArticle: 140136
On Apr 29, 10:58=A0am, Tommy Thorn <tommy.th...@gmail.com> wrote: > On Apr 17, 7:45=A0am, "Antti.Luk...@googlemail.com" > > <Antti.Luk...@googlemail.com> wrote: > > your verilog is ICARUS verilog, and ALTERA verilog > > > but not fully portable verilog > > fixed 4 different issues that prevent your code to pass synthesis with > > XST but still some problems to solve :( > > Antti was absolutely right, but I've fixed this now and I have it > support Xilinx now. My distribution has partial support (SSRAM support > missing) for the Virtex-4 based ML401. Others should be easy as well. > > Regards, > Tommy Hi great work well, I should have said not cross-vendor friendly verilog as Altera synthesis was happy and XST not, so it may be partially the problem of XST, nevertheless it is nice to know the code now passes synthesis for both a and x Antti PS I am happy as a cricket, getting from PCB fab today 27 different PCB! for a electronic constuctor-kit prototyp. yes the first set includes some modules with FPGA's too :)Article: 140137
jetmarc@hotmail.com writes: > 2) Given VHDL that works on FPGA, will there be considerable risk > associated with the ASIC conversion? Yes. RAM's, PLL's, and IO buffers will be different. Any IP you use might not be available in a compatible part (microblaze, nios, bus interfaces, etc). The gates are different so timing will be different. Mostly you will have to do production test vectors in order to test your chips. Altera and Xilinx have done this for you with your FPGA's. You need a set of new tools and learn how to use them. ASIC synthesis tools (dc), timing analyzers (primetime), ATPG etc. The tools are expensive and takes time to learn. > 3) How long can it take to have working chips? It depens... > 4) Who can do it? Do you have any recommendation? Maybe Altera Hardcopy could be a good start for you? The savings is not as great for high volumes, but the risk is lower and Altera does most of the work for you. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 140138
Hi all, I have question on representation of data bus bits I have a module called CCM (core control module) with 16-bit data bus if i want to write 32-bit data how can i write and how to represent on expected results; can i represent: --Upper 16 bits--Ist cycle dsp_d(15:0) = 0x0123 --Lower 16 bits--2nd cycle dsp_d(15:0) = 0x4567 (or) reading 32-bits of data in two cycle burst of 16-bit words. dsp_d(15:0) = 0xDDDD. Please give me some exposure on this. because we have like CCM's three kinds one is having READ and WRITE data buses same widths but others are having different so make balance conventions i required suggestions. Sreeni.JArticle: 140139
jetmarc@hotmail.com wrote: > I'm considering the option of converting an FPGA design into ASIC, but > have no experience with that. My questions are: If you don't have any experience in ASIC design, then hire someone that has. ASIC design is quite different compared to FPGA design and there are many more steps. Easiest way to do this is to hire a company that does this for living. They have the knowledge, tools, experience with ASIC vendors etc. They can also give some estimates if the project is worthwhile. But even then you will need someone with ASIC experience, to speak the same language with the company. > 1) Cost savings, how do ASICs compare to FPGAs? There is no answer to this. This depends on the selected process, design size, package, volume, your relationship with the vendor etc. For example high IO count packages are expensive, and in some cases FPGA might be more cost efficient due to their volume if the design is not that big. On the other hand if you have very big FPGA the price of silicon area defines the price mostly, and then the savings can be big. You have to also divide the NRE+work to each chip, and that also depends on the process selection. Habe you looked into eASIC nextreme chips? They should be cheaper than FPGA and have a low NRE. > 2) Given VHDL that works on FPGA, will there be considerable risk > associated with the ASIC conversion? Yes. There are many caveats at code level. Also IO-structures, PLLs, clocking, IP-blocks and many other things are different. As an example initial values in signals work in fpgas, but do not work in ASICs. ASICs need explicit resets if some initial values are needed. Also some code structures might be bad for testability (ATPG). > 3) How long can it take to have working chips? This depends on the process and design complexity. I would say 9-18 months. You can get even lower if you use some experienced company for the conversion, the design is not too complex and the process is not leading edge. > 4) Who can do it? Do you have any recommendation? Just google for companies, one that comes to mind is esilicon, but there are others. Those companies also look into the business case and if they are interested in it. If you are in a small company the ASIC fab might not be interested in the business (too low volume vs. risk etc.) --KimArticle: 140140
On 29 Apr., 17:22, David Fejes <fej...@gmail.com> wrote: > Hello there, > > I want use a GCLK pin in a Xilinx CPLD as a regular input. > Unfortunatelly the fitter designates it to global clock. > How can I tell to the fitter that this input is a regular data signal? > I've tried the BUFG constraint in the UCF file, but didn't success. > > GCLKs can operate as regular output so I think they have to able to > work as regular input too.. Am I wrong? > > Many thanks in advance > > David Fejes Hi David, Which CPLD family? Which type, which pin? (sometimes there are more than one clock Input) regards Eilert WhichArticle: 140141
"Benjamin Couillard" <benjamin.couillard@gmail.com> wrote in message news:d4b34802-28fe-48dd-a4e8-28d812bb0f50@r13g2000vbr.googlegroups.com... > Hi, I've downloaded ISE 10.1 and I'm now trying to install it on my > PC. Every time I click on setup.exe, the program crashes and I get an > error message from Windows. > > I tried running it as an administrator, I tried running it with > "windows xp compatability mode" and it still doesn't work. What's > weird is that I've installed ISE 9.2 without any problems. It seems > that Vista home is not officially supported by Xilinx since they only > mention Vista Business on ISE 10.1 webpage. However, it should stil > work with Vista Home. I recall very **vaguely** some issues running the downloaded installers on XP, so assume for now and pursue it as though it were not an OS issue. It was long ago, and I don't recall the details. They all worked with some trick. Something like right click/Install; or unzip and then run the installer; or move the download to a different directory, maybe one without spaces in the path... As I said, I don't recall, but all the 10.1 product installers had the same problem on my system, and all installed fine with the same trick.Article: 140142
I was wondering if there is any simulator that could emulate my Verilog code meant for the FPGA. The problem is that my code cant be implemented on the FPGA boards available in my university lab. Hence have to look out for a simulator. Any help appreciated deeply! Thanks!Article: 140143
Hi, Just to follow up on this, since the topic of hard FIFO vs. soft came up here, I went ahead and tried simulating and making adjustments to both to see what the kinks and workarounds would be for each one, keeping in mind mind that I want to chain a few FIFOs together and have the data continuously flow through the entire chain after resetting and starting to clock data through. I thought maybe this could be of use if somebody else wants to find some info on the Actel FIFOs. Also, opinions might be appreciated on which to use given the Here's a summary of what I've found. Hard FIFO: The FULL flag apparently only works on power of two depths. Using a depth of 10, I didn't get a FULL flag until 512 writes. This can be worked around by using the AFULL flag set to 10, but then there is not an extra AFULL flag available to address the next issue that I'm going to mention. Soft FIFO Controller: As I mentioned in the last post, the data is ready 2 clocks after RE is asserted (does this mean the read out is "pipelined?". I originally wanted to use the FIFO's own FULL flag to assert RE, but this can be worked around by using the AFULL flag set to go off 2 elements before FULL (AFULL=8 in the case of a FIFO depth of 10), then use the FULL flag as a write enable for the destination of the readout. Hard FIFO: Data comes out 1 clock after RE, or 2 clocks if the output pipeline is used. Since we can't use both FULL and AFULL together as with the soft controller, the workaround to avoid losing a clock cycle with every stage in the chain of multiple FIFOs is to set AFULL to assert one or two clocks earlier than the FIFO depth, and feed it into a flip-flop (assuming no pipeline on the FIFO macro) to delay write-enable assertion to the next stage. Taking these things into account, , in simulation I have achieved my desired results with either the hard or soft FIFO. I suppose it will be good to check the post-synth simulations for both designs as well, and then it's on to deciding which of these to use for the real hardware. At the end of the day it'll probably be good to actually flash both designs onto the chip and test them, as well. This is straying quite a bit from the original topic of just getting the simulation to work, though. Once again thanks for the responses!Article: 140144
jleslie48 <jon@jonathanleslie.com> writes: > I ~should~ just be sending in the external signal to the input pin, > but my instinct tells me I'm gonna smoke something when I solder two > wires with 3.3 volts together... > The smoke comes out when too much current flows. Current only flows when there's a voltage *difference* between two points. The size of that current depends on the resistance between two points (Ohms law - Current = Voltage difference / Resistance). In your case, (to a first and probably 2nd approximation) the voltage difference is zero (you have 3.3V at the end of each wire), so no current flows, so no smoke... Now if the voltage at the "far" end were zero volts (because you had enabled the PULLDOWN option in the UCF file), there'd still be no smoke as the pulldown is of the order of 1000s of ohms, so the current flowing will be of the order of milliamps, still no smoke. [As an aside - if the "far end" pin were actually defined as an *output*, so actively *driving* 0V onto the wire (in the same way as your other output is driving 3.3V onto the wire) and you conencted them together, a not insignificant current would flow (up to 10s of milliamps), but in my experience, still no smoke. The chip can feel warm if you do this lots though :)] Does that help any? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 140145
1stderivative@gmail.com writes: > I was wondering if there is any simulator that could emulate my > Verilog code meant for the FPGA. The problem is that my code cant be > implemented on the FPGA boards available in my university lab. Hence > have to look out for a simulator. > Are you really asking if there are Verilog simulators? Does your university not have access to one of the severeal available options? Google will tell you what they are! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 140146
> >1) Cost savings, how do ASICs compare to FPGAs? > > ASICs are very high NRE and low incremental unit cost so to get any > cost saving at all you have to get a large number of chips made. As a > first approximation you can assume that you'll have to spend $1M to > get an ASIC made and say $1 per chip after that. While the NRE may be this high for <90nm processes, for older processes it can be a lot less (i.e. less than $100k). So what it will cost you will depend upon the requirements of your design (i.e. power consumption, operating frequency, voltage, etc.). >4) Who can do it? Do you have any recommendation? I work for a company who does exactly this job. If you want to discuss it in more depth, please feel free to drop me an e-mail. Cheers, JonArticle: 140147
On Apr 30, 1:59=A0pm, Martin Thompson <martin.j.thomp...@trw.com> wrote: > 1stderivat...@gmail.com writes: > > I was wondering if there is any simulator that could emulate my > > Verilog code meant for the FPGA. The problem is that my code cant be > > implemented on the FPGA boards available in my university lab. Hence > > have to look out for a simulator. > > Are you really asking if there are Verilog simulators? =A0Does your > university not have access to one of the severeal available options? > Google will tell you what they are! > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html I'm aware of the Simulators around... we use ModelSim. I would like to know if the face recognition code could be implemented on such simulators after proper interfacing. Is it possible for ModelSim to simulate the code? Thanks!Article: 140148
On Apr 30, 1:59=A0pm, Martin Thompson <martin.j.thomp...@trw.com> wrote: > 1stderivat...@gmail.com writes: > > I was wondering if there is any simulator that could emulate my > > Verilog code meant for the FPGA. The problem is that my code cant be > > implemented on the FPGA boards available in my university lab. Hence > > have to look out for a simulator. > > Are you really asking if there are Verilog simulators? =A0Does your > university not have access to one of the severeal available options? > Google will tell you what they are! > > Cheers, > Martin > > -- > martin.j.thomp...@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w= ww.conekt.net/electronics.html I'm aware of the Simulators around... we use ModelSim. I would like to know if the face recognition code could be implemented on such simulators after proper interfacing. Is it possible for ModelSim to simulate the code? Thanks!Article: 140149
On Apr 29, 8:40=A0am, meti...@gmx.de wrote: > Hi, > > first off, this subject keeps bugging me since i work with (Xilinx) > FPGAs. > > So,..there is an OFFSET OUT constraint to specify for Outputs. > > So far i understand from timing reports, PAR evaluates OFFSET OUT as a > maximum value. > > But...design i'm currently doing restricts me also for suppliying a > minimum clock-to-output > > constraint. Seems like this is currently not possible with xilinx > tools...am i right? > > I need to specify an maximum and minimum value for OFFSET OUT. > > All i can do is...after PAR finishes...do timing anaylsis with "Report > fastest paths/verbose hold paths" check box selected. > > This gives me the setup/hold paths for all timing paths avaliable in > the design, right? > So at least i can check what my current min. clk-to-out delay is. > > And, i found also something like Speedgrade -0 for checking best case > timing results. > > (referring tohttp://www.xilinx.com/support/answers/4506.htm) > > Do someone know the difference. > > Thanks I looked in the Xilinx Timing Constraints User's Guide http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf. It seems there is an OFFSET OUT AFTER constraint that checks for maximum clock-to-out (setup) and then there is an OFFSET OUT BEFORE constraint that checks for hold. Pete
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