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We are Ricoh Innovations in Menlo Park, CA are looking for some masters/phd students (in the U.S) in the area of digital logic design (for FPGA) with experience in digital signal and image processing: http://rii.ricoh.com/about/jobs/dor-int1.php DirkArticle: 139551
On Thu, 2 Apr 2009 07:54:21 -0700 (PDT), John Adair <g1@enterpoint.co.uk> wrote: >With SSO edge rate, current and number of I/O switching at exactly the >same time are what is important. It's the inpulse, or step, in current >that creates a ground or even a power bounce as current tries to flow >through parasitic inductance in lead frames and bond wires etc.. >Very simple techniques like dithering I/O switch say by offsetting by >half a clock (opposite edge clocking) can reduce a potential problem >by spreading the current impulse. Or even simpler like SLEW=SLOW and 2mA drive current (which can be applied in the UCF without touching the RTL code) since for most applications, at low frequency, edge speeds can be made relatively unimpertant. - BrianArticle: 139552
jleslie48 wrote: > so I have a system that has a 25mhz clock built on it, and I'd like to > have either a 20mhz clock or a 100mhz clock, > > Now I'm thinking of options, > > 1) make a 20mhz clock out of the 25mhz. - the obvious idea is to count > up to 5 and force a state change on one of the counts, but this will > give me a 80/20 duty cycle. If i'm only clocking on the rising edge, is > this a problem? Depends entirely on your application. And BTW, I'd suggest if you use this method, you generate a 20MHz clock _enable_, rather than a clock... > 2) how would I make a 20mhz clock out of the 25mhz with a closer to > 50/50 duty cycle? DCM > 3) I keep hearing about clock mulitpliers, how is that done in an fpga? > I could on paper multiply the 25mhz by 4 and have a 100mhz clock, that > would be good... The Xilinx DCM will _surely_ be able to produce a 20MHz clock from the 25MHz clock (I'm an Altera guy). That's exactly what they're for! You shouldn't need to be worrying about feeding in different clocks... > 4) given I have input pins on my fpga, could I make up a daughter card, > that has a 100mhz oscillator on it, send that signal in on one of the > pins and use that as the clock and ignore the 25mhz clock? You can only use certain pins for clocks, you can't just feed it in on any old pin and use it as a (global) clock. Use a DCM!!! It will do everything you need. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 139553
On Thu, 2 Apr 2009 16:23:20 -0700 (PDT) jleslie48 <jon@jonathanleslie.com> wrote: > On Apr 2, 7:05 pm, jprovide...@yahoo.com wrote: > > On Apr 2, 3:46 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > > > > > Ok, > > > > > so I have a system that has a 25mhz clock built on it, and I'd > > > like to have either a 20mhz clock or a 100mhz clock, > > > > > Now I'm thinking of options, > > > > > 1) make a 20mhz clock out of the 25mhz. > > > - the obvious idea is to count up to 5 and force a state change > > > on one of the counts, but this will give me a 80/20 duty cycle. > > > If i'm only clocking on the rising edge, is this a problem? > > > > > 2) how would I make a 20mhz clock out of the 25mhz with a closer > > > to 50/50 duty cycle? > > > > > 3) I keep hearing about clock mulitpliers, how is that done in an > > > fpga? I could on paper multiply the 25mhz by 4 and have a 100mhz > > > clock, that would be good... > > > > > 4) given I have input pins on my fpga, could I make up a daughter > > > card, that has a 100mhz oscillator on it, send that signal in on > > > one of the pins and use that as the clock and ignore the 25mhz > > > clock? > > > > > Tia, > > > > > Jonathan > > > > If you're using a Xilinx FPGA, you can use a DCM block to multiply > > the 25MHz up > > to 100 MHz. The 100MHz can easily be divided down to 20MHz. > > > > John Providenza > > Ok, yeah, that is what I'm reading up on. > > there is no good way to divide 25mhz to get 20mhz, that was > incorrect. > I'm still interested in an external oscillator coming in on a pin > though. > > I'm seeing some write-ups on dll (delay latch logic?) but I'm > unfamiliar with > DCM (and dll) for that matter. Here is what xilinx has as code: > > [snip] > so what, I just make up an instance on this routine, send in my 25mhz > clock, and out comes > a 100mhz clock? And then my program references this 100mhz clock > instead? > > That's all there is to it? > Pretty much, although some of that instance didn't look quite right. Most people use CoreGen to put together a nice clean wrapper over top of the DCM instance (it might be the only thing CoreGen's good for). Check out the chapter on the DCMs in UG331, the Spartan3 User's Guide. It's got a lot of information that will be of use to you. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 139554
On Apr 2, 9:20 pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Thu, 2 Apr 2009 16:23:20 -0700 (PDT) > > > > jleslie48 <j...@jonathanleslie.com> wrote: > > On Apr 2, 7:05 pm, jprovide...@yahoo.com wrote: > > > On Apr 2, 3:46 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > Ok, > > > > > so I have a system that has a 25mhz clock built on it, and I'd > > > > like to have either a 20mhz clock or a 100mhz clock, > > > > > Now I'm thinking of options, > > > > > 1) make a 20mhz clock out of the 25mhz. > > > > - the obvious idea is to count up to 5 and force a state change > > > > on one of the counts, but this will give me a 80/20 duty cycle. > > > > If i'm only clocking on the rising edge, is this a problem? > > > > > 2) how would I make a 20mhz clock out of the 25mhz with a closer > > > > to 50/50 duty cycle? > > > > > 3) I keep hearing about clock mulitpliers, how is that done in an > > > > fpga? I could on paper multiply the 25mhz by 4 and have a 100mhz > > > > clock, that would be good... > > > > > 4) given I have input pins on my fpga, could I make up a daughter > > > > card, that has a 100mhz oscillator on it, send that signal in on > > > > one of the pins and use that as the clock and ignore the 25mhz > > > > clock? > > > > > Tia, > > > > > Jonathan > > > > If you're using a Xilinx FPGA, you can use a DCM block to multiply > > > the 25MHz up > > > to 100 MHz. The 100MHz can easily be divided down to 20MHz. > > > > John Providenza > > > Ok, yeah, that is what I'm reading up on. > > > there is no good way to divide 25mhz to get 20mhz, that was > > incorrect. > > I'm still interested in an external oscillator coming in on a pin > > though. > > > I'm seeing some write-ups on dll (delay latch logic?) but I'm > > unfamiliar with > > DCM (and dll) for that matter. Here is what xilinx has as code: > > > [snip] > > so what, I just make up an instance on this routine, send in my 25mhz > > clock, and out comes > > a 100mhz clock? And then my program references this 100mhz clock > > instead? > > > That's all there is to it? > > Pretty much, although some of that instance didn't look quite right. > Most people use CoreGen to put together a nice clean wrapper over top > of the DCM instance (it might be the only thing CoreGen's good for). > > Check out the chapter on the DCMs in UG331, the Spartan3 User's Guide. > It's got a lot of information that will be of use to you. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order hey thanks guys. ok so I have some reading to do. ug331, and that will explain what a DCM is. It seems all agree that is the way to the solution. I forgot to mention I am on a Spartan3 chip anyway, so much the better for the reading. Sincerely, Jonathan LeslieArticle: 139555
On Apr 2, 8:53 pm, Mark McDougall <ma...@vl.com.au> wrote: > jleslie48 wrote: > > so I have a system that has a 25mhz clock built on it, and I'd like to > > have either a 20mhz clock or a 100mhz clock, > > > Now I'm thinking of options, > > > 1) make a 20mhz clock out of the 25mhz. - the obvious idea is to count > > up to 5 and force a state change on one of the counts, but this will > > give me a 80/20 duty cycle. If i'm only clocking on the rising edge, is > > this a problem? > > Depends entirely on your application. And BTW, I'd suggest if you use this > method, you generate a 20MHz clock _enable_, rather than a clock... That is a very good point. If you need multiple clock circuits internally, you might be better off using a high rate clock with a common factor and internally using clock enables. If you need to move data around using these clocks they can be independent until you need to move that data between one clock domain and another. > > 2) how would I make a 20mhz clock out of the 25mhz with a closer to > > 50/50 duty cycle? > > DCM The method used for generating one frequency from another that doesn't just involve dividing down a rate typically is a PLL. I know that most FPGA types include a PLL. Depending on the chip family, Xilinx uses a DLL which is very similar. The way a PLL works is to run a VCO (voltage controlled oscillator) as part of a feedback loop. The output rate of the VCO is divided down to a reference frequency and compared to the input divided down to the same reference frequency. The phase comparitor outputs a voltage to control the VCO. When the frequencies are not matched, the phase comparator sees a difference in phase and adjusts the output voltage. So the output frequency changes until the two reference frequencies match. A low pass filter between the phase comparator and the VCO helps to smooth the adjustments in frequency. In this case, the 25 MHz can be used directly as the input reference frequency. The output is divided by four so that it run at 100 MHz when the divided clock matches the 25 MHz reference. > > 3) I keep hearing about clock mulitpliers, how is that done in an fpga? > > I could on paper multiply the 25mhz by 4 and have a 100mhz clock, that > > would be good... > > The Xilinx DCM will _surely_ be able to produce a 20MHz clock from the > 25MHz clock (I'm an Altera guy). That's exactly what they're for! You > shouldn't need to be worrying about feeding in different clocks... > > > 4) given I have input pins on my fpga, could I make up a daughter card, > > that has a 100mhz oscillator on it, send that signal in on one of the > > pins and use that as the clock and ignore the 25mhz clock? > > You can only use certain pins for clocks, you can't just feed it in on any > old pin and use it as a (global) clock. Are you sure about that? I haven't looked at this detail on a Xilinx part in a while, but the Lattice parts allow a clock source to be from the general routing. Because of the long delay in the routing, this won't be usable to clock input data that is relative to that clock, but it can be used internally. This is one of those situations where a little knowledge is a dangerous thing. There is so much more to clocking an FPGA than just getting a clock rate. It would be best if we understood the bigger problem. That could easily save going down a more complex and difficult path when it is not needed at all. RickArticle: 139556
On Apr 2, 5:25=A0pm, aleksa <aleks...@gmail.com> wrote: > NET "CLOCK" TNM_NET =3D "CLOCK"; > TIMESPEC "TS_CLOCK" =3D PERIOD "CLOCK" 50 ns HIGH 50 %; > > OFFSET =3D IN =A015 ns VALID 20 ns BEFORE "CLOCK"; > OFFSET =3D OUT 15 ns AFTER "CLOCK"; > > I believe that this is the correct way to say: > > =A0 1. I have a 20MHz clock. > =A0 2. All inputs =A0are 15 ns SETUP and 5 ns HOLD. > =A0 3. All outputs are 15 ns MAXDELAY. > > Right? > > It works if the first two lines are > commented out, but fails otherwise, > even if I set the PERIOD to 500 ns... why? > > And why is ISE insisting on "HIGH 50 %" when > it is an oscillator clock, who cares if it > started low or high? Some FFs in my design > are using rising_edge, some falling_edge, > but any FF has 50ns from edge to edge. I've fixed the problem (not working with PERIOD) by specifing the same constraint for BOTH edges: OFFSET =3D IN 15 ns VALID 20 ns BEFORE "CLOCK" RISING; OFFSET =3D IN 15 ns VALID 20 ns BEFORE "CLOCK" FALLING; # (hey, xilinx, why do I have to specify the *same* # OFFSET IN for both rising and falling # and not just one w/o rise/fall keyword ??) # (again, only if PERIOD is used) On the OUT side, the same applies: OFFSET =3D OUT 15 ns AFTER "CLOCK" RISING; OFFSET =3D OUT 15 ns AFTER "CLOCK" FALLING; this works in my test 'project', but creates a protection fault on a real one. If I use the OUT w/o rise/fall: OFFSET =3D OUT 15 ns AFTER "CLOCK"; then it doesn't create a protection fault, but fails timing big time. So, the only thing left to do is to remove the PERIOD constraint. Then it works..Article: 139557
On Apr 2, 11:27=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > On Apr 2, 10:01=A0pm, David Fejes <fej...@gmail.com> wrote: > > > > running parallel 165mhz datapaths via XC95 doesnt sound like a good > > > idea > > > but maybe i am wrong, has happened b4 > > > There is a similar application note at the Xilinx webpage in the > > xapp944.pdf =A0It is true that the maximum frequency of the signals is > > only 27Mhz in this design and it uses CoolRunnerII instead of XC95, > > but there is a interesting sentence at the end of the document: > > > ,,All similar signals travel through the same path in the CPLD, so > > they will emerge from the other side with negligible skew, because of > > to the deterministic nature of the timing model and architecture." > > > I think it should be true at higher frequencies too, didn't? > > What load is this driving, and what time variance can you tolerate ? The time variance should be less than 1ns. Only one IC is connected to the outputs. > Within the CPLD the data paths are nominally the same, but you will > find signals further from GND pins are more variable, and the signals > will also have different thermal-delay-profiles. > It's normally best to have the device delays a fraction of our signal, > so > any variations in those delays are an even smaller fraction of your > signal. > > Why chose the XC95xxx ? There was three main reason: - high IO count with relative low cost - FBs have 54 inputs, it gives more freedoom at mapping output pins (Coolrunner II FBs have only 40) - FastConnectII provides uniform delay so inputs can be mapped freely... Can you offer a better solution? BTW, I have just examined a CoolRunnerII X-Board (a Digilent devboard) and I have measured 120ns rise time on the outputs. I don't understand, maybe I made mistake somewhere.. (the datasheet specifies 4.5ns....) DavidArticle: 139558
David Fejes <fejesd@gmail.com> writes:
>Can you offer a better solution?
If you don't need to multiplex the signals at 160MHz, what about Quickswitch?
http://www.idt.com/?catID=58731&loc=1&bHt=961
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 139559On Apr 3, 9:51=A0pm, David Fejes <fej...@gmail.com> wrote: > Can you offer a better solution? You should be able to target both Xilinx CPLD families easily and see what the timing reports say. How many pins are switched on this, and how wide are the busses. I'd expect the newer CR2 devices to have better 165MHz performance, and you may need certain packages, if a lot of lines are active. Ask XiIinx. > > BTW, I have just examined a CoolRunnerII X-Board (a Digilent devboard) > and I have measured 120ns rise time on the outputs. I don't > understand, maybe I made mistake somewhere.. (the datasheet specifies > 4.5ns....) Sounds like your measuring bandwidth is rather low. -jgArticle: 139560
On Apr 3, 6:17=A0am, -jg <Jim.Granvi...@gmail.com> wrote: > On Apr 3, 9:51=A0pm, David Fejes <fej...@gmail.com> wrote: > > > Can you offer a better solution? > > You should be able to target both Xilinx CPLD families easily and see > what the timing > reports say. > > How many pins are switched on this, and how wide are the busses. > > I'd expect the newer CR2 devices to have better 165MHz performance, > and you may need certain packages, if a lot of lines are active. > Ask XiIinx. > > > > > BTW, I have just examined a CoolRunnerII X-Board (a Digilent devboard) > > and I have measured 120ns rise time on the outputs. I don't > > understand, maybe I made mistake somewhere.. (the datasheet specifies > > 4.5ns....) > > Sounds like your measuring bandwidth is rather low. > > -jg Is the output set to open-drain?Article: 139561
On Apr 2, 10:06=A0pm, rickman <gnu...@gmail.com> wrote: > > > You can only use certain pins for clocks, you can't just feed it in on = any > > old pin and use it as a (global) clock. > > Are you sure about that? =A0I haven't looked at this detail on a Xilinx > part in a while, but the Lattice parts allow a clock source to be from > the general routing. =A0Because of the long delay in the routing, this > won't be usable to clock input data that is relative to that clock, > but it can be used internally. > > This is one of those situations where a little knowledge is a > dangerous thing. =A0There is so much more to clocking an FPGA than just > getting a clock rate. =A0It would be best if we understood the bigger > problem. =A0That could easily save going down a more complex and > difficult path when it is not needed at all. > > Rick You need to set an environment variable to allow connecting just any input pin to a DCM. If the frequency is all you care about, i.e. there is no external signal synchronous to the 25 MHz oscillator, then any pin will do, but it is "not recommended" by Xilinx. If you haven't already defined the pinout, best to use a global clock input for this. Regards, GaborArticle: 139562
knight <krsheshu@gmail.com> wrote:
>Hi all,
>
>Iam using Xilinx XST for synthesis.
>Iam using almost 20 modules in my design.
>each if i synthesize seperately iam getting a maximum frequency of
>more than 400 Mhz. But when i combine everything iam getting
>only 121Mhz.
>
>Can you tell me the reason...???
>Does this mean i cannot use a clock more than 121 Mhz in my design(iam
>using and found it working well..)
>How can i increase my timing for high frequencies..??
>Iam providing the synthesis report here.
>Can you tell me what is the Maximum frequency mentioned here..?
>
>Timing Summary:
>---------------
>Speed Grade: -1
>
> Minimum period: 8.226ns (Maximum Frequency: 121.566MHz)
> Minimum input arrival time before clock: 3.043ns
> Maximum output required time after clock: 3.281ns
> Maximum combinational path delay: 2.072ns
>
>I want to acheive minimum 400Mhz for my entire design.... Is it
>possible...? That is my target....
>Do comment...
THe solution is simple: don't look at these numbers. They are
completely bogus. What counts is the timing report after place &
route. The timing analysis tool is very usefull to analyze a design
which doesn't meet timing after place and route.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 139563On Apr 1, 8:55=A0pm, rickman <gnu...@gmail.com> wrote: > On Apr 1, 7:09=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I am looking at this, because sometimes other logic seems to be > > combined with the adder LUT and I want to understand what they are > > doing. > > > Rick > > I added KEEP attributes to force the logic to be distributed the way I > intended and added a register to the output of the adder. =A0The > register seems to have been moved to the other side of the adder so > that the inputs to the adder are being registered. =A0I guess the tool > is free to do that, but when I added a timing constraint to the output > of the adder, rather than move the register to where I asked for it, > the tool just reports a timing violation! > > Do I have to add special attributes to get the register where I want > it so that it meets timing constraints? > > Rick I guess there are not a lot of Lattice users here. I have been trying to see if my coding can influence the synthesis and I am finding that it does influence it greatly, but not in a good way. The circuit I am working with is in essence a 4 input mux with an enable added to the output of a 2 input mux with an enable. No matter how I coded it, the 4 input mux with enable would be done less efficiently than was possible. This is not a speed/density tradeoff since the same circuit is optimal for both. It would split off the logic in odd ways so that two LUTs had to be combined by a third with a control signal normally. Ideally it would just treat the logic as a 4 input mux which can be done with 2 LUTs per bit and use the fourth input to each LUT as an enable. That would only use two LUTs per bit and give the shortest delay possible. Is there a way to force the use of the LUT5 in this situation other than instantiation? RickArticle: 139564
On Apr 1, 2:08=A0am, Sharan <sharan.basa...@gmail.com> wrote: > Hi, > > In few of the protocols (e.g. USB), there is an 8b10b and then there > is line encoding. Since one of the purpose of 8b10b is to create > enough 1&0 transitions, why is there a separate line encoding after > 8b10b? Am I missing something > > Regards Hi, 8b10 is a coding method at the physical layer and it is used to maintain that the differences of numbers of '0' and '1' in a transaction are not beyond 2. Its physical meaning is to make sure that transmission line has no charge accumulated. For example, a code "11111" is transferred to other end of transmission line and several '1' would accumulate some charge, then a successive '0' will have to discharge it to ground. The more charges accumulated in a transmission line, the more discharge time and more time based on formulae: T =3D RC in seconds, and lower frequency required. To increase transmission rate, a coding is needed to maintain balance between the '0' and '1'. A higher level or even several levels of coding are needed to do their own purposes. For example, correction code is to be used to keep error rate as low as possible by adding more data bits used to correct errors. 8b10b coding become popular in recent year and it has two reasons: a. higher frequency of transmission line is much needed. b. Its patent by IBM expired in 2002. You may see "Byte oriented DC balanced (0,4) 8B/10B partitioned block transmission code" patented by IBM, 4486739, filed on Jun 30, 1982, and after reading the paper you may know why it was introduced. It is a real invention which was invented before new technology needs it. I think PCI-Express may be the first standard to use it near the expiration data of the patent and IBM may not receive any royalty from the invention. WengArticle: 139565
On Apr 3, 1:18=A0pm, rickman <gnu...@gmail.com> wrote: > On Apr 1, 8:55=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Apr 1, 7:09=A0pm, rickman <gnu...@gmail.com> wrote: > > > > I am looking at this, because sometimes other logic seems to be > > > combined with the adder LUT and I want to understand what they are > > > doing. > > > > Rick > > > I added KEEP attributes to force the logic to be distributed the way I > > intended and added a register to the output of the adder. =A0The > > register seems to have been moved to the other side of the adder so > > that the inputs to the adder are being registered. =A0I guess the tool > > is free to do that, but when I added a timing constraint to the output > > of the adder, rather than move the register to where I asked for it, > > the tool just reports a timing violation! > > > Do I have to add special attributes to get the register where I want > > it so that it meets timing constraints? > > > Rick > > I guess there are not a lot of Lattice users here. > Well, it's an acquired taste... :-) > I have been trying to see if my coding can influence the synthesis and > I am finding that it does influence it greatly, but not in a good > way. =A0The circuit I am working with is in essence a 4 input mux with > an enable added to the output of a 2 input mux with an enable. > > No matter how I coded it, the 4 input mux with enable would be done > less efficiently than was possible. =A0This is not a speed/density > tradeoff since the same circuit is optimal for both. =A0It would split > off the logic in odd ways so that two LUTs had to be combined by a > third with a control signal normally. =A0Ideally it would just treat the > logic as a 4 input mux which can be done with 2 LUTs per bit and use > the fourth input to each LUT as an enable. =A0That would only use two > LUTs per bit and give the shortest delay possible. > > Is there a way to force the use of the LUT5 in this situation other > than instantiation? > > Rick I have to admit that although I use Lattice parts, I try to stay out of the FPGA Editor (er... I mean EPIC) unless I'm making sure my registers found their way into the MGIOL or that my clock really uses global routing. So not much to help you with fabric related optimization. What version of ispLever are you using? If you are trying to optimize muxes, is instantiation really so bad? Have you tried instantiation to make sure what you want to do is really possible and there isn't some other gotcha that keeps synthesis from coming up with your preferred solution? Regards, GaborArticle: 139566
I'm starting to play with the Xilinx Mig for a DDR2 design. I have the basic logic generated by Mig simulating and the DDR2 model seems to be twitching happily. Of course, it takes a while to simulate through the DDR2 setup and calibration. Does anyone have a bus function model of the user interface to the Mig DDR2 controller, ie, the app_* interface? I don't need/want to simulate the DDR2 interface for a lot of my tests and I'd like to have a simple memory model using the app* interface for a lot of my testing to speed up the development. Thanks in advance. John ProvidenzaArticle: 139567
On Apr 3, 4:02=A0pm, gabor <ga...@alacron.com> wrote: > On Apr 3, 1:18=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Apr 1, 8:55=A0pm, rickman <gnu...@gmail.com> wrote: > > > > On Apr 1, 7:09=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I am looking at this, because sometimes other logic seems to be > > > > combined with the adder LUT and I want to understand what they are > > > > doing. > > > > > Rick > > > > I added KEEP attributes to force the logic to be distributed the way = I > > > intended and added a register to the output of the adder. =A0The > > > register seems to have been moved to the other side of the adder so > > > that the inputs to the adder are being registered. =A0I guess the too= l > > > is free to do that, but when I added a timing constraint to the outpu= t > > > of the adder, rather than move the register to where I asked for it, > > > the tool just reports a timing violation! > > > > Do I have to add special attributes to get the register where I want > > > it so that it meets timing constraints? > > > > Rick > > > I guess there are not a lot of Lattice users here. > > Well, it's an acquired taste... :-) > > > > > I have been trying to see if my coding can influence the synthesis and > > I am finding that it does influence it greatly, but not in a good > > way. =A0The circuit I am working with is in essence a 4 input mux with > > an enable added to the output of a 2 input mux with an enable. > > > No matter how I coded it, the 4 input mux with enable would be done > > less efficiently than was possible. =A0This is not a speed/density > > tradeoff since the same circuit is optimal for both. =A0It would split > > off the logic in odd ways so that two LUTs had to be combined by a > > third with a control signal normally. =A0Ideally it would just treat th= e > > logic as a 4 input mux which can be done with 2 LUTs per bit and use > > the fourth input to each LUT as an enable. =A0That would only use two > > LUTs per bit and give the shortest delay possible. > > > Is there a way to force the use of the LUT5 in this situation other > > than instantiation? > > > Rick > > I have to admit that although I use Lattice parts, I try to stay > out of the FPGA Editor (er... I mean EPIC) unless I'm making sure > my registers found their way into the MGIOL or that my clock > really uses global routing. =A0So not much to help you with fabric > related optimization. =A0What version of ispLever are you using? > > If you are trying to optimize muxes, is instantiation really > so bad? > > Have you tried instantiation to make sure what you want to do > is really possible and there isn't some other gotcha that > keeps synthesis from coming up with your preferred solution? I don't want to use instantiation because I don't want this to be dedicated to one logic vendor. I am using ispLever 7.1 which is one version back. I have the 7.2 discs, but I haven't upgraded yet. The synthesis tool is Syniplify Pro. Since this architecture is very similar to the Xilinx stuff, I'm surprised that it isn't better at getting a more optimal solution. It really surprises me that it just can't seem to figure out how to do it efficiently when it is so obvious looking at the code. Yes, I am sure there are no hardware limitations that prevent this. It is just a matter of using the inputs to the LUTs rather than trying to reorganize the logic with suboptimal connections of the hardware. I had to add "KEEP" statements to prevent it from trying to shove logic into the adder. When it does these sorts of "optimizations", it always seems to use more logic and have a slower path. I've actually spent a fair amount of time optimizing the design to provide fast paths with minimal logic use. Now it is just a matter of finding code that will infer the right implementation. Maybe I'll try the Xilinx tools to see if they do a better job. RickArticle: 139568
Hi all, For some reason it is not possible to use RLOC_RANGE with AREA_GROUP. Is there another method of creating a relatively placed AREA_GROUP without having to create a fully blown RPM? I know there is a COMPRESSION constraint which can be attached to the AREA_GROUP, but I haven't been successful trying to use it in the past. Thanks, /MikhailArticle: 139569
> On Apr 3, 4:02 pm, gabor <ga...@alacron.com> wrote:
>> Have you tried instantiation to make sure what you want to do
>> is really possible and there isn't some other gotcha that
>> keeps synthesis from coming up with your preferred solution?
I think this is quite likely.
Either there is some non-obvious kludge
in the epic architecture,
or synthesis missed an optimization.
Unless I were down to my last gate,
I wouldn't spend time worrying about
which one it is.
-- Mike Treseler
Article: 139570Hi, There were a few posts relevant to FPGA die area from archives, but non of them mentioned about the die are of XC3S700A. I was pointed to semiconductor insight report on the device by one of the posts, but the information was not readily accessible. I would be very grateful if the information could be shared if you have. Many thanks. JackArticle: 139571
Hi, I wanted to use chipscope to verify my design (on Xilinx Virtex4 using ISE 10.1 and XST), but something strange happens which I don't have any idea about that. I generated the ICON and ILA cores by core generator and then instantiated them and connected some signals to the ILA core. Everything seemed fine until I wanted to download the bitsream. The bitstream cannot be downloaded. When I attempt to download it, it waits for a few seconds and then an error message appears ( I guess the Done signal is not asserted). First, is it possible for the tools to generate a faulty bitstream? Second, how come the chipscope cores affect the design in this way? (If I simply remove the debug cores, things will work perfect again) Later, I looked at the DRC file generated by bitgen. There are are a number of warnings in the DRC file. The warnings are mainly about unconnected signals. The time I'm not using chipscope there are 48 warnings and when I'm using it there are 191. The thing surprised me was that these additional warnings MUST always exist regardless of using debug cores. Because they refer to some unconnected output pins of BRAMs which is always the same in my design. In fact, I'm using dual port BRAMs (18-bit wide) for which output of port a is fully connected while only 9 LSB bits of output b is used.Article: 139572
> knight <krsheshu@gmail.com> wrote: > >> Hi all, >> >> Iam using Xilinx XST for synthesis. >> Iam using almost 20 modules in my design. >> each if i synthesize seperately iam getting a maximum frequency of >> more than 400 Mhz. But when i combine everything iam getting >> only 121Mhz. >> Can you tell me the reason...??? >> Does this mean i cannot use a clock more than 121 Mhz in my >> design(iam >> using and found it working well..) >> How can i increase my timing for high frequencies..?? >> Iam providing the synthesis report here. >> Can you tell me what is the Maximum frequency mentioned here..? >> Timing Summary: >> --------------- >> Speed Grade: -1 >> Minimum period: 8.226ns (Maximum Frequency: 121.566MHz) Minimum input >> arrival time before clock: 3.043ns Maximum output required time after >> clock: 3.281ns Maximum combinational path delay: 2.072ns >> >> I want to acheive minimum 400Mhz for my entire design.... Is it >> possible...? That is my target.... >> Do comment... > THe solution is simple: don't look at these numbers. They are > completely bogus. What counts is the timing report after place & > route. The timing analysis tool is very usefull to analyze a design > which doesn't meet timing after place and route. > If you use physical synthesis the post-synthesis timing numbers should be within 10%, but as Nico said, don't use these numbers. To get really accurate number you can't even rely on post-PAR timing numbers. You must run serveral multi-pass PAR runs to determine the maximum frequency for each design configuration. ---Matthew HicksArticle: 139573
Sounds like you've messed up the JTAG connection... Are you using ISE GUI? If you are using GUI there is no need to generate and connect ICON and ILA cores manually. Instead add a Chipscope definition and connection file as a new source using the new source wizard. Simply right click on the top of your project tree and choose new source, then choose the Chipscope. It will guide you through the whole thing. /Mikhail "Ehsan" <ehsan.hosseini@gmail.com> wrote in message news:c16aab71-0e15-4828-9583-4be7c037dbb3@v1g2000prd.googlegroups.com... > Hi, > > I wanted to use chipscope to verify my design (on Xilinx Virtex4 using > ISE 10.1 and XST), but something strange happens which I don't have > any idea about that. I generated the ICON and ILA cores by core > generator and then instantiated them and connected some signals to the > ILA core. Everything seemed fine until I wanted to download the > bitsream. The bitstream cannot be downloaded. When I attempt to > download it, it waits for a few seconds and then an error message > appears ( I guess the Done signal is not asserted). First, is it > possible for the tools to generate a faulty bitstream? Second, how > come the chipscope cores affect the design in this way? (If I simply > remove the debug cores, things will work perfect again) > > Later, I looked at the DRC file generated by bitgen. There are are a > number of warnings in the DRC file. The warnings are mainly about > unconnected signals. The time I'm not using chipscope there are 48 > warnings and when I'm using it there are 191. The thing surprised me > was that these additional warnings MUST always exist regardless of > using debug cores. Because they refer to some unconnected output pins > of BRAMs which is always the same in my design. In fact, I'm using > dual port BRAMs (18-bit wide) for which output of port a is fully > connected while only 9 LSB bits of output b is used.Article: 139574
Hello, my question is I'm making a modulo-10 counter using a CB4CLE counter (http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0080_48.html) and some logic gates. I am making a modulo-10 counter because I need a 1 Hz clock for my design (the clock input to the counter is a 10 Hz signal). The problem is that, when I implement my design to a FPGA, my tool warns me that there may be a problem due to clock skew, because the clock is being generated after a combinational network (two levels of AND gates to detect when the counter reaches 10). My question is simple, is there any other method to build a modulo-10 counter from CB4CLE modules or I can simply ignore the warning? Thank,
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