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>
> My question is simple, is there any other method to build a modulo-10
> counter from CB4CLE modules or I can simply ignore the warning?
>
Very easy...write the code for a modulo 10 counter in VHDL or Verilog and
stop trying to use vendor specific widgets like CB4CLE that don't do what
you want them to do anyway.
...snippet of VHDL example...
signal Count: natural range 0 to 10;
...
Modulo_10_Counter : process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Count <= 0;
elsif(Clock_Enable = '1') then
if (Count = 9) then
Count <= 0;
else
Count <= Count + 1;
end if;
end if;
end process Modulo_10_Counter;
Kevin Jennings
Article: 139576> my tool warns me that > there may be a problem due to clock skew, because the clock is being > generated after a combinational network (two levels of AND gates to detect > when the counter reaches 10). Forgot to address this in the earlier post. This warning indicates that you're not using a synchronous design process (because you're making gated clocks) which is almost without exception a very big mistake in FPGAs. The warning should not be ignored, because it means that your design is likely to not work reliably (like, it works when it is first turned on and then stops working later...or just the opposite). In any case, the VHDL code I posted in previously addresses this point as well...but assumes that the signal 'Clock' is not generated by any logic of any sort (i.e. it comes from an input pin that comes from a crystal or oscillator or is the output of a PLL). KJArticle: 139577
On Apr 5, 6:04=A0am, "MM" <mb...@yahoo.com> wrote: > Sounds like you've messed up the JTAG connection... Are you using ISE GUI= ? > If you are using GUI there is no need to generate and connect ICON and IL= A > cores manually. Instead add a Chipscope definition and connection file as= a > new source using the new source wizard. Simply right click on the top of > your project tree and choose new source, then choose the Chipscope. It wi= ll > guide you through the whole thing. > > /Mikhail > > "Ehsan" <ehsan.hosse...@gmail.com> wrote in message > > news:c16aab71-0e15-4828-9583-4be7c037dbb3@v1g2000prd.googlegroups.com... > > > > > Hi, > > > I wanted to use chipscope to verify my design (on Xilinx Virtex4 using > > ISE 10.1 and XST), but something strange happens which I don't have > > any idea about that. I generated the ICON and ILA cores by core > > generator and then instantiated them and connected some signals to the > > ILA core. Everything seemed fine until I wanted to download the > > bitsream. The bitstream cannot be downloaded. When I attempt to > > download it, it waits for a few seconds and then an error message > > appears ( I guess the Done signal is not asserted). First, is it > > possible for the tools to generate a faulty bitstream? Second, how > > come the chipscope cores affect the design in this way? (If I simply > > remove the debug cores, things will work perfect again) > > > Later, I looked at the DRC file generated by bitgen. There are are a > > number of warnings in the DRC file. The warnings are mainly about > > unconnected signals. The time I'm not using chipscope there are 48 > > warnings and when I'm using it there are 191. The thing surprised me > > was that these additional warnings MUST always exist regardless of > > using debug cores. Because they refer to some unconnected output pins > > of BRAMs which is always the same in my design. In fact, I'm using > > dual port BRAMs (18-bit wide) for which output of port a is fully > > connected while only 9 LSB bits of output b is used.- Hide quoted text = - > > - Show quoted text - Yes! I'm using the GUI and did the same you've just written. I've used Chipscope quite a few times and never had experienced this kind of problem.Article: 139578
Jonathan The DCM comes in almost two parts and the best part for this is the clock sythesiser part. Basically it's the CLKFX output you are looking to use. I'd suggest a multiply number of 4 and a divide number of 5 to achieve 20MHz. A good source of information is the user guide ug331.pdf. Google that and you should find it. You can also look at the libraries guide, usually found under help in ISE, for information on primatives. You can also find some VHDL and Verilog templates under the light bulb icon in ISE than may help. There is also the "Architecture Wizard" which is under ISE-Accessories can do some generation of templetes for some modes of the DCM although I don't think frequency synthesis is one covered. Most DCM modes will give near 50:50 clock except when locking and you get some real oddballs then. John Adair Enterpoint Ltd. On 2 Apr, 23:46, jleslie48 <j...@jonathanleslie.com> wrote: > Ok, > > so I have a system that has a 25mhz clock built on it, and I'd like to > have either a 20mhz clock or a 100mhz clock, > > Now I'm thinking of options, > > 1) make a 20mhz clock out of the 25mhz. > - the obvious idea is to count up to 5 and force a state change on one > of the counts, but this will give me a 80/20 duty cycle. If i'm only > clocking on the rising edge, is this a problem? > > 2) how would I make a 20mhz clock out of the 25mhz with a closer to > 50/50 duty cycle? > > 3) I keep hearing about clock mulitpliers, how is that done in an > fpga? =A0I could on paper multiply the 25mhz by 4 and have a 100mhz > clock, that would be good... > > 4) given I have input pins on my fpga, could I make up a daughter > card, that has a 100mhz oscillator on it, send that signal in on one > of the pins and use that as the clock and ignore the 25mhz clock? > > Tia, > > JonathanArticle: 139579
>Yes! I'm using the GUI and did the same you've just written. I've used >Chipscope quite a few times and never had experienced this kind of >problem. So, is it working now or not? If not try cleaning project files and rebuilding everything from scratch. /MikhailArticle: 139580
Dont forget to use proper feedback (internal or external) while using DCM (the architecture wizard will cover all that using a GUI). If your design is timing critical and a full blown product, you might want to include locked signal in your clock enables for fail safe operation. Hope this helps Mak On Apr 3, 3:46=A0am, jleslie48 <j...@jonathanleslie.com> wrote: > Ok, > > so I have a system that has a 25mhz clock built on it, and I'd like to > have either a 20mhz clock or a 100mhz clock, > > Now I'm thinking of options, > > 1) make a 20mhz clock out of the 25mhz. > - the obvious idea is to count up to 5 and force a state change on one > of the counts, but this will give me a 80/20 duty cycle. If i'm only > clocking on the rising edge, is this a problem? > > 2) how would I make a 20mhz clock out of the 25mhz with a closer to > 50/50 duty cycle? > > 3) I keep hearing about clock mulitpliers, how is that done in an > fpga? =A0I could on paper multiply the 25mhz by 4 and have a 100mhz > clock, that would be good... > > 4) given I have input pins on my fpga, could I make up a daughter > card, that has a 100mhz oscillator on it, send that signal in on one > of the pins and use that as the clock and ignore the 25mhz clock? > > Tia, > > JonathanArticle: 139581
Thanks, but I have to do it with schematics...... "KJ" <kkjennings@sbcglobal.net> wrote in message news:B3UBl.3614$im1.441@nlpi061.nbdc.sbc.com... > > >> My question is simple, is there any other method to build a modulo-10 >> counter from CB4CLE modules or I can simply ignore the warning? >> > > Very easy...write the code for a modulo 10 counter in VHDL or Verilog and > stop trying to use vendor specific widgets like CB4CLE that don't do what > you want them to do anyway. > > ...snippet of VHDL example... > > signal Count: natural range 0 to 10; > ... > Modulo_10_Counter : process(Clock) > begin > if rising_edge(Clock) then > if (Reset = '1') then > Count <= 0; > elsif(Clock_Enable = '1') then > if (Count = 9) then > Count <= 0; > else > Count <= Count + 1; > end if; > end if; > end process Modulo_10_Counter; > > Kevin Jennings >Article: 139582
On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote: >Thanks, but I have to do it with schematics..... Oh dear. Why? Basic Metalwork course, Lab 1: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ You are given a piece of steel approximately 5cm x 5cm x 5cm. Your task is to construct a steel cylinder, of diameter 3cm and length 4cm, without using a lathe. Marks will be deducted for any evidence that you borrowed your friend's CNC milling machine. Extra credit is available for completing the task using tools made only from elk antlers. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 139583
Jonathan Bromley wrote: > > Basic Metalwork course, Lab 1: > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > You are given a piece of steel approximately > 5cm x 5cm x 5cm. Your task is to construct > a steel cylinder, of diameter 3cm and length > 4cm, without using a lathe. Marks will be > deducted for any evidence that you borrowed > your friend's CNC milling machine. Extra > credit is available for completing the task > using tools made only from elk antlers. > :-) So true. But just imagine, you're lost in a snow storm and a cylinder of your car is broken. Then you won't have any CNC machine and you'd be sooo glad to not have cheated with a CNC machine during your metalwork course. :-) :-)Article: 139584
rickman wrote: > Are you sure about that? I haven't looked at this detail on a Xilinx > part in a while, but the Lattice parts allow a clock source to be from > the general routing. Because of the long delay in the routing, this > won't be usable to clock input data that is relative to that clock, > but it can be used internally. Altera Cyclone devices have a limited number of pins connected to the global clock network. Admittedly, I'm not sure about Xilinx devices. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 139585
On Apr 6, 12:23=A0am, "MM" <mb...@yahoo.com> wrote: > >Yes! I'm using the GUI and did the same you've just written. I've used > >Chipscope quite a few times and never had experienced this kind of > >problem. > > So, is it working now or not? If not try cleaning project files and > rebuilding everything from scratch. > > /Mikhail Nope, It's not working at all. And I cleaned everything a couple of times, but notihng changed.Article: 139586
You said the following in the original post: >I generated the ICON and ILA cores by core >generator and then instantiated them and connected some signals to the >ILA core. From this it doesn't sound as you had used the wizard? Had you or had you not? Also, does your Chipscope version match the ISE version? /MikhailArticle: 139587
On Apr 6, 11:56=A0am, "MM" <mb...@yahoo.com> wrote: > You said the following in the original post: > > >I generated the ICON and ILA cores by core > >generator and then instantiated them and connected some signals to the > >ILA core. > > From this it doesn't sound as you had used the wizard? Had you or had you > not? > > Also, does your Chipscope version match the ISE version? > > /Mikhail I guess you are referring to ISE versions lower than 10.1. In 10.1, you need to generate Chipscope cores like any other ip cores via the coregen which you can run it either within the Project Navigator or standalone. There is no more Chipscope GUI for generating debug cores. The Chipscope has the same version. It was actually installed when I installed the ISE. I don't remember if we had to pay for the license or it just came for free. EhsanArticle: 139588
On Apr 5, 2:16=A0am, "Xin Xiao" <n...@no.com> wrote: > Hello, my question is I'm making a modulo-10 counter using a CB4CLE count= er > (http://www.xilinx.com/itp/xilinx6/books/data/docs/lib/lib0080_48.html) a= nd > some logic gates. I am making a modulo-10 counter because I need a 1 Hz > clock for my design (the clock input to the counter is a 10 Hz signal). T= he > problem is that, when I implement my design to a FPGA, my tool warns me t= hat > there may be a problem due to clock skew, because the clock is being > generated after a combinational network (two levels of AND gates to detec= t > when the counter reaches 10). > > My question is simple, is there any other method to build a modulo-10 > counter from CB4CLE modules or I can simply ignore the warning? > > Thank, Hi Xin, as pointed out by KJ it is not a wise idea not to use the global clock nets for clock signals. However it's very tricky to do so with signals created by your own logic. But there is a well working solution to your problem. Build your modulo 10 counter so, that it generates a some kind of ripple signal that is active for only one 10Hz period. Use this signal as a Clock Enable for all the FFs that shall run with 1Hz. The Clock for these FFs is your 10Hz Master Clock. There are papers available, e.g. from xilinx, that discuss this method in detail. ____ Truly, schematic input is not the method of choice for designing FPGA logic, but it's not your fault that you are forced to use it. If you are a student, schematics are helpful to understand digital logic. But if that task is mixed up with understanding how FPGAs work it is like learning to walk during an olympic sprinting competition. _____ One more comment : Ok, you get this warning about possible dangers arising from clock skew. This is definitly true, and would affect your design if you would play in the X- MHz league. But for your 10Hz design you probably could have 64bit combinatorical multipliers in your datapath without being bothered by clock skew problems. Data would be stable way loooong before the next clock edge. (Actually, some logic between your FFs would be very useful in this case.) There's a very good article in the english wikipedia about Clock Skew. Read it for further understanding. Have a nice synthesis EilertArticle: 139589
On Sun, 5 Apr 2009 23:42:12 -0700 (PDT), goouse@twinmail.de wrote: >Ok, you get this warning about possible dangers arising from clock >skew. >This is definitly true, and would affect your design if you would play >in the X- MHz league. >But for your 10Hz design you probably could have 64bit combinatorical >multipliers in your datapath without being bothered by clock skew >problems. OUCH - dangerous myth... as Eilert knows well, I hope. Clock skew is likely to lead to hold time violations, which break the design's functionality on EACH INDIVIDUAL clock edge. Hold problems are not related to the time between clocks, and cannot be fixed by running the clock more slowly. >(Actually, some logic between your FFs would be >very useful in this case.) Yes; hold-time fixup. Some FPGA tools already do this for you to some extent. For a small, slow design, the message is clear: USE CLOCK ENABLES. Get your divide-by-10 circuit to generate a synchronous pulse that is true for 1 cycle of the 10Hz clock, and false for 9 cycles. Use that pulse as the clock enable for any logic that you want to run at 1Hz. Use the single, common 10Hz clock as the clock input for every flip-flop in the design. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 139590
Hi, I have to generate a partial bitstream for Xilinx spartan 3 devices for dynamic reconfiguration. My question is about the bitgen partial mask option. i think it is not well documented in the Bitgen manual. i just don't understand how it's working. everytime i'm getting a diffrent strange bitstream. C:\Xilinx\10.1\ISE\bin\nt\bitgen.exe -w -g ActiveReconfig:Yes -g PartialMask0:1 -g PartialMask0:0 -g PartialMask0:0 ... By putting a patialmask on 1 what i'm i omitting and what am i including in the bitstream. Then how can i figure the adresses of Columns , i'm using FPGA editor to find them :) what about the number in hexadecimal .. (I am aware that Dyamic partial reconfiguration is not recommended for Spartan3s ...) Best regards, Hassen.Article: 139591
The question is on the IO selection type. Is there a quick guide to understand on the type of IO for a given chip. For standard interfaces (like DDR2 memory), the IO type will anyway come from memory. But for others (say chip to chip custom interface), what should be the selection criteria? Also, I would assume that choice would also depend on whether it is an ASIC or FPGA. If it is an ASIC, I think the size of the IO buffer would be another factor during selection. Any thoughts/comments? Regards,Article: 139592
On Apr 6, 5:12=A0am, Sharan <sharan.basa...@gmail.com> wrote: > The question is on the IO selection type. > Is there a quick guide to understand on the type of IO for a given > chip. > For standard interfaces (like DDR2 memory), the IO type will anyway > come from > memory. But for others (say chip to chip custom interface), what > should be the selection criteria? > Also, I would assume that choice would also depend on whether it is an > ASIC or FPGA. If it is an ASIC, I think the size of the IO buffer > would be another factor during selection. Any thoughts/comments? > > Regards, There are a few things to look at: 1) DC levels. Look at Vih and Vil, both min and max and make sure the I/O standard meets these specs. 2) DC drive. Most chips have very high impedance inputs, but you may occasionally run into something where this is a consideration. Don't forget the current to drive termination networks if applicable. 3) AC drive. While the load may only require a handful of microamps at DC, if you need incident-wave switching you may need to think of the load more like a resistor of Zo to ground. Also look at the timing specs in your FPGA datasheet to find how much capacitive load can be driven and still meat the nominal timing in your reports. If your load has much more capacitance you probably need to add to your timing margin. Usually simulation is the best way to determine how this affects switching, but you can often estimate the effect as a linear delay adder per unit of load capacitance, especially where you don't need to model the load as a transmission line. Regards, GaborArticle: 139593
I just tried loading this and got a core dump. Anyone else try it yet? John EatonArticle: 139594
I think he is using CoreGenerator. Have you tried using Core Inserter? Core Inserter is the app launched from the Chipscope folder and is much easier to use (my opinion). You can drag and drop the signals you wish to probe from their GUI instead of manually wiring up to ILA ports in your RTL.Article: 139595
> I guess you are referring to ISE versions lower than 10.1. In 10.1, > you need to generate Chipscope cores like any other ip cores via the > coregen which you can run it either within the Project Navigator or > standalone. There is no more Chipscope GUI for generating debug cores. As another poster rightly pointed out, essentially you need to run the chipscope core inserter. That's what gets called by the new file wizard in ISE8.2 anyway. I can't verify if it is indeed broken in 10.1 at the moment, but perhaps you are right. If that's the case just run the Chipscope inserter standalone. /MikhailArticle: 139596
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:4g4it4d9ah49jmotmo9btar8lmd8qoa3cm@4ax.com... > On Sun, 5 Apr 2009 21:55:21 +0200, "Xin Xiao" wrote: > >>Thanks, but I have to do it with schematics..... > > Oh dear. Why? > > Basic Metalwork course, Lab 1: > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > You are given a piece of steel approximately > 5cm x 5cm x 5cm. Your task is to construct > a steel cylinder, of diameter 3cm and length > 4cm, without using a lathe. Marks will be > deducted for any evidence that you borrowed > your friend's CNC milling machine. Extra > credit is available for completing the task > using tools made only from elk antlers. > > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. ???? If he was using Altera Quartus schematic then it would take less than 10 seconds using the LPM_COUNTER wizard - about 100 times faster than using crap VHDL.Article: 139597
On Mon, 6 Apr 2009 17:03:28 +0100, "Dave Wilson" wrote: >???? >If he was using Altera Quartus schematic then it would take less than 10 >seconds using the LPM_COUNTER wizard - about 100 times faster than using >crap VHDL. That's the purest humbug. You can't even START the wizard in ten seconds. Then you have to wade through a gazillion dialogs. Then you have to drop the stupid thing on a sheet and wire it up. Any wizard, no matter how clever, must guide the user through all the choices that the same user could have made with a few keystrokes of text. Give me text any day. Verilog, VHDL, even PALASM if you really must torture me. But spare me the schematics. They have their uses when doodling on restaurant napkins, and maybe for some kinds of top-level block-stitching, but not for anything much else. Schematics live in my head, as a thinking tool, and occasionally leak out on to paper as a tool for communicating with myself or with fellow humans. They are a lousy design entry tool. And that's even before you start to deal with the general crumminess of most schematic capture packages, where tools for ripping and re-numbering buses are palaeolithic, and re-use means working out how to bring up impenetrable property sheets instead of simply patching and commenting the generics on VHDL components. I guess we'll have to agree to differ, but I gave up serious use of schematics a decade ago and I don't miss them even a tiny little bit. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 139598
Jonathan Bromley wrote: > I guess we'll have to agree to differ, but I gave up serious use of > schematics a decade ago and I don't miss them even a tiny little bit. Not to mention problems with re-use, portability to other vendors, and version control software issues (diff anyone?). Serious PL work just isn't done in schematics. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 139599
News123 wrote: > But just imagine, you're lost in a snow storm and a cylinder of your car > is broken. > Then you won't have any CNC machine and you'd be sooo glad to not have > cheated with a CNC machine during your metalwork course. That's fine if you've broken down in Northern America (or thereabouts). How are you going to get elk antlers in outback Australia??? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
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