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"Muzaffer Kal" <kal@dspia.com> wrote in message news:4gau05dlg6fqqrbq8k57ecfoq7149b8ak7@4ax.com... > Nevertheless, if you're just copying from clk0 to clk90, the time you > need is only clk to output delay of one flop and with minimal routing > you should be able to meeting timing; you just can't put any logic > between those two flops. > -- > Muzaffer Kal > What about the setup time of the destination FF? Perhaps the OP could use another DCM to adjust the phase of CLK90 so it can meet the timing. Syms.Article: 140551
On Tue, 12 May 2009 08:13:37 -0700 (PDT), lolita.tangier@gmail.com wrote: |i tried a description of RAM but i can't syntesize it and i have |the following error: | |ERROR:Pack:18 - The design is too large for the given device and |package. | |i think i will be to use the external SRAM FPGA's board, but i don't |know if i can use it without EDK and how i can read and write in this |SRAM. |=========== You do not need EDK to access the onboard SRAM. Webpack is sufficient. You just need a simple SRAM interface with enough address, data and control lines to store and read data from it. jamesArticle: 140552
On Sun, 17 May 2009 00:42:58 +0100, "Symon" <symon_brewer@hotmail.com> wrote: > >"Muzaffer Kal" <kal@dspia.com> wrote in message >news:4gau05dlg6fqqrbq8k57ecfoq7149b8ak7@4ax.com... > >> Nevertheless, if you're just copying from clk0 to clk90, the time you >> need is only clk to output delay of one flop and with minimal routing >> you should be able to meeting timing; you just can't put any logic >> between those two flops. >> -- >> Muzaffer Kal >> >What about the setup time of the destination FF? Perhaps the OP could use >another DCM to adjust the phase of CLK90 so it can meet the timing. >Syms. > Buf of course. With Tcko around ~300ps, setup ~200ps there is not much time left for any wire but I think it's still doable. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140553
> We've done a number of PCIe designs and take the conservative approach of > using parallel FLASH to insure the FPGA configures under the PCI spec reset > time. However, we've found that to be too conservative as the PC goes > through many reset cycles when it powers up. The BIOS will bring it out of > reset and configure the bus then the a PC will go thru another reset cycle > before the OS comes up. So I should not worry about the SPI Flash configuration speed at all ? > Since BW is a concern in your design, you'll want to make sure you have a > DMA engine on your endpoint device and make sure its supports scatter > gather as both Windows and Linux may only provide small memory ranges for > where to stuff your data on the PC side. DMA is required because transfers > originating on the PC side will be broken into single cycle accesses. To do > bursting of data, the transfers will need to originate in the endpoint. I read the application note XAPP1052, and the BUS MASTER DMA design could achieve the bandwidth of 6912Mbps card to PC and 5440Mbps PC to card in the PCIe X4 configuration. XAPP1052 does not implement Scatter Gather DMA, and the performance is already acceptable. Although the test is taken in small data volumn (32768 bytes), larger datasets could be divided into multiples of 32768 bytes. Will the bandwidth reduce largely in my application, say the incoming data at the rate of 500Mbytes/s without the Scatter Gather DMA mechanism?Article: 140554
Hi,
I don't know how many people now are still using opb_hwicap for Virtex
4... well, I am. I found a bug in hwicap_v1_01_a/src/xhwicap_srp.c
that causes "segmentation fault" when you write a icap drive and
insmod it in linux.
lines 170~185:
/*
* Dummy Read as the first data read has to be discarded.
*/
InstancePtr->IsReady = XCOMPONENT_IS_READY;
TempDevId = XHwIcap_GetConfigReg(InstancePtr, XHI_IDCODE);
InstancePtr->IsReady = 0;
#ifdef __KERNEL__ /* Linux Kernel */
extern int XHwIcap_init_remap_baseaddress(XHwIcap *);
if (XHwIcap_init_remap_baseaddress(InstancePtr)) {
return XST_FAILURE;
}
#endif
/* Read the IDCODE from ICAP if specified. */
if (DeviceIdCode == XHI_READ_DEVICEID_FROM_ICAP) {
Actually, lines 170~175 are added for Virtex 4 (they do not exist in
version 1.00a), a dummy first read. Indeed, lines 177~182 (the #ifdef
KERNEL ...) should appear before this first read.
Maybe somebody has already pointed out this bug ... then I'm sorry for
the repetition.
regards
Wenwei Zha
Article: 140555Hi, 1. Anybody success in using ethernet with xps_ll_temac (EDK 10.1, hw driver version 1.01a)? I can't get it work in either MII mode or RGMII mode. (GMII mode is not supported, right?) Even build a system with bsb using MII, an web_server application (adopted from Avnet's reference design) simply fails - can't ping the board ip. Building a system with bsb using XPS_ethernet also fails a ping program. Neither tx or rx led is blinking. I try to modify core xps_ll_temac in RGMII mode, copying constraints from 2.00a's datasheet. I can't pass timing constrains on RX data of 1ns setup and hold time. However, according to HP's RGMII spec, the normal value for setup and hold time is more than 1ns. I relax the timing constrain and got passed. While tx led is blinking, rx led is dead. Is there any problem with hardware ip? The hardware seems to be OK since the "rgmii" reference design on Xilinx's ml410 page works. (But the hw drive is plb_temac with a hard core wrapper). 2. I'm poring a linux to ml410. Anybody is able go use NFS? I'm git latest linux-2.6-Xilinx kernel from xilinx.linux. Obviously, I can not use LL_TEMAC drive, as I said above, I can't get MII or RGMII mode work with a xps_ll_temac core. It seems the only drive I can use is the plb_temac. However, the drive there can't get compiled. I tried to use EDK's BSP generator to generate an alternative drive, copying it to $linux_kernel_dir/drive/net/xilix_temac, however, I still can't get the code compiled. I tried different EDK's linux 2.6 kernel libray versions, without any luck ... 3. I have successfully brought up a web-server program (adopted by Digilent's reference design for X2P board) on a Digilent V4FX12 board. Then I compiled a linux 2.4 kernel with plb_ethernet support. I successfully ported linux on the board. I would like to do the same for the ML410 board. I'm using plb_ethernet 1.01 hw drive. The system is building with EDK BSB. (I need to initially use old version like 8.2 and 9.1). Weirdly, though the message shows that "phy reset is OK", actually I can not ping the ip address I assigned to the ML410 board. RX led is blinking while TX led is blind. Anybody has any suggestion? thanks Wenwei ZhaArticle: 140556
On May 17, 1:16=A0am, -jg <Jim.Granvi...@gmail.com> wrote:
> On May 16, 6:47=A0pm, "Antti.Luk...@googlemail.com"
>
> <Antti.Luk...@googlemail.com> wrote:
> > eh, i just found POC(tm) Pascal On Chip IP core
>
> > it does execute the old pascal-s pseudo codes in hardware
> > only 145 slices :) - without the console opcodes
>
> Any links for that POC ?
>
> Is it a HW version of this ?http://en.wikipedia.org/wiki/P-code_machine#E=
xample_machine
>
> or can it run this ?http://www.moorecad.com/standardpascal/pascals.html
>
> -jg
i think probably more of the later, I did take some pascal-s compiler
and tried to implement it in FPGA
I have done this as AVR virtual machine before, was even tested on
some AVR boards.
the direct FPGA version was optimized for single cycle operation
so every clock 24 bits of instruction and 2 16 bit words TOS/NOS are
fetched from BRAMs
here is list of implemented opcodes (marked with + )
/*
from PASCALM.pas
+ add =3D 0; { opcodes }
+ neg =3D 1;
use T. Coonan verilog muldiv16!
mul =3D 2;
divd =3D 3;
remd =3D 4;
+ div2 =3D 5;
+ rem2 =3D 6;
check comparison!
+ eqli =3D 7;
+ neqi =3D 8;
+ lssi =3D 9;
+ leqi =3D 10;
+ gtri =3D 11;
+ geqi =3D 12;
+ dupl =3D 13;
+ swap =3D 14;
check logic ops
+ andb =3D 15;
+ orb =3D 16;
load =3D 17;
stor =3D 18;
+ hlt =3D 19; { terminate program }
+ stop =3D 20; { end of code }
need a solution for console and streaming?
wri =3D 21;
* wrc =3D 22;
wrl =3D 23;
rdi =3D 24;
rdc =3D 25;
rdl =3D 26;
eofi =3D 27; { check eof }
eol =3D 28;
+ ldc =3D 29;
lda =3D 30; { load address }
ldla =3D 31;
ldl =3D 32;
ldg =3D 33;
stl =3D 34;
stg =3D 35;
implement as P-Code handler??
move =3D 36;
copy =3D 37;
+ addc =3D 38;
mulc =3D 39;
+ jump =3D 40;
+ jumpz =3D 41;
check call
+ call =3D 42;
+ adjs =3D 43;
was same as adjs why ??
++? sets =3D 44;
check exit!
+ exitt =3D 45;
*/
I was at that focusing in as much as possible single cycle exec, so
some op codes are not yet implemented (the hard ones)
also probably some opcodes should be emulated by trap and soft handler
rather then being full in hw
the machine executing the above opcodes is 145 slices
but i do not seem to have tested it with real pascal compiled output,
only some asm test cases
---
I am thinking hard how would be the best way others could benefit the
most of what i have done in my life...
not yet figured out how :( but thinking process is on
Antti
Article: 140557Hi I have done lots of search and research in the past, I guess there is some interest in some report and comparison of different soft processor cores I wonder if i have missed many, I try to include those I found and fetched too, some are no longer available online. dont have a list yet of what are included, just if you think you have found some that i may have missed or if you have some that is not public (but what you may release for REVIEW only) please drop me a note. its all part of my "organize my life(tm)" process what i am doing right now, so it takes some times, but i may publish the report as interim one, as soon as i have some collection of interest ready AnttiArticle: 140558
"Samuel Thomas Kerr" <stkerr@cs.purdue.edu> wrote in message news:Pine.SOC.4.64.0905102207540.1378@lore.cs.purdue.edu... > Hi guys, I'd like to get started with FPGAs and I'm looking for a good > development board to get started with. > > Could you please point me to some good boards? Hi Samuel, The following video may assist. Video number 3 is "Five questions to ask before you choose an FPGA board". http://www.burched.com/freevideos.ag.php Best wishes, Tony BurchArticle: 140559
Hi,
I've succeeded to access the BSCAN_SPARTAN3 without any Xilinx software.
I've used the libusb-driver: http://rmdir.de/~michael/xilinx/
and urJTAG: http://urjtag.org/
The BSCAN_SPARTAN3 has been instantiated as follows in my VHDL code:
[...]
signal jt_shift, jt_tck, jt_update, jt_tdi, jt_tdo, jt_capture, jt_tck2,
jt_sel1, jt_sel2, jt_rst, jt1, jt2, jt3 : std_ulogic := '0';
[...]
BSS3_1 : BSCAN_SPARTAN3
port map (CAPTURE => jt_capture,
DRCK1 => jt_tck,
DRCK2 => jt_tck2,
RESET => jt_rst,
SEL1 => jt_sel1,
SEL2 => jt_sel2,
SHIFT => jt_shift,
TDI => jt_tdi,
UPDATE => jt_update,
TDO1 => jt_tdo,
TDO2 => jt_tdi);
process (jt_tck)
begin -- process
if jt_tck'event and jt_tck = '1' then -- rising clock edge
jt1 <= jt_tdi;
jt2 <= jt1;
jt3 <= jt2;
jt_tdo <= jt3;
end if;
end process;
process (jt_update)
begin -- process
if jt_update'event and jt_update = '1' then -- rising clock edge
led(3) <= jt3;
led(2) <= jt2;
led(1) <= jt1;
end if;
end process;
[...]
I have compiled libusb-driver and urjtag, and run it as follows:
$ PATH="/home/user/urjtag/bin":$PATH \
LD_PRELOAD="/home/user/xilinx-usb-driver/libusb-driver.so" jtag
Then from the jtag prompt I have run the following commands (I have used the
Xilinx SPARTAN-3E Starter Kit via the USB platform cable):
cable xpc_ext
detect
part 0
instruction BYPASS
part 1
instruction BYPASS
part 2
register UR 3
instruction USER1 000010 UR
instruction USER1
shift ir
dr 111
shift dr
I could set the required LED pattern with the sequences like
dr 100
shift dr
dr 001
shift dr
In fact, to get the whole thing working, I had to introduce a small
modification in the urJTAG files.
In the original urJTAG, the "detect" command returned the following results:
jtag> detect
IR length: 22
Chain length: 3
Device Id: 00000110111001011110000010010011 (0x0000000006E5E093)
Manufacturer: Xilinx
Part(0): XC2C64-VQ44
Stepping: 0
Filename:
/home/user/urjtag/share/urjtag/xilinx/xc2c64a-vq44/xc2c64a-vq44
Device Id: 11110101000001000110000010010011 (0x00000000F5046093)
Manufacturer: Xilinx
Part(1): xcf04s
Unknown stepping!
Device Id: 00000001110000100010000010010011 (0x0000000001C22093)
Manufacturer: Xilinx
Part(2): xc3s500e_fg320
Stepping: 0
Filename:
/home/user/urjtag/share/urjtag/xilinx/xc3s500e_fg320/xc3s500e_fg320
chain.c(149) Part 1 without active instruction
chain.c(200) Part 1 without active instruction
chain.c(149) Part 1 without active instruction
jtag>
And then I was not able to set the INSTRUCTION for the part 1:
jtag> part 0
jtag> instruction BYPASS
jtag> part 1
jtag> instruction BYPASS
instruction: unknown instruction 'BYPASS'
jtag>
I have found that the SETTINGS file for the xcf04s
( /home/user/urjtag/xilinx/xcf04s/SETTINGS ) contains the following entry:
# bits 31-28 of the Device Identification Register
0000 xcf04s 0
This bits in my xcf04s are set to '1's, so I've added the following line:
( PLEASE BEWARE, THAT I HAVE DONE IT WITHOUT ANY KNOWLEDGE AND UNDERSTANDING
WHAT THIS LINE IS FOR :-(. I JUST WANTED TO BYPASS THE xcf04s. PROBABLY
ACCESSING ANY OTHER FUNCTIONS OF xcf04S REQUIRES MORE REASONABLE ADJUSTMENT
OF "SETTINGS" FILE. OTHERWISE THE CHIP MAY BE POSSIBLY DAMAGED)
# bits 31-28 of the Device Identification Register
0000 xcf04s 0
1111 xcf04s f
After this change detection worked correctly:
jtag> detect
IR length: 22
Chain length: 3
Device Id: 00000110111001011110000010010011 (0x0000000006E5E093)
Manufacturer: Xilinx
Part(0): XC2C64-VQ44
Stepping: 0
Filename:
/home/xl/urjtag/bin/share/urjtag/xilinx/xc2c64a-vq44/xc2c64a-vq44
Device Id: 11110101000001000110000010010011 (0x00000000F5046093)
Manufacturer: Xilinx
Part(1): xcf04s
Stepping: f
Filename: /home/xl/urjtag/bin/share/urjtag/xilinx/xcf04s/xcf04s
Device Id: 00000001110000100010000010010011 (0x0000000001C22093)
Manufacturer: Xilinx
Part(2): xc3s500e_fg320
Stepping: 0
Filename:
/home/xl/urjtag/bin/share/urjtag/xilinx/xc3s500e_fg320/xc3s500e_fg320
And I was able to set the xcf04s in the BYPASS mode:
jtag> part 0
jtag> instruction BYPASS
jtag> part 1
jtag> instruction BYPASS
jtag>
So now, the "only" thing I have to add are the Python bindings for urJTAG...
--
Regards,
Wojtek
Article: 140560Hi, Creating of Python bindings for urJTAG appeared to be too complicated :-( (hopefully it will be possible to change it in the future). Therefore I have created a quick (but SLOOOW in operation) solution, based on interactive communication with urJTAG shell via the Python pexpect module. You can find the code here: http://groups.google.com/group/alt.sources/browse_thread/thread/603ff14bdf020776# (remember to access the message via the "show original" option). -- Regards, WojtekArticle: 140561
On May 17, 11:01=A0pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On May 17, 1:16=A0am, -jg <Jim.Granvi...@gmail.com> wrote:
>
> > On May 16, 6:47=A0pm, "Antti.Luk...@googlemail.com"
>
> > <Antti.Luk...@googlemail.com> wrote:
> > > eh, i just found POC(tm) Pascal On Chip IP core
>
> > > it does execute the old pascal-s pseudo codes in hardware
> > > only 145 slices :) - without the console opcodes
>
> > Any links for that POC ?
>
> > Is it a HW version of this ?http://en.wikipedia.org/wiki/P-code_machine=
#Example_machine
>
> > or can it run this ?http://www.moorecad.com/standardpascal/pascals.html
>
> > -jg
>
> i think probably more of the later, I did take some pascal-s compiler
> and tried to implement it in FPGA
I see also the link above extends the pascal-s, to have INTEGER and
REAL operands
> I have done this as AVR virtual machine before, was even tested on
> some AVR boards.
>
> the direct FPGA version was optimized for single cycle operation
> so every clock 24 bits of instruction and 2 16 bit words TOS/NOS are
> fetched from BRAMs
>
> here is list of implemented opcodes (marked with + )
>
> /*
> =A0 =A0 from PASCALM.pas
>
> + =A0 =A0add =A0 =3D =A0 =A0 0; =A0 =A0 { opcodes }
> + =A0 =A0neg =A0 =3D =A0 =A0 1;
>
> use T. Coonan verilog muldiv16!
>
> =A0 =A0 mul =A0 =3D =A0 =A0 2;
> =A0 =A0 divd =A0=3D =A0 =A0 3;
> =A0 =A0 remd =A0=3D =A0 =A0 4;
>
> + =A0 =A0div2 =A0=3D =A0 =A0 5;
> + =A0 =A0rem2 =A0=3D =A0 =A0 6;
<snip>
>
> I was at that focusing in as much as possible single cycle exec, so
> some op codes are not yet implemented (the hard ones)
> also probably some opcodes should be emulated by trap and soft handler
> rather then being full in hw
Looks good, it also looks to be quite close to Instruction List
capable,
http://www.3s-software.com/index.shtml?en_CoDeSys_IL
so perhaps an IL assembler could be viable ?
-jg
Article: 140562I've built a website - http://OutputLogic.com - with online tools that generate a Verilog code for parallel CRC and Scrambler given data width and polynomial coefficients. Also, there are short posts that describe an efficient parallel CRC/ Scrambler generation algorithm for Verilog or VHDL that I've used. -evgeniArticle: 140563
Hi, I've declared a memory in test bench code and i've initialised the memory in test bench module itself. I need to transfer this memory contents to design block of my code. Pls tell me how can i go ahead... Thanks.Article: 140564
"-jg" <Jim.Granville@gmail.com> wrote in message news:64002ea3-bfef-405a-84bb-7e26dc060a57@b34g2000pra.googlegroups.com... On May 16, 6:47 pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > eh, i just found POC(tm) Pascal On Chip IP core > > it does execute the old pascal-s pseudo codes in hardware > only 145 slices :) - without the console opcodes Any links for that POC ? Is it a HW version of this ? http://en.wikipedia.org/wiki/P-code_machine#Example_machine or can it run this ? http://www.moorecad.com/standardpascal/pascals.html ============== Linked from that wikipedia page: A concise definition of the p-code machine: http://homepages.cwi.nl/~steven/pascal/book/10pcode.html. The OCR'ed book from whence it came: http://homepages.cwi.nl/~steven/pascal/book/. C source for a compiler and interpreter, along with p-code versions: http://homepages.cwi.nl/~steven/pascal/. One supposes a core running the compiler can boot itself from a text terminal on the UART. Aside from solving a problem the world doesn't even know it has yet, I wonder how many cores will fit on a Spartan3 400A. For that matter, it sounds like a cool way to flash 7-segment LEDs on a coolrunner.Article: 140565
thank you very much i just used an interface between the SoC and the external SRAM and it's working regards lolitaArticle: 140566
On Sun, 17 May 2009 23:10:56 -0700 (PDT), wrote: >I've declared a memory in test bench code and i've initialised the >memory in test bench module itself. I need to transfer this memory >contents to design block of my code. Pls tell me how can i go ahead... In SystemVerilog the ports of a module can be of multi-dimensional array type (including "memories"). In regular Verilog, though, you have these two choices: 1) If the memory is fairly small, combine its elements into a single long vector using a "for" loop. Pass the combined vector through a port of your module. Unpack it back to an array with another procedural loop inside your module. You can do this all in combinational (zero-time) logic, since it's really just a re-arrangement of wires. 2) Transfer the memory's contents one word at a time, using some kind of sequential mechanism - in hardware you would use a state machine; in simulation-only code, you could use a loop that reaches into the target module by cross-module reference. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140567
"rickman" <gnuarm@gmail.com> wrote in message
news:a87c5ee0-0dc1-4035-b8b6-9803b7ce1a75@g19g2000vbi.googlegroups.com...
On May 6, 2:48 pm, "M.Z." <mzdkm...@gmail.com> wrote:
> Hi Rick,
>
> I have had similar problems with the 'Generics, Parameters' under
> 'Synthesis Options'. I could get it to work in a simple example, but
> synthesis did not react on the value for a more complex design.
>
> But there is an alternative through the 'Other XST Command Line
> Options', which is last line in the window with 'Generics,
> Parameters'. You can then use the XST command line syntax, that
> Jan Pech mentioned, thus '-generics {BIDIR=TRUE CHANNELS=1}'. That
> worked for me.
>
> Good luck,
> Morten
I had thought of that. But it doesn't work an better. Here is the
error message I get when I try it.
WARNING:Xst:2705 - Value 'FPGA_FAMILY_SPARTAN_3' is not a valid value
WARNING:Xst:2312 - Ignoring definition of generic 'DEVICE_FAM' because
of bad value provided
The option lines I tried were
-generics {DEVICE_FAM=FPGA_FAMILY_SPARTAN_3}
and
-generics{DEVICE_FAM=FPGA_FAMILY_SPARTAN_3}
I also tried it with quotes and got this error message.
ERROR:Xst - CheckCondition -
Xst_HdlConst_Utility::ConvertIntegerToType : unable to adjust constant
<"FPGA_FAMILY_SPARTAN_3"> (type array [1 to 21] of char) to type enum
(fpga_family_spartan_3, fpga_family_lattice_xp, ).
-generics {DEVICE_FAM="FPGA_FAMILY_SPARTAN_3"}
and
-generics{DEVICE_FAM="FPGA_FAMILY_SPARTAN_3"}
I believe I also tried it with spaces around the = sign, but the
manual clearly say not to leave spaces there.
I am starting to think the problem is the use of an enumerated value
rather than a string constant or a numerical constant. I changed it
to an integer and it still does not work when using a constant name.
But if an integer value is used, it works ok. It would seem that the
generic input function in XST does not work with symbols, only
values.
================
I think I saw something like that done in the LEON3 and GRLIB distribution.
It might be worth a look.
Article: 140568On May 17, 7:10 am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > I have done lots of search and research in the past, I guess there is > some interest in some > report and comparison of different soft processor cores > > I wonder if i have missed many, I try to include those I found and > fetched too, some are no longer > available online. > > dont have a list yet of what are included, just if you think you have > found some that i may have missed > or if you have some that is not public (but what you may release for > REVIEW only) please drop me a note. > > its all part of my "organize my life(tm)" process what i am doing > right now, so it takes some times, but > i may publish the report as interim one, as soon as i have some > collection of interest ready > > Antti If you are interested, I could provide details on a CPU I have designed/am designing. It is a stack based processor with an architecture similar to Bernd Paysan's B16, but with a very different instruction design (both the instruction set and the encoding). I designed an 8 bit instruction/16 bit data path form some time ago which I used in a simple application and have reworked it as a 9 bit instruction/18 bit data path form more recently which has not been used as yet. RickArticle: 140569
I recalled a site which generated code for CRCs and did a search for: crc online vhdl ethernet verilog Both gave a nominal 4,300 hits but with Google there was no link to the site I required within a hundred hits, yet the same search in Yahoo gave the desired result in hit number 4: http://www.easics.be/webtools/crctool I've never been a fan of Google but it only goes to show. FYI - I have no connection with Google, Yahoo or Easics!Article: 140570
Avnet hosts a 1-day, Xilinx-focused "X-Fest" every 18 to 24 months. Here's a few links from the last time it was held in 2007. The articles mention that the next one was tentatively planned for 2008, but that did not happen. http://www.fpgajournal.com/news_2007/08/20070815_01.htm http://news.thomasnet.com/companystory/518935 http://www.em.avnet.com/evs/home/0,4582,CID%253D35679%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32233%2526BID%253DDF2%2526CTP%253DEVS,00.html?SUL=xfest BryanArticle: 140571
On Fri, 15 May 2009 13:00:00 -0700, Mike Treseler wrote: >The surviving conferences >are focused on academia and sales rather than practical design. I think that's perhaps a little unfair to DesignCon and DVCon, both of which usually have plenty of very practical content. But it is certainly true that they tend to be more ASIC than FPGA focused. And it is also true that some other well-known conferences emphasise academic developments (fascinating to tool developers, but less interesting to design grunts like you and me) at the expense of practical considerations. You may well find that the tool vendors' user-group meetings (Synopsys SNUG, Cadence CDNLive, Mentor u2u) are a good source of practical know-how. And they tend to be less expensive to attend than the mainstream conferences, and to offer events in a wider range of geographical locations. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140572
Hi eh sometimes i just wanna shine, i guess :) but well it was real nice seeing AVR code loaded and executed from SD card by bootstrap code in the 128 byte FlashROM of Actel FPGA the complete SD card bootstrap code takes 55 AVR instructions (from 64 available) ah, the SPI is FULL software bit bang, there is no SD related hardware peripherals. well the AVR core in the FPGA is little modified 1 ROM is mapped to RAM space both read write 2 SBI/CBI are modified to be able to write Carry to IO port :) without [2] the code would be 56 instructions but still fit. this code bootstraps from file copied to FAT file system, using NoFAT (tm) method, SDHC is not supported I guess, without NoFAT, it might be possible to add SDHC support too, but then initial bootstrap would need to be in sector 0, what is possible but requires special SD card formatting tool Antti PS and yes, this just one bootstrap for the FPGA-AVR module with Actel PA3Article: 140573
On May 15, 4:00=A0pm, John McCaskill <jhmccask...@gmail.com> wrote: > Xilinx has switched to using FlexLM for licensing as of ISE 11.1. =A0I > have been using multiple other software packages that use FlexLM for > years, so I have some experience with the issues that it can cause. > FlexLM is more restrictive than just giving you an activation ID, and > I expect that they will be getting a lot of calls from customers about > this. =A0However, after evaluating how Xilinx has used FlexLM, I think > that some of your issues above have been addressed in a reasonable > fashion, and I think that some of their licensing terms have been made > more favorable for the customer. I've dealt with FlexLm in the past, and I've learned to curse its very existence when the license server, typically in an inaccessible location, goes down. This always happened on a weekend with a looming Monday-morning deadline. But all that aside, after all these years, Xilinx still doesn't get it. We use their software to develop applications FOR THEIR CHIPS. There is no other use for it. Locking it down and otherwise making it difficult to install and use is at cross purposes with Xilinx' objectives: selling chips. Now I understand that there is a real cost for technical support. What Xilinx needs to do is to uncouple tech support from the cost of the tools. To wit: a) If you are a hobbyist and you want to play with a starter kit or whatever, use the tools and use the various WWW resources for support. You don't get a tech-support account and Xilinx won't answer your phone calls. b) The professional user should be able to choose between per-incident and blanket yearly tech-support options. Perhaps two tiers of support should be available -- initial WebCase, and direct-to-smart-people telephone support. The point is that if we are paying directly for the support, we expect REAL results and not the usual web-case runarounds. c) In either case, any user (from the hobbyist to the pro) should be able to report bugs and get updates on their resolutions. Xilinx should not cut off a source of bug reports simply because the users aren't paying for support. As it is now, users who buy ISE/EDK etc spend a lot of money and don't get any real support, and this latest licensing nonsense is a kick in the teeth. -aArticle: 140574
On May 15, 3:30=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 14 May 2009 16:02:00 -0700 (PDT), Andy <jonesa...@comcast.net> wr= ote: > > >As others have pointed out, a Synchronously Deasserted Asynchronous > >Reset (SDAR) still allows the system to reset without a clock, but the > >system cannot resume without a clock (the latter of which is identical > >to synchronous resets). > > Therefore be extra careful when applying Reset to your clock generator > (e.g. Xilinx DCM) > > Don't ask me how I know this. I would imagine that you learned that lesson the same way I did ... -a
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