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Hi, How to run ngcbuild in windows xp environment? Does it run only at command line? How can I run command line in windows xp? thanks, JasonArticle: 89801
Excellent! Thank you very much for the fine work, sir! The MAPLD conference is one of the best out there, and I unfortunately have been too busy with work this year to attend. Bill McCulley Ft. Worth, TX Richard B. Katz wrote: > Hi, > > Almost all of the presentations from the 2005 MAPLD (Military and Aerospace > Programmable Logic Device) International Conference, held earlier this month, > are now on-line. There are a few items that need cleanup which will be taken > care of soon. > > You may access the presentations by Session from the conference home page: > > http://klabs.org/mapld05 > > Comprehensive proceedings can be found at: > > http://klabs.org/mapld05/abstracts/ > > Papers will be posted in October. If you find any errors, please let me know. > > Regards, > > Rich Katz > National Aeronautics and Space AdministrationArticle: 89802
Hi, LVDS is not a bidirectional standard. It is a standard that has sinks, and sources (as in one each, a source at one end, and a sink at the other). You will have to do something a bit non-standard to do this. I saw one suggestion to use a bus-LVDS output, with an LVDS input, where now you can actually control the output (go tristate). But, perhaps there is someone else out here who has managed to figure out how to do this (in spite of the fact it isn't a standard, so we have little reason to support it). Austin assaf_sarfati@yahoo.com wrote: > Hi all, > > I am trying to create LVDS, bidirectional, DDR I/O pads > in a Spartan-3E chip (xc3s500e). > > I've created an I/O pad in VHDL which simply instatiates > and connects Xilinx library components: > * IOBUFDS = bidirectional, differential I/O pad, > * IDDR2 = S3E input DDR logic, > * ODDR2 = S3E output DDR logic, > Tri-State control is not DDR - I've added a simple FF > instance. > > The pad matches a subset of the S3E description of the > I/O pad logic. > > When I try to implement a chip using these I/O pads, the synthesis > and Translate stages complete without errors, but the Map stage > outputs the following error for each I/O Pad: > > ERROR:Pack:1564 - The dual data rate register > Data_Pad/IO_Pad6/Out_DDR_Reg/Data_Pad/IO_Pad6/Out_DDR_Reg/ODDR2.C0D1 > > failed to join the DIFFSI component as required. Symbol > Data_Pad/IO_Pad6/Out_DDR_Reg/Data_Pad/IO_Pad6/Out_DDR_Reg/ODDR2.C0D1 > > is not a kind of symbol that can join a DIFFSI component. > >>From what I've been able to find, the DIFFSI is the "negative" > pin of the I/O pad - the I/O logic is placed at the "positive" > pad, but borrows resources from the negative pad, which can't > be used for anything else. > > The error is connected to having bidirectional pads; when I used > separate input and output pads, there were no errors. > > There is no difference in the errors when I place LOC constraints > on the positive, negative, both or none of the I/O pads. > > The IDDR2 and ODDR2 have Generic options to control clock > alignment, some of which borrow FFs from the negative pad; > changing these Generics make no difference in the errors. > > I am using ISE7.1i, SP4 (problem appeared in SP3 as well). > The Xilinx knowledge base doesn't have anything about this error. > > Anyone knows what is the problem and if there is any way to > fix it? please help, I am getting pretty desperate (need to > start board layout). > > Thanks in Advance >Article: 89803
After try and error, it seems that ngcbuild can only be launched in command line mode. Here is the command I used to combine .ucf and .ngc file. ngcbuild -uc <ucf file name>.ucf <input design name> <output design name>.ngcArticle: 89804
I need an ARM environment, hopefully a complete ARM9 and bus, on an FPGA to prototype multiple copies of a custom, loosely coupled, media signal processor. The MSP is about 50K (real) gates with 16KB of dual-port memory on each. I'd like to try to hang two of them (total 100K gates and 32KB dual-port) off an AHB or AHB2 to test the interprocessor communication with an RTOS plus driver/manager software. The old Altera Excalibur looks like the ideal solution, especially if I can find an old EPXA10 DDR Dev Board. Any suggestions would be deeply appreciated.Article: 89805
After try and error, below is the way I create the RPM: (1) XST: in xilinx specific options, uncheck "Add I/O Buffers" (2) XST -> translate (3) Map: in map properties, uncheck "trim unconnected signals" (4) Map->PAR (5) Open floorplaner, floorplan-replace all with placement file-write RPM to UCF It will generate .ucf file (6) Run ngcbuild, it needs to be run at command line: ngcbuild -uc <ucf file name>.ucf <input design name> <output design name>.ngc The generated ngc file contains all the RPM information.Article: 89806
Your wear-out analogy does not apply. Metastability failure is completely statistical and probabilistic. Even when the MTBF is a million years, the failure can occur in the next second. Not likely, but possible. That's why I claim that the problem can never be solved. We can only reduce the probability down to an acceptable level. I really believe that this is an important distinction vs any failure besed on wear-out. Peter AlfkeArticle: 89807
Hello 'CMOS' It is usually a very bad idea to use a signal in the combinational process that updates it because it describes an asynchronous loop. I think you should use a synchronous process instead. NicolasArticle: 89808
Hi kd, Not sure if this may help you... But I'm using a Virtex4FX and I found no problem to implement uIP on 10/100/1000 Mbps. uIP is a light version of lwIP. If you go on http://www.sics.se/~adam/uip/index.html you can find a lot of documentation on lwIP and uIP. >From this website you can find also some examples like: Web-server, Web-Client, email sender, telnet terminal. The Web-server is working fine... and I can browse a static web page (that is inside the FPGA) Xilinx has a good app notes (xapp 807) about uIP (Is a A++ app notes) Going from uIP to lwIP should be not difficoult according to http://www.sics.se/~adam/uip/index.html I hope this help, FrancescoArticle: 89809
The message means the ILA does not capture data, with which trigger conditions are met. You can check the trigger condition again or maybe VIO will be needed.Article: 89810
We have been using the LVDS BUS mode for some time now and it works well enough... haven't tried it as DDR so can't qualify that part. I have found that you have to be excessively explicit about tieing things down.. and you MUST use the UNISIM libraries or it won't work... XST keeps optimizing things down until it won't connect correctly any more. I ended up creating a standard IO block which has 3 latches (can be inferred) the inverter (from UNISIM) and the LVDS tri-buffer and receiver (FROM UNISIM) Inside the block I use pragmas to force the flip flops into the IO buffer although I have seen it ignore this but it doesn't seem to matter at the speeds I'm running at. I also use a few keeps to prevent optimizing of the inverters etc.... What would be better, of course, is to have a standard symbol which when placed, allowed you to select the IO standard, tri-state or not, receiver or not, IO latch or not. It would simplify things down. Simon "austin" <austin@xilinx.com> wrote in message news:dhaje8$skg7@xco-news.xilinx.com... > Hi, > > LVDS is not a bidirectional standard. It is a standard that has sinks, > and sources (as in one each, a source at one end, and a sink at the other). > > You will have to do something a bit non-standard to do this. > > I saw one suggestion to use a bus-LVDS output, with an LVDS input, where > now you can actually control the output (go tristate). > > But, perhaps there is someone else out here who has managed to figure > out how to do this (in spite of the fact it isn't a standard, so we have > little reason to support it). > > Austin > > > assaf_sarfati@yahoo.com wrote: > > Hi all, > > > > I am trying to create LVDS, bidirectional, DDR I/O pads > > in a Spartan-3E chip (xc3s500e). > > > > I've created an I/O pad in VHDL which simply instatiates > > and connects Xilinx library components: > > * IOBUFDS = bidirectional, differential I/O pad, > > * IDDR2 = S3E input DDR logic, > > * ODDR2 = S3E output DDR logic, > > Tri-State control is not DDR - I've added a simple FF > > instance. > > > > The pad matches a subset of the S3E description of the > > I/O pad logic. > > > > When I try to implement a chip using these I/O pads, the synthesis > > and Translate stages complete without errors, but the Map stage > > outputs the following error for each I/O Pad: > > > > ERROR:Pack:1564 - The dual data rate register > > Data_Pad/IO_Pad6/Out_DDR_Reg/Data_Pad/IO_Pad6/Out_DDR_Reg/ODDR2.C0D1 > > > > failed to join the DIFFSI component as required. Symbol > > Data_Pad/IO_Pad6/Out_DDR_Reg/Data_Pad/IO_Pad6/Out_DDR_Reg/ODDR2.C0D1 > > > > is not a kind of symbol that can join a DIFFSI component. > > > >>From what I've been able to find, the DIFFSI is the "negative" > > pin of the I/O pad - the I/O logic is placed at the "positive" > > pad, but borrows resources from the negative pad, which can't > > be used for anything else. > > > > The error is connected to having bidirectional pads; when I used > > separate input and output pads, there were no errors. > > > > There is no difference in the errors when I place LOC constraints > > on the positive, negative, both or none of the I/O pads. > > > > The IDDR2 and ODDR2 have Generic options to control clock > > alignment, some of which borrow FFs from the negative pad; > > changing these Generics make no difference in the errors. > > > > I am using ISE7.1i, SP4 (problem appeared in SP3 as well). > > The Xilinx knowledge base doesn't have anything about this error. > > > > Anyone knows what is the problem and if there is any way to > > fix it? please help, I am getting pretty desperate (need to > > start board layout). > > > > Thanks in Advance > >Article: 89811
I would second that ... Sorry about doing your homework....
1/ Synchronous counter desperately needs a clock.. you will get funny in
between states when multiple bits transition simultaneously. And the state
machine will quickly be in left field.
2/ Simulators need a reset.
3/ You need to assign state.. or better still, ignore next_state and just
use state.
4/ Be nice to people who follow and give processes sensible names and add
comments... no comments, no marks in my book
5/ what happens to ram_counter_w when it hits 131071 and wants to increment?
library ieee;
use ieee.std_logic_unsigned.all;
type state_type is (
rw_1, rw_2, rw_3
);
signal state: state_type;
signal ram_counter_w: integer range 0 to 131071;
state_machine : process (clk) is
begin
-- add an async reset ?? or a synchronized reset
if rising_edge(clk) then
if ((reset = '1') or (start = '0')) then
state <= rw_1;
ram_counter_w <= 0;
else
case state is
when rw_1 =>
state <= rw_2;
ram_counter_w <= ram_counter_w + 1;
when rw_2 =>
if (ram_counter_w = 131070) then
state <= rw_3;
else
state <= rw_1;
end if;
when rw_3 =>
-- some statements...
when others => -- Default case if reset or some crap happens!
-- some statements
end case;
end if;
end process state_machine;
"Nicolas Matringe" <nic_o_mat@msn.com> wrote in message
news:1127803075.305910.74310@g14g2000cwa.googlegroups.com...
> Hello 'CMOS'
> It is usually a very bad idea to use a signal in the combinational
> process that updates it because it describes an asynchronous loop.
> I think you should use a synchronous process instead.
>
> Nicolas
>
Article: 89812If you look at some of the history... the cheapest way to reverse engineer a project... is to pay off one of the designers and just get him to send you the source. Of course you might get caught.. but then it comes down to who has the biggest check book for lawyers. Back in the 80's I was given a book on the costliest computer hacks... the first was a disgruntled employee with a fire-axe ... (there's a moral here) Simon "Austin Lesea" <austin@xilinx.com> wrote in message news:dh92it$skg6@xco-news.xilinx.com... > Adam, > > It was pointed out to me the other day, that Neocad reverse engineered > bitgen. They never reverse engineered the bitstream (had no idea what > controlled what). > > Folks are ofthen fond of saying "there is no security in obscurity" but > then they do not have to search for a needle in a haystack. > > Keeping the bitstream secret is still a powerful means of preventing > reverse engineering. > > Lately I asked a well know reverse engineering firm to do their job, and > tell me what the design was given only the bitstream. > > They no bid the job "as we felt it would take to long, and cost too > much." That definitely surprised me, as to refuse business for > something that is understandably long and arduous (read $$$) was a surprise. > > But from their point of view, they would much rather go after something > that was easier (cut, section, etc.) and had immediate payback. > > Now it is said that governments would not be so limited (they would > reverse engineeer a bitstream). > > Very few of our customers are worried about a governement stealing their > designs and intellectual property. For those that are (other > governments), we are happy to assure them that the bitstream still > remains a secret (for what that is worth, which may in fact be a lot). > > So far the 'Logic Vault' cards I have sent out to academia have not been > able to be cracked by DPA (a commonly held belief is that differential > power attack (DPA) is able to 'crack' 3DES or AES easily). Seems that > finding the keys in a smart card may be a junior EE class exercise, but > going after something a bit more challenging (like the keys held in out > battery backed RAM) is no easy task. > > I'd like to think that it has to do with brilliant engineering, but it > is more likely that one can not discern the information from the noise > of all those pesky support transistors that clutter up a FPGA. > > Austin > > Adam Megacz wrote: > > >>Some one already told me "Jbits is dead" but didn't explain why ! > > > > > > Because http://www.megacz.com/research/bitstream.secrecy.xt > > > > - a > >Article: 89813
francesco_poderico@yahoo.com wrote: > Hi kd, > Not sure if this may help you... > But I'm using a Virtex4FX and I found no problem to implement uIP on > 10/100/1000 Mbps. Cool...I've been trying to make the time to play with this and the associated app-note from Xilinx. Have you had a chance to do any throughput testing? I.e., there was a discussion a few weeks back here about trying to send hundreds of megabits/sec through this interface, using, say, UDP instead of TCP to reduce the overall overhead/buffering required. I would be VERY curious to see if you can really push bits that fast through the gig-E port with this setup...the app note gives some preliminary info regarding throughput, but its all in terms of how long before a steady TCP data stream will cause an internal overflow of the buffers that hold the TCP segments (IIRC)..any chance you're interesting in doing a little experimentation with UDP for the good of the group??? :-) JohnArticle: 89814
"Jason Hu" <shihhsin.hu@gmail.com> wrote in message news:1127794969.565784.91570@g49g2000cwa.googlegroups.com... > Hi, > > How to run ngcbuild in windows xp environment? > Does it run only at command line? > How can I run command line in windows xp? > > thanks, > > Jason > Click "Start" Click "Run..." Type "cmd" Now you should see a window with the command prompt. Use it like Linux or Solaris shell. MarcoArticle: 89815
thank you very much for all of your comments. i ll try proposed methods in a while. although i read a full book on introduction to VHDL for simulation and synthesis, i think i dont have enough knowledge to build a complex sysytem. the book i reead does not stress on the points you've mentioned here well. so im trying to find some good material on VHDL for sysnthesis ( specially for FPGA's ). If someone knows any resources, please let me know. One other question. i got a book on "VHDL and AMS", which is about designing systems that might involve analog electronics as well. Im not sure about the extent to which this type of designing is used in the industry, so delaying reading of the book. Please if someone knows about of this, let me know.. Thank you CMOSArticle: 89816
austin wrote: > Hi, > > LVDS is not a bidirectional standard. It is a standard that has sinks, > and sources (as in one each, a source at one end, and a sink at the other). > > You will have to do something a bit non-standard to do this. > > I saw one suggestion to use a bus-LVDS output, with an LVDS input, where > now you can actually control the output (go tristate). > > But, perhaps there is someone else out here who has managed to figure > out how to do this (in spite of the fact it isn't a standard, so we have > little reason to support it). > > Austin > > What I meant was: I want to create a bidirectional, differential I/O pad, using LVDS voltage-levels and signaling, and Dual-Data- Rate transfers. My problem is in the low-level entity encapsulating the I/O pad and the assicated DDR logic. BTW, the same problem occured when I created separate input and output pads (each with the required DDR logic), and tied the I/O pins together at the top level. I guess the mapper recognizes that both input and output paths go to the same pad, places them together and THEN chokes on it. If the I/O pins are kept separate without any other change, everything is implemented correctly. I wasn't trying to implement a "real" LVDS standard, and my design has the provisions to change direction cleanly without glitches and bus contention.Article: 89817
You can choose any one you like, but you have to think about whether you are going to get a devleopment board or make your own. Go to www.altera.com, and see what suits you. Cyclone is a good series to start with, as they are relatively cheap, and you can prototype boards yourself if you wish. Just do a google search for cyclone schematics, and you will come up with quit ea bit. My web page also has schematics for my dev. board, so you can maybe get some helpful info from there (http://via.dynalias.org).Article: 89818
Hi everyone!Who have been done this aspect?I want to do this,but i don't how to do.Can you give some advice?For example,i want to do image feature extraction based on FPGA.I'm a learner.Thank for your ideas.Article: 89819
Neil, We use PVCS for version control with our VHDL, and it works just fine. The only tricky part is figuring out what files (beyond the vhdl) that your tool really needs to recreate a particular version, such as constraints, cores, and project setting files. Since we use 3 different tools (Active-HDL / Synplicity / Xilinix ISE), it took a while to figure out which files store which configuration information to truly recreate a project from pvcs. I would recommend creating the pvcs project folders to exactly mirror your fpga working folder structure. -Paul QuadTech "Neill A" <neilla@ewst.co.uk> wrote in message news:1126861259.461630.193380@g44g2000cwa.googlegroups.com... > I've just started looking into getting our VHDL code into some sort of > version control tool, and would like to get some information about > which ones work best with VHDL & FPGA tools. > > All our designs are done using Actel Libero, and AFAIK it doesn't > provide any helpful features for version control. I have previously > used SourceSafe for a little while, but since we are just a small > company I think the cost is a bit much. > > Our software team currently use PVCS, has anyone had any experience > using this with VHDL? >Article: 89820
Bought the starter board from xilinx and the jtag-usb cable from digilent. I've had the starter board a few weeks. And seeing that I only have USB on my laptop, I purchased the usb cable. This way I won't have to use my slow and noisy machine with a par-port to program the board, I thought. But I can't get the cable working properly. It (ExPort software from digilent) finds the chain and when I program the xc3s200 the sw says it worked ok. But...it didn't, the board is totally hung and pressing the Prog button on the board doesn't do anything (still had the original prom-config that was pre-loaded). Removing and reapplying the power to the board, and everything works ok again. Am I missing anything elemtary here? Like settings for the .bit file or something? Just tried it with a SVF file and now the PROM is empty as well...even though I asked the prom to be bypassed. Programming with the par-cable still works fine, though (thankfully, nothing is dead on the board) Any help would be appreciated! Cheers! ((miceArticle: 89821
It's possible that the driver was improperly installed/uninstalled by the installer. Try running 'bblpt /r' followed by 'bblpt /i' from the quartus\drivers\i386 directory. Hope this helps, Subroto Datta Altera Corp.Article: 89822
Hi, I are looking to purchase some FPGA software in the very near term for a project utilizing Xilinix's Virtex-4 device. I are relatively new to FPGA design and would appreciate any comments from those who have experience with Virtex-4 regarding FPGA synthesis software options. I have looked at Mentor, Synplicity, Synopsis, and Xilinx solutions. Are there any recommendations for or Against any of the above? Am I missing a good resonably priceds third party option? Thanks, ChrisArticle: 89823
As has been said before, it's normally safe to make sure the MTBF is (say) double the length of time you wanna be at your present company. Cheers, Syms.Article: 89824
On Tue, 27 Sep 2005 12:07:10 -0700, Symon wrote: > As has been said before, it's normally safe to make sure the MTBF is (say) > double the length of time you wanna be at your present company. > Cheers, Syms. I bet that's what the Army Core of Engineers thought when they designed the levees in New Orleans. The design spec was for a 200 year event, none of those guys expected to be around in 200 years. We'll guess what, a 200 year event is another way of saying that there was a .5% chance of that event happening in any one year. The chances of two such events in the same year is .0025 percent, sounds pretty small doesn't it. But it happened because .0025% isn't zero. When I was a physic's major the rule was that anything with a probability of less than once per 10^18 seconds could be treated as 0. 10^18 seconds is age of the universe.
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