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Never mind. I fixed it. I was sending the bits LSB first. That is incorrect. The spartan-3 requires the bits MSB first. I also had a few problems with my data transfer, since I have not implemented any sort of flow control. My system basically implements the crudest of flow control, i.e. write and read back the byte. This is insanely slow and I will be implementing other faster flow contol mechanism, now that my serial configuration system works. Thanks Antti. Yaju Nagaonkar --- Electrical and Computer Engineering Brigham Young University Provo UT 84602 yaju [(shift+2)] byu eduArticle: 96226
"Yaju Nagaonkar" <yaj_n@hotmail.com> schrieb im Newsbeitrag news:1138763966.680642.8460@g49g2000cwa.googlegroups.com... > Never mind. I fixed it. > > I was sending the bits LSB first. That is incorrect. > > The spartan-3 requires the bits MSB first. I also had a few problems > with my data transfer, since I have not implemented any sort of flow > control. My system basically implements the crudest of flow control, > i.e. write and read back the byte. This is insanely slow and I will be > implementing other faster flow contol mechanism, now that my serial > configuration system works. > > Thanks Antti. > > Yaju Nagaonkar > --- > Electrical and Computer Engineering > Brigham Young University > Provo UT 84602 > yaju [(shift+2)] byu edu > :) you did not follow my instructions full, number [3] of the advices was to use different bit order in bytes 'just in case' its a generic trouble solver if one setting that can influence the result can have two values, then check out both - even if you thing your current setting is correct. AnttiArticle: 96227
I think that you will find that Altium doesn't support 8.1 They will tell you on the forum. They are usually a rev behind for some time. Simon "Mark McDougall" <markm@vl.com.au> wrote in message news:43dffffe$0$32609$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > Nils wrote: > > > After translating the design an error message is displayed as follows: > > ERROR:Portability:90 - Command line error: Switch "-quiet" is not > > allowed > > > > Do I have to change any setting for the NGDBuild Option? > > Check out the DefaultScript_Xilinx_MAP.txt file in the System directory > of your Altium installation. I believe you can comment-out this option > with "#"... not that I've tried it myself. > > Failing that, try the DXP forums at Altium.com. > > Regards, > MarkArticle: 96228
Actually.. yes.. if you look at the output files .. you will see it detecting and replacing counters, comparators, state machines, ram etc. Simon "DJ Delorie" <dj@delorie.com> wrote in message news:xn3bj4icdg.fsf@delorie.com... > > [disclaimer: I'm a GCC developer and former Cygwin developer] > > One key difference between Cygwin and Xilinx, is that apps built with > Cygwin also *include* part of cygwin (almost verbatim) in the > resulting binary. Do bitstreams built by Xilinx tools *include* > portions of the Xilinx tools in the resulting bitstream? Can Xilinx > point to a bitstream and say "these 1000 bits are copied from our > library" ? > > A better comparison is comparing Xilinx to GCC. The GCC license > explicitly states that binaries built *with* GCC are not affected in > any way by GCC's license. > > Note that binaries built *from* GCC (derived works) are a different > story. GCC's runtime libraries have a specific clause that covers > linking; if you build with GCC, linking doesn't incur the GPL. If you > build with something else, linking does incur the GPL.Article: 96229
John Williams wrote: > Hi Antti, > > On the Linux vs windows workstation issue, we are almost evenly split > here in our group. I do everything (ISE, EDK, uClinux, ...) on a Linux > box, running CentOS3 (perfectly compatible with Xilinx tools). I do > have an old Windows laptop for running MS Office and web/email but > that's about it. > > Others in the group are running CoLinux, some on laptops, and they run > all of the tools in that environment. CentOS 3 installs just fine in > CoLinux, so the entire Xilinx tool flow can occur in a virtual Linux PC. > > One of our brainy guys hacked colinux to tunnel the parallel port, so we > run impact inside CoLinux with vanilla Xilinx drivers - it couldn't be > much easier. > > The decision to not support Windows (Cygwin) for MicroBlaze uClinux > development is a difficult one, but justified I believe by experience in > the misery of Cygwin. Cygwin is just enough like Linux to make you > think "it should work", but just different enough to make life > miserable. > > Some of these restrictions come from underlying Windows crud, like case > insensitive filesystems, poor handling of file permissions, that sort of > thing. Linux sees a difference between 'makefile' and 'Makefile' - > windows can't. While nobody would recommend overloading filenames in > this way, there's not a lot that can be done about it retrospectively > without (IMO) inordinate effort. > > It's also dreadfully slow - compile times can be on the order of 2-3 > times longer. > > Anyway, perhaps we should package up our CoLinux environment a bit > better and distribute it, it might make life a bit easier for people in > your position (and those stuck in MS Windows corporate environments). > > Regards, > > John > Hi John, It would be *very* nice to have pass-through parallel port access from CoLinux. Personally, I'd be looking at it for debugging a ColdFire running ucLinux rather than any Xilinx work, but I suspect it would be of interest to a range of embedded developers. I know the CoLinux developers have been looking at the possibilities of tunnelling serial ports, parallel ports, and USB, but have had problems with locking issues. If your "brainy guy" has working code, perhaps it could be donated to the official CoLinux project? mvh., DavidArticle: 96230
Hallo, I bought recently a notebook with only usb, firewire, ethernet and 1 pcmcia connectors. I use Parallel Cable IV. I have bought a ps/2 to usb and a parallel to usb cables. But parallel to usb seems to function only with parallel printers. Do you know a all-in-one port replicator with usb, serial and ps/2 connectors that works with Parallel Cable IV? Many Thanks MarcoArticle: 96231
Jerry Coffin wrote: > John Williams wrote: > > [ ... ] > >> Some of these restrictions come from underlying Windows crud, like case >> insensitive filesystems, poor handling of file permissions, that sort of >> thing. Linux sees a difference between 'makefile' and 'Makefile' - >> windows can't. > > I don't want to create a long off-topic thread about it, but Windows is > entirely capable of distinguishing case in file names. See the > documentation for CreateFile, specifically FILE_FLAG_POSIX_SEMANTICS, > (e.g. at > http://msdn.microsoft.com/library/default.asp?url=/library/en-us/fileio/fs/createfile.asp) > for more details. > > Given the basic nature of Cygwin, I'd have expected its implementation > of creat and/or open to include this, and just about everything else > should run on top of that, but perhaps not -- I haven't looked at its > source code recently to check. > Windows is *not* entirely capable of dealing with posix semantics properly. It can handle them to some extent, on some file systems (NTFS) on some forks of windows. It can't handle symbolic links, hard links are limited (even on NTFS), and having two files like "makefile" and "Makefile" in the same directory confuses windows. Cygwin goes to a lot of effort to hide that sort of issue. This is the main reason (AFAIK) for compilations to be slower under Cygwin than coLinux, as it takes much longer to find and open files, which is a big overhead when compiling. >> While nobody would recommend overloading filenames in >> this way, there's not a lot that can be done about it retrospectively >> without (IMO) inordinate effort. > > I'm not sure what constitutes inordinate, but I'd expect the effort to > be relatively minor. There shouldn't be many places that need changing > (quite possibly only one), and most of the software running on cygwin > expects case-sensitive file names anyway, so it doesn't seem like this > change would be likely to break much of it. >Article: 96232
<fpga_toys@yahoo.com> wrote in message news:1138753558.833731.142700@g14g2000cwa.googlegroups.com... > So, back to the question of worst case designs for supporting RC. > > What are the worst case VccInt currents that various packages will > handle? > Hi John, OK, let's work through this. First I'll pick a package, say FG672. Now, I'll choose a part, say FX20. From UG075 ThetaC = 0.4 and ThetaB = 3.8. So, best case thermal resistance from junction to case = 0.4 // 3.8 = 0.36 K/W OK, say we've selected a commercial grade part. That means our junction temperature can't exceed 85degC or 358K (from DS112). The minimum Vccint voltage is 1.14V (from DS302). Right, you asked for worst case Vccint current, which I assume means 'what's the maximum current' the package can handle. Assuming best case heatsinking, we can keep the case at c.0K with a perfect liquid Helium cooled heatsink. Therefore we can dissapate 358/0.36 = 1000W. Vccint can be 1.14V, so that's a maximum current of about 870A. Now do you see why you're asking the wrong question? ;-) Of course my example is a ridululous exaggeration, but your posting provided little to go on. You need to do a proper analysis with thermal simulation tools to get a meaningful answer, and even when you get that answer it'll be wrong! Try this bloke's book:- http://tkordyban.coolingzone.com/ There's a brief review of the book by an FPGA expert on Cambrian Design's website http://www.sonic.net/~bobperl/blogger/2006/01/book-of-month-hot-air-rises-and-heat.html HTH, Syms. p.s. I hereby release the copyright on this post to avoid any legal ramifications. ;-)Article: 96233
Dear Tom, Are you using Picoblaze to do the MAC ? Few times ago I designed the back end of a "Small C" compiler for Picoblaze, it may be usefull for you you can download from www.poderico.co.uk At moment (at work) I'm doing some reserch to see what is the cheapest way to implement a tri mode ethernet MAC What I found is: 1) if you go on www.opencores.org and you download the tv80 then one of the application is a simple GMII Interface. Now MII is half/full duplex and GMII is full duplex only, but iff you can set up your PHY to be full duplex, then it should be easy to go from GMII to MII. 2) on www.opencores.org you can download a free 10/100 MAC, why you don't use this core? (also tri mode MAC and 10 G not tested yet) 3) here http://www.sics.se/~adam/uip/index.html you can download the smallest TCP/IP stack it has been ported on... (Xilinx Ultracontroller) AVR, PIC etc. is very good, and I reccomend it... good luck, FrancescoArticle: 96234
"Symon" <symon_brewer@hotmail.com> wrote in message news:43e07882$0$15785$14726298@news.sunsite.dk... > > Now do you see why you're asking the wrong question? ;-) Of course my > example is a ridululous exaggeration, but your posting provided little to > go > I sound like Donna Chang out of Seinfeld. Of course it should be 'ridicurous'. I need coffee. Cheers, Syms.Article: 96235
Hi! I have already set the option you mentioned. Using the FPGA editor I could figure out one register that was not placed in an IOB but correcting this does not solve my problems. Best regards, S. Hagenkoetter.Article: 96236
DJ Delorie wrote: > [disclaimer: I'm a GCC developer and former Cygwin developer] > > One key difference between Cygwin and Xilinx, is that apps built with > Cygwin also *include* part of cygwin (almost verbatim) in the > resulting binary. Do bitstreams built by Xilinx tools *include* > portions of the Xilinx tools in the resulting bitstream? Can Xilinx > point to a bitstream and say "these 1000 bits are copied from our > library" ? > > A better comparison is comparing Xilinx to GCC. The GCC license > explicitly states that binaries built *with* GCC are not affected in > any way by GCC's license. That is not quite entirely true - binaries build with gcc *are* affected by gcc's licenses. In particular, patterns of assembly code generated by gcc are generated verbatim from gcc's source code (or in some cases, gcc's low-level libraries' source code), and these sections are therefore directly affected by gcc's licenses and copyrights. There main license for gcc's source code is GPL, but there are explicitly stated exceptions to remove all restrictions and copyright assignments from the generated code, precisely so that you can do as you will with gcc-generated binaries. If Xilinx' tools also have such verbatim copying through to the generated bitstreams, and they do not have such stated exceptions, then they are in a position (in my interpretation - IANAL) to claim joint copyright ownership of the bitstream. > > Note that binaries built *from* GCC (derived works) are a different > story. GCC's runtime libraries have a specific clause that covers > linking; if you build with GCC, linking doesn't incur the GPL. If you > build with something else, linking does incur the GPL.Article: 96237
"Marco T." <marc@blabla.com> schrieb im Newsbeitrag news:drpt4t$igp$1@nnrp.ngi.it... > Hallo, > I bought recently a notebook with only usb, firewire, ethernet and 1 > pcmcia connectors. > > I use Parallel Cable IV. I have bought a ps/2 to usb and a parallel to usb > cables. > > But parallel to usb seems to function only with parallel printers. > > Do you know a all-in-one port replicator with usb, serial and ps/2 > connectors that works with Parallel Cable IV? > > Many Thanks > Marco > there is no such cable and can not be, you are out of luck AnttiArticle: 96238
Antti, As you guys are really on this group/ community everyday and mutually helping each others, I was over expecting /hoping to get the suggestion fast . I really Sorry, If I had annoyed you much. We where to looking for Unix free drivers easy and fast , or such things are available. As our complete college network is of Unix and we have no Windows /Linux systems at all. Hope you get back to me with the solution on this. regardsArticle: 96239
Dears I am serching the web for te block diagram of STM 1, 4 &16 Block diagram with the component information on board , where can I get it , if you have some can you share with me for our college resources thank you in advance Satish KArticle: 96240
"TigerSatish" <satishkmys@gmail.com> wrote in message news:1138789779.480931.76450@f14g2000cwb.googlegroups.com... > Dears > > I am serching the web for te block diagram of STM 1, 4 &16 Block > diagram with the component information on board , where can I get it , > if you have some can you share with me for our college resources > > thank you in advance > Satish K > Sweeties, http://www.jdsu.com/test_and_measurement/technical_resources/technology_documents/pocket_guides/sdh_pg_opt_tm_ae_1005.pdf Cheers, Syms.Article: 96241
Don't know (I am a VHDL programmer :-), the point I was trying to make is that from a job prospective having SystemC on your CV might be slightly better than having a propriety language like Handel-C. I have no idea which one is better just that I hear more noises on SystemC than on Handel-C. Regards, Hans. www.ht-lab.com "Robin Bruce" <robin.bruce@gmail.com> wrote in message news:1138612793.879088.282550@g49g2000cwa.googlegroups.com... > > Hans wrote: >> If you have to choose a C language I would recommend you check out >> SystemC >> which might be better on your CV than Handel-C :-) > > What's so good about SystemC? :) >Article: 96242
>>: Hans wrote: >>: > If you have to choose a C language I would recommend you check out >>SystemC >>: > which might be better on your CV than Handel-C :-) >> >>: What's so good about SystemC? :) >> >>What's so good about AnythingC? >> >>I have quite strong feelings that whilst a high level language than >>Verilog/VHDL could be a real boon to FPGA development, C is far from a >>good prototype form for such a language.... > > uh, in what way is C a higher level language than VHDL anyway? C is probably not but don't forget that SystemC has all the goodies(?) of an object oriented language and support deterministic concurrency like VHDL. I like VHDL but I do recognise that for high level modelling you need to resort to these kinds of languages. Perhaps one day we get "SystemVHDL" although it seems accellera and the EDA industry have given up :-( Hans www.ht-lab.comArticle: 96243
Hi Guys I'm looking for some die area information on FPGAs. It is prooving quite difficult to find any information so if anyone has some pointers or datapoints it'd be much appreciated. Thanks!Article: 96244
I've got an app where I need to communicate between several cards in a chassis, with cable lengths up to about 15cm, and a data rate of about 1.5Gb/s, possibly increasing to about 4.5 Gb/s. At some point in the future, I may also need a cable run of a few metres. I've had a look around the Xilinx website, but it seems to be pretty short on basic beginner's selection information. Can anyone give me some advice on this lot? I can do all the necessary encoding/decoding; the problem is just the physical level: - RocketIO? Or could I use LDT/LVDS/whatever in a cheaper device? - Can I drive straight off-board from the FPGA, or do I need additional drivers/receivers? - Can I just use twisted pair from board to board? At what point do I have to go optical? Any recommendations on cabling and connectors? - What about cabling and connectors if I go for multiple channels at a lower date rate? Thanks - PaulArticle: 96245
Marco T. wrote on 01.02.2006 09:56: > Do you know a all-in-one port replicator with usb, serial and ps/2 > connectors that works with Parallel Cable IV? Haven't been able to find one of those either... The problem seems to be that iMPACT/Chipscope don't recognize the "virtual" LPT-ports those port replicators usually provide... There are parallel-port-controllers for Cardbus/PCMCIA you can plug in to get a "real" parallel port on your laptop, but I haven't tried any of those, so I can't comment on how good they are. The problem is the chipset: to get decent programming speeds, the parallel port should support 2MHz or 5MHz operation. All PCI-plugin-cards I've seen in stores lately use the same cheap controller-chip that doesn't support operation above 1MHz, so the cable will work in compatibility mode and drop down to 200kHz. Instead, I suggest buying a Platform USB cable. Gives you much less trouble in the long run, and works well on every modern machine. ... if you can afford it, that is. I think it's $150, so about double what the parallel cable costs. Plus, I'm not sure if it works under Linux, but there have been discussions about that here lately. cu, SeanArticle: 96246
Hi everybody, I get this warning under Quartus 5.1 : "Performance of this circuit may degrade because the Fitter Delay Information is not loaded" The FPGA is an ACEX EP1K30TC144-3... I don't know what this warning is and how to load the correct Fitter Delay Information File ? Thanks Best Regards.Article: 96247
Hi "LDPC" is a common platform on LDPC codes for sharing ideas, research problems, issue discussions, software and neat papers. This is first group of its kind on Google. Feel free to join here: http://groups.google.com/group/LDPC?lnk=li SBQ,MichiganArticle: 96248
I had the same problem, the answer from Altera is: This message is being incorrectly printed. It is a bug that it is printed, and it has been corrected (by removing the message) in Quartus II 5.1 SP1. Ignore the message -- your design functionality and optimization are fine. Basically our most recent FPGA families (Stratix, Stratix II, Cyclone, etc.) use a different method of storing delay information for optimization during the fitting procedure. This message says that new method is not being used. For APEX that is expected -- it uses a different method, and always will. Regards, Vaughn Betz [v b e t z (at) altera.com] <patrick.melet@dmradiocom.fr> schrieb im Newsbeitrag news:1138800040.199195.218160@z14g2000cwz.googlegroups.com... > Hi everybody, > > I get this warning under Quartus 5.1 : > "Performance of this circuit may degrade because the Fitter Delay > Information is not loaded" > > The FPGA is an ACEX EP1K30TC144-3... > > I don't know what this warning is and how to load the correct Fitter > Delay Information File ? > > Thanks > Best Regards. >Article: 96249
Hi everybody, I'm trying to implement a BPSK modulation. A sin waveform has to be generated at a given frequency (1MHz) with phase offset (binary PSK i.e. 180=B0) when transition occures on a data wire. Is there any "simple" LogiCORE with BPSK functionality available for my Xilinx Spartan-3 - Board ? My attempt would be a LUT in BRAM - but do I have to fill its content manualy ? The LUT content (e.g. 16bit) could drive a DAC. On the other hand, If I'm forced to use a external DAC, I might use a DDS (e.g. AD9834) with all BPSK functionality on chip... ?!? I'm interested in your ideas and suggestions ! Bye, BEN
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