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Hi Friends, I am working on project, where I am using CPLD operating at 5V supply. Can we direcly give the high inut voltage i.e. +5V to its input pin? Or we have to connect a resistor in between them? If so then how to select a value for +5V supply. simillarly give information for grounding the i/o pin. Regards, SonaliArticle: 96326
On Thu, 02 Feb 2006 15:42:39 +1100, Allan Herriman <allanherriman@hotmail.com> wrote: >On Wed, 01 Feb 2006 11:27:40 -0800, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>Hi, >> >>We have several products that use S3's, with a number of fpga pins >>connected to dipswitches. The dips switch to ground, and we program >>the fpga's to provide internal resistive pullups. >> >>Some small part of the time, at random, one (typically) pin will fail >>to pull up, and we have to replace the fpga to fix it. >> >>Anybody else observe this? > >I don't have the datasheet in front of me, but I believe that Xilinx >do not guarantee a minimum pullup current, merely that the pin will be >pulled up if it has no external load. > >You have an external load. > An open dipswitch is a load? Is a pad a load? >They used to guarantee a minimum of 25uA (for 3.3 or 5V parts?), but >presumably they droppped this specification because of designers >forgetting about leakage currents on their boards (or more likely, >leakage currents into tri-state outputs on other chips). > >In your case, the failure is likely to be because of leakage currents >on your board (due to insufficient cleaning) or perhaps capacitvely >coupled crosstalk (if the problem is transient in nature). > If any of these boards leaked even 1 nA, we couldn't sell them. But they don't. And it's not transient. >Moral: read and understand the datasheet, and use pullup resistors >where they are needed. I used pullup resistors; Xilinx provided them. They're in the databook and the ISE software. If they can't pull up an open circuit, they shouldn't be documented. JohnArticle: 96327
Peter - One reason to want to know the size is just to be impressed with how much stuff gets fit into such a small piece of silicon. It would be interesting to know from a historic perspective just how things have changed. How big was a 7400? a 74181? a Z80? a Xilinx 2064 (that was your 1st FPGA?)? a 16L8? etc... How much more logic is really getting crammed into the silicon today.... The desire to try to find the "actual" number of gates in an FPGA is silly. It will depend on how CLBs are used, if you can fit SRL16's into your design, etc. I think knowing the actual size is just fun from a gee-whiz perspective. John ProvidenzaArticle: 96328
It's safer and easier to analyze if you keep thing in one clock domain.
Change your code to be:
module slowclk(input clk, output slow_pulse);
reg [19:0] cnt = 29'h0;
assign slow_pulse = cnt[19];
always @(posedge clk)
if (slow_pulse)
cnt <= 'b0;
else
cnt <= cnt + 1'b1;
endmodule
In the rest of your logic:
always @(posedge clk)
if (reset)
// do reset stuff
else if (slow_pulse)
// do your 'slow' stuff
Keeping all your logic in one domain makes timing analysis easier.
Sometimes
you can't do it, but why make life complicated if you don't need to?
Note that in a power sensitive design, you may want to have a separate
slow
clock domain depending on how much logic it's got. You might save some
dynamic power. If that's not a concern, stay with one domain!
Hope this helps!
John Providenza
Article: 96329Allan Herriman wrote: > No, but you can measure the GND voltage on the die that way. That's > half the answer you want. No. But one can measure the carrier ground plane, which is half way to half of what I want :)Article: 96330
Just out of curiosity, on a failed part, if you add an external pullup resistor, does it start working again? If you look at a failed pin with a scope, what level do you see? John ProvidenzaArticle: 96331
John Larkin wrote:
> An open dipswitch is a load? Is a pad a load?
You bet! Almost all the DIP switches I've seen quote an insulation
resistance of 100Mohm minimum. 3.3V/100Mohm = 33nA max leakage.
> If any of these boards leaked even 1 nA, we couldn't sell them. But
> they don't. And it's not transient.
If the pullups are not pulling up, then you must have leakage somewhere
pulling them down.
>> Moral: read and understand the datasheet, and use pullup resistors
>> where they are needed.
>
> I used pullup resistors; Xilinx provided them. They're in the databook
> and the ISE software. If they can't pull up an open circuit, they
> shouldn't be documented.
Yes, they're in the databook, and it says:
"The optional pull-up and pull-down resistors are intended
to establish High and Low levels, respectively, at unused I/Os."
^^^^^^^^^^^^^^
Yours are not unused.
Cheers,
James
Article: 96332fpga_toys@yahoo.com wrote: > Allan Herriman wrote: > >>No, but you can measure the GND voltage on the die that way. That's >>half the answer you want. > > > No. But one can measure the carrier ground plane, which is half way to > half of what I want :) You can measure the GND on an IO ring, and that can still be usefull - that is the method used to test for crosstalk. Measuring via a sense-routed bump, will likely get you much more than 'half way' to the Core Vcc - because there are very many, very short bumps from the carrier plane, to the die, and the PCB traces/vias that go back to the regulator are included in the other leg. The powersupply controller can also do what it likes with the Sense Feedback, and Current information, so you can, (if it really matters to you), regulate a virtual point ahead of the sense point, to a stable voltage. - jgArticle: 96333
John Larkin wrote: > Hi, > > We have several products that use S3's, with a number of fpga pins > connected to dipswitches. The dips switch to ground, and we program > the fpga's to provide internal resistive pullups. > > Some small part of the time, at random, one (typically) pin will fail > to pull up, and we have to replace the fpga to fix it. > > Anybody else observe this? You could get a uA multi-meter, and check the pins that work, and compare them with the one(s) that don't. Also check the voltages. That will give you some numbers on the actual effect - It's an analog world - how weak is too weak ?. You could also create a special test pattern, that does waveform out to the DIP pins, and verify the bonding and IO are intact. Are these instant failures, or did they work once, and then fail ? ESD events dump energy into the pins, and I'm not sure if they'd bother to include the pullup fets in the energy radar - these are normally such Hi Z - but they could be a failure point for ESD. -jgArticle: 96334
There doesn't seem to be a fix for this. As a work around, I scrapped the PLB_DDR controller and DDR sim module. In its place, I used Create/Import wizard to make a PLB slave pcore that supports bursts. This pcore instantiates a large memory array and I'm now using this in simulation. It seems to work well. This solution only took a few hours to implement...I wish I done this in the first place :) NN Nju Njoroge wrote: > Hello, > > Sometime back there was a question on the comp.arch.fpga about > interfacing a PLB master pcore with the PLB DDR controller (see below > for thread or check this out: > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/72bc1bce10a2a4ac/adc03dda153a66c8?lnk=st&q=Sl_rearbitrate&rnum=1&hl=en#adc03dda153a66c8). > Recently, I have set-up a simulation environment in which my master > pcore talks a PLB DDR controller (instead of a PLB BRAM). My master > pcore issues 384 writes to the PLB DDR controller, then it reads from > the locations it wrote. My master pcore successfully completes all 384 > writes, then it starts the reads. On the 109th read, it encounters the > exact same problem as described in the posting. Anyone encountered this > issue and fixed it? I have been avoiding using PLB_DDR in simulation, > but I have some apps that use too much memory and cannot fit in the > conventional PLB BRAMs. > > Thanks, > > NNArticle: 96335
"johnp" <johnp3+nospam@probo.com> wrote in message news:1138860063.840480.174190@f14g2000cwb.googlegroups.com... > Peter - > > One reason to want to know the size is just to be impressed with how > much > stuff gets fit into such a small piece of silicon. It would be > interesting to > know from a historic perspective just how things have changed. > > How big was a 7400? a 74181? a Z80? a Xilinx 2064 (that was your 1st > FPGA?)? > a 16L8? etc... > So, I bet everyone who posts on this board has got a dead or old FPGA lying around somewhere. Although probably fewer than half of us have fuming nitric acid lying around, I also bet we've all got hammers. I'd suggest a ball pein for this particular de-encapsulation job. Is there an EULA for the parts? Cheers, Syms. ;-)Article: 96336
Hi, hope there is anybody who implemented the same: I want to use the AC97 Codec and so i'm trying to implement the Controller in Verilog. The Controller will be working on the Virtex 4 FPGA. The Codec and Controller are working with a special protocoll (AC Link Interface Serial Protocol). What's the best way to implement the controller? Does anybody have/know a sample code for the controller? Best regards, lori.Article: 96337
Antti Lukats schrieb: > Hi > > I have compiled the GNU tools for microblaze (from the 8.1 source from > Xilinx website) the win32 binaries are downloadable > > http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,12/ > the toolchain as compiled and made available is now also tested to compile working uClinix flat images so it is possible to cross compile "Out-Of-Tree" for uClinux !! really nice you type make on Windows machine, you get the binary and that will actually work on microblaze - uClinux !! so no need for CoLinux or full linux box if you are only writing userland applications for uClinux on winPC AnttiArticle: 96338
> I am working on project, where I am using CPLD operating at 5V supply. > Can we direcly give the high inut voltage i.e. +5V to its input pin? that depends on the chip you use ... usually they support 1-2 higher voltage standards as input than they deliver as output but you can only find out about that by looking to the data-sheet of *your* CPLD ... the newer parts run on lower voltage and at least recent FPGAs would not even support 5V - that is why we use some of the old FPGAs as well ... Looks like you can still buy them but recent Xilinx ISE tools do not support them any more so we have a few machines still running ISE 4! bye, MichaelArticle: 96339
"Gabor" <gabor@alacron.com> wrote an excellent post! We use a criss-cross pattern of smaller traces going between the pads and vias, four narrower traces per gnd pad and per via. Makes it look nicer around the edges of the central cluster, but works much the same as yours! Cheers, Syms.Article: 96340
Austin This all suggests that I can have an outer ring of vias in the center of a device (next to every "outer" gnd ball) and a copper pour on the top layer connecting the rest of the gnd balls with a few vias. I can then easily put some bulk decoupling right in the center of the bga as it is no longer peppered with vias. If this is the case then you have my thanks for pointing this out. By the way, you say no current flows on the inner balls but surely they carry their share of the DC current? Regards ColinArticle: 96341
"colin" <colin_toogood@yahoo.com> wrote in message news:1138876017.581870.242570@g43g2000cwa.googlegroups.com... > > This all suggests that I can have an outer ring of vias in the center > of a device (next to every "outer" gnd ball) and a copper pour on the > top layer connecting the rest of the gnd balls with a few vias. I can > then easily put some bulk decoupling right in the center of the bga as > it is no longer peppered with vias. If this is the case then you have > my thanks for pointing this out. > We leave out an occasional via to squeeze in 0805 caps in this centre region. Works well on our FG676 parts with, IIRC, a 6x6 centre. The 0805s are 2mm long so they fit nicely into the via matrix. The 0805 pads are directly aligned with the FPGA GND pads, so the via fit into the gaps. HTH, Syms.Article: 96342
VCC given to IC is +5V. so then can i directly give +5V to CPLD XC9536's logic pin which configured as input. Inside there is a multiplexer. it has one control signal. how to give '1' i.e. logic high input to CPLD. Should I need to connect resistor in between VCC and that pin. What should be its value taking account of power dessipation. Pradnya.Article: 96343
> hope there is anybody who implemented the same: > > I want to use the AC97 Codec and so i'm trying to implement the Controller in Verilog. The Controller will be working on the > Virtex 4 FPGA. The Codec and Controller are working with a special protocoll (AC Link Interface Serial Protocol). This is already done: http://www.opencores.org/projects.cgi/web/ac97/overview > > What's the best way to implement the controller? Does anybody have/know a sample code for the controller? I've used it with JOP for the following board: http://www.soc.tuwien.ac.at/courses/projects/dspio/ The controller is a little bit big, but works most of the time ;-). I have sometimes issues with the initialization, but did not investigate it. MartinArticle: 96344
Hi all,
I'm VERY sorry because I've seen much discussion about globally static
expressions and Modelsim, but I cannot find a clear answer to this
problem.
When you instantiate an entity, is quite common to negate one of the
inputs. It would look something like this:
i_my_entity : MyEntity
port map(
ena => not(nEN)
);
When we pass it to Modelsim for pre-synthesis simulation, it complains:
"The actual for formal 'ena' is not a globally static expression".
I don't look for an answer for "why it does not work". I would like to
know HOW can I make it work in a convenient way, different from
assigning not(nEN) to a signal and passing this signal to the
instantiation like this:
signal aNegation : std_logic;
...
aNegation <= not(nEN);
...
i_my_entity : MyEntity
port map(
ena => aNegation
);
Regards.
Jose.
Article: 96345
Hehehe, I answer to myself (and to those who found the same problem).
I found a possible answer here:
http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/c7a753ad13b31cc/5a955217c17a88f0?lnk=st&q=port+map+not&rnum=4&hl=en#5a955217c17a88f0
The trick seems to be enclosing the NOT like this:
i_my_entity : MyEntity
port map(
ena => "not"(nEN)
);
I'm trying now if it works, but what I can tell you for sure is that
Modelsims compiles it.
Regards.
Jose.
Article: 96346John Larkin wrote: > > Some small part of the time, at random, one (typically) pin will fail > to pull up, and we have to replace the fpga to fix it. You should be fine using the internal pullups for DIP switches, as S3 has much lower pullup values than did the older families. Although nominally for S3E, the following document has some additional info on S3 pullup and pulldowns (p60), along with other power and ESD info: www.xilinx.com/products/spartan3e/sp3e_power.pdf Things I'd check: Is there a series resistor or snubber to protect against statically charged fingers pushing the DIP switches? Is the dead pin completely dead, or does it still work if you drive the input pin high, or configure it as an output with another bitstream? Have there been any power supply sequencing, phantom power, or configuration issues observed with those boards? ( i.e., could that pin ever have acted as an output or a sneak rail path to a hard ground at some point ) Are any of the dead pins dual-purpose config pins in one of the configuration modes? BrianArticle: 96347
cs_posting@hotmail.com wrote: > Ray Andraka wrote: > > > Alternatively, you could generate ascii binary in your external > > application and past that into an array of bit_vectors directly. > > This is where I like verilog's include directive... no pasting > required. Recent versions of Synplify are very handy in that they can synthesize $readmemb/h statements to create both ROMs and initialised RAMs. Cheers, JonArticle: 96348
You can rsync the ppc linux source from rsync://source.mvista.com/linuxppc-2.4 But setting up the ppc gcc cross compiler correctly for linux kernel is not a trivial task. -TonyArticle: 96349
What about trying yourself? Frank wrote: > I put these conditions in different always and if-else-if statements, will > design compiler & ISE be smart enough to recognise them and reduce > hardware cost accordingly? > > I had a tendency to write the conditions with a wire & assign statement > e.g.: > wire cond1; assign cond1 = pop && (process == 8'h25) || kick; > but if synthesizers handles these, then it will save me some thinking. > > > > > > > always @ (posedge clk) > begin > if (pop && (process == 8'h25) || kick) > whatever <= asdf; > else if (pop1 && (process == 8'h25) || kick1) > whatever <= asdf1; > else if (pop2 && (process == 8'h25) || kick2) > whatever <= asdf2; > end > > always @ (posedge clk) > begin > if (pop && (process == 8'h25) || kick) > whatever1 <= asdf3; > else if (pop1 && (process == 8'h25) || kick1) > whatever1 <= asdf4; > else if (pop3 && (process == 8'h25) || kick3) > whatever1 <= asdf5; > end
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