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Hallo, does anyone knows when will be available? And multi-port memory controller will be included? Many Thanks MarcoArticle: 94076
"Marco T." <marcotoschi@nospam.it> schrieb im Newsbeitrag news:dpjcbm$bl7$1@nnrp.ngi.it... > Hallo, > does anyone knows when will be available? > > And multi-port memory controller will be included? > > Many Thanks > Marco It was supposed to be available around Christmas. What is defenetly not in 8.1 is DDR2 controller, dont know about multiport memcontroller AnttiArticle: 94077
hi group, we are trying to test DDR2 on a custom Virtex-4 board after implementing the desing with Xilinx MIG the Status LEDs says the DDR2 is OK, short circuit of some data pins to ground did 'inject' errors as to be expected but I am still not sure if the default FPGA test top from MIG is reliable indicator that the DDR2 memory is actually fully working does anyone have an idea how to test the DDR2 in a better way? there doesnt seem to be any reference design with DDR2 and EDK 8.1 is also not going to have DDR2 support yet AnttiArticle: 94078
Ralph, Xilinx has a Marketing and a Sales organization whose job it is to distribute and sell our products. I have neither the inclination nor the authority to create a parallel bootleg operation. I do occasionally help a personal friend, especially when I know that he will use it immediately and intensely. Very intensely. Have a happy and prosperous New Year ! PeterArticle: 94079
Jim Granville wrote:
> Do you have any Simulation benchmark indications,
Simulation performance is basically limited by the Python
interpreter. Compared to mainstream HDL simulators, I
expect a performance degradation similar to Python versus C.
Therefore, raw simulation performance is not a good argument
in favor of MyHDL at this point. Fortunately, there are
many other good reasons :-)
> and any
> simple, example 'complete' side-by-side projects ?
> By simple, I mean things like 16/24/32 bit Up/Dn/ReLoad counter,
> perhaps a DDS as well, and since it seems to have good ROM/RAM support,
> a 7 segment display counter ?
No, but it seems like a good idea to set up such a page on
the web site. Perhaps you have a pointer to Verilog/VHDL
code for such relevant designs?
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 94080Debashish, The DFS part of the DCM is more than happy to work with inputs down to 1 MHz as long as the multiplier results in an output of > 24 MHz. Do you intentionally use the reset pin? Or are you using the internal reset on startup? If you are not resetting intentionally some time after configuration is complete and the input clock is stable, it may be that the input glitches right as the part is trying to lock. Try a delayed reset to the DCM. The only way the DCM will not lock is if the input clock is glitching while it is trying to lock. Once it has tried, and failed, it will just output the 1X clock (the input) as you described until it is reset. LOCK remains low throughout. If the output is correct for a while, and LOCK does go high, and then the DFS fails, that is a different issue which is caused by excessive input jitter. Austin debashish.hota@gmail.com wrote: > Hi all, > > i am facing a problem with Xilinx DCM in DFS (not in DLL mode, in which > you need to provide a feedback clock for phase alignmen). So my DCM is > working in without feedback (internal as well as external) mode. > > I am trying to generate a 32Mhz clock from a 16Mhz input clock. Most > of the time it works fine but sometimes after giving a reset to FPGA or > reprogramming the FPGA the DCM is not able to multiply the clock to > give a 32Mhz clock and gives the same input 16Mhz clock as the output. > > But according to Xilinx DCM datasheet, in DFS mode we should be able to > multiply or divide clocks with frequency > 1 Mhz. > > So if anyone has faced any such problem or if there is any synthesis > attribute which I need to set etc then please guide me. > > Thanks in advance > Debashish >Article: 94081
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1136474338.741535.310520@g43g2000cwa.googlegroups.com... > Ralph, > Xilinx has a Marketing and a Sales organization whose job it is to > distribute and sell our products. > I have neither the inclination nor the authority to create a parallel > bootleg operation. > I do occasionally help a personal friend, especially when I know that > he will use it immediately and intensely. > Very intensely. > Have a happy and prosperous New Year ! > Peter > Thank You Peter! you really appreciate the _intense_ work with the leading edge technologies (Xilinx FPGAs) And I have rendered some real intense work from the very moment I got the sample pack ! gosh, I wanted very badly to announce today that I have on my desk and FPGA that can configure itself from removable media card (without external circuits) but unfortunatly I failed - it is not working yet, but in order to test it I did: make proto PCB with Laser Printer toner technology (6 mil traces!!!) for XC3S250e-VQ100 (I will put the pictures online soon..) XXXX, done here http://xilant.com/content/view/35/2/ that board did work immediatly, then I added MMC Card socket to the CCLK and config pins and tried to talk to the Atmel DataFlash card inserted into MMC socket, unfortunatly with no response, it is very likely that my DataFlash card is non functional as I have not tested it ever, (not before today) I can read write standard SPI flash connected as S3e config memory over JTAG no problems with that. As of today: I have tested and used for testing EVERY single Spartan3e silicon device I have in my hands (1 each of the 3 smallest members), actually I did test Impact against Spartan3e JTAG before I got any S3e (by using S3e JTAG /BSCAN emulation IP cores) - as confirmed by that testing and testing today with Impact 7.1SP4 Spartan3e-250 programming is not supported, ChipScope 7.1 does however configure all my tested Spartan3e devices (I suppose it will also program 1200 and 1600 but I have not verified that). -- Antti Lukats http://www.xilant.comArticle: 94082
Hey all, I am trying to run a script that Synplicity has provided to integrate synplify pro with the EDK. I think it is new. I can't find it on their website, but anyways... It invokes synplify_pro in batch mode after making a .prj file for each block/module/IP in the EDK project. Synplify errors out with code 768. This error is not documented anywhere. I have Synplicity working on it, but thought I would ask here... Interestingly enough, if I open the same .prj file that the scripts have made in the synplify gui, then hit run, everything works fine...actually not. I had to add the top level module in the GUI. So I thought maybe that was the problem. The top level module was not being defined for mixed-language projects. So I tweaked the script that builds the .prj files to include the "set_option top_level "module"" directive. I verified that it was doing this, but the batch mode still errors out with the 768. If I pull this new and improved .prj file (now with the top module defined) into the GUI, I can hit run and it synthesizes fine without any other intervention... Hmmmmm. I am not very familiar with synplify, so just putting it out there. PS Once this script works, it will be a great way to interate the EDK with synplify synthesis....without a lot of hassle!Article: 94083
I've known lots of ASIC designers that name their device something cool like vader or dilbert. Do people name their FPGA designs as well? Anyone know how or why this got started other than the fact that EEs are geeks? Was is driven by marketings folks, or maybe the mood the designer was in at the time of the design such as ATI's Rage? Enjoy, BeanutArticle: 94084
<fourbeans@gmail.com> schrieb im Newsbeitrag news:1136477878.639809.167900@f14g2000cwb.googlegroups.com... > I've known lots of ASIC designers that name their device something cool > like vader or dilbert. Do people name their FPGA designs as well? > Anyone know how or why this got started other than the fact that EEs > are geeks? Was is driven by marketings folks, or maybe the mood the > designer was in at the time of the design such as ATI's Rage? > > Enjoy, > Beanut > dont know about FPGAs but some Xilinx PLDs have names, see below: MONET 95108XL RENOIR 95144XL PICASSO 9536XL VAN_GOGH 9572XL -- Antti Lukats http://www.xilant.comArticle: 94085
Hi All,
Just a (hopefully) quick question regarding accessing arrays using
Modelsim FLI.
I've created an memory block signal as follows:
// std_logic literals
char * std_logicLiterals[9] = { "'U'", "'X'", "'0'", "'1'", "'Z'",
"'W'", "'L'", "'H'", "'-'" };
// Create a type representing std_logic
mtiTypeIdT std_logicType = mti_CreateEnumType(1, 9, std_logicLiterals);
// Create a std_logic_vector(15 downto 0)
mtiTypeIdT memWordType = mti_CreateArrayType(0, 15, std_logicType);
// Create a block of RAM (array) 4096 deep
mtiTypeIdT memDataType = mti_CreateArrayType(0, 4095, memWordType);
// Create Memory Data
memData = mti_CreateSignal("memData", region, memDataType);
I want to be able to drive and fetch values from this signal.
The functions available to so this seem to want to work with the signal
array as a whole, rather than just accessing single words.
mti_GetArraySignalValue() looks like it will only fetch the whole block.
As the memory signal array is 16x4096, this is quite a lot of memory to
allocate and deallocate in a process function.
So, is there a way to both get and drive a single word value without
having to fetch and write the whole block of memory.
Thanks
Andy
--
Dr. Andrew Greensted Department of Electronics
Bio-Inspired Engineering University of York, YO10 5DD, UK
Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk
Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112
Article: 94086Hi It makes me weird. Till now I thought that on all I/O's is highZ while V2 is configured. But it just before starting to work on some I/O's (I've checked only five or six of all of them) there is logic '1'. I don't know what to think about it. Device: xc2v2000fg676 -4C, Configure: Slave SelectMap by microcontroller. Do you have an idea, is it normal and why? best regards Jerzy GburArticle: 94087
jerzy.gbur@gmail.com wrote: > Hi > It makes me weird. Till now I thought that on all I/O's is highZ while > V2 is configured. > But it just before starting to work on some I/O's (I've checked only > five or six of all of them) there is logic '1'. > I don't know what to think about it. > > Device: xc2v2000fg676 -4C, > Configure: Slave SelectMap by microcontroller. > > Do you have an idea, is it normal and why? > > best regards > Jerzy Gbur > How do you mean checked, with a scope? Are these pins connected to anything else on the board? Could be that there's a pull-up somewhere, incluing a weak pull-up within the FPGA. -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112Article: 94088
Look at the definition of the HSWAP_EN pin and how you have it strapped in your design. <jerzy.gbur@gmail.com> wrote in message news:1136479208.482562.186020@o13g2000cwo.googlegroups.com... > Hi > It makes me weird. Till now I thought that on all I/O's is highZ while > V2 is configured. > But it just before starting to work on some I/O's (I've checked only > five or six of all of them) there is logic '1'. > I don't know what to think about it. > > Device: xc2v2000fg676 -4C, > Configure: Slave SelectMap by microcontroller. > > Do you have an idea, is it normal and why? > > best regards > Jerzy Gbur >Article: 94089
In DS031 it says:- "Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M2, M1 and M0 are dedicated pins. An additional pin, HSWAP_EN is used in conjunction with the mode pins to select whether user I/O pins have pull-ups during configuration." Of course, you know this already because you read the datasheet cover to cover before posting! ;-) HTH, Syms. <jerzy.gbur@gmail.com> wrote in message news:1136479208.482562.186020@o13g2000cwo.googlegroups.com... > Hi > It makes me weird. Till now I thought that on all I/O's is highZ while > V2 is configured. > But it just before starting to work on some I/O's (I've checked only > five or six of all of them) there is logic '1'. > I don't know what to think about it. > > Device: xc2v2000fg676 -4C, > Configure: Slave SelectMap by microcontroller. > > Do you have an idea, is it normal and why? > > best regards > Jerzy Gbur >Article: 94090
Often an FPGA or ASIC is a project on its own rather than simply part of another project. Projects get names to have some identity rather than "that thing John's working on... no the other thing." If the function can describe what the device is for (e.g., the video processor in the PDX1800 follow-on product) you don't want to tip the inductry that you're using cutting edge FPGA technology in a next-generation product due to hit the market in 2Q06. Code names help keep things a little more secure. <fourbeans@gmail.com> wrote in message news:1136477878.639809.167900@f14g2000cwb.googlegroups.com... > I've known lots of ASIC designers that name their device something cool > like vader or dilbert. Do people name their FPGA designs as well? > Anyone know how or why this got started other than the fact that EEs > are geeks? Was is driven by marketings folks, or maybe the mood the > designer was in at the time of the design such as ATI's Rage? > > Enjoy, > Beanut >Article: 94091
Jerzy, if you check with a high-impedance oscillosope probe, you cannot detect the difference between an active High (10 Ohm) or 3-stated with a weak pull-up (multi-kilohms). To see the difference, load the pin with a kilohm to ground... Peter Alfke jerzy.gbur@gmail.com wrote: > Hi > It makes me weird. Till now I thought that on all I/O's is highZ while > V2 is configured. > But it just before starting to work on some I/O's (I've checked only > five or six of all of them) there is logic '1'. > I don't know what to think about it. > > Device: xc2v2000fg676 -4C, > Configure: Slave SelectMap by microcontroller. > > Do you have an idea, is it normal and why? > > best regards > Jerzy GburArticle: 94092
Beanut, Typically companies (and government agencies) have provided names for their internal projects. This seems to be fairly common. Mercury, Gemini, Apollo, etc.... I have heard some say that this is meant to keep secret/confuse competition, as saying you are working on 'Pinatubo' gives very little information as to what you are really working on. Personally, I like to think that by calling it something innocuous, it leaves room for Marketing to decide what they really want to call their new product. Artists, mountains, novels, minerals, politicians, movies, anything is fair game. I used titles of novels for one string of releases. It was actually quite amusing to send out the "Dr. Faustus" release, followed by the "Paradise Lost" release. AustinArticle: 94093
hitsx@hit.edu.cn wrote: > Now I want to design a RISC cpu for study the cpu architecture, and I > am puzzled about how to start? Try reading about the DLX and looking at the code for the OpenRISC. > Whether should I start with a RISC 16 bit cpu, including just serveral > instructions like add, substract, multiply and divide? This is usually a good starting point. > And I wonder whether I should introduce the pipeline and superscalar > into the architecture? It's not really a RISC if it's not pipelined. I'd save superscalar for another day, if this is your first effort. Cheers, JonArticle: 94094
Subhasri krishnan wrote: > Hi all, > What should I read to find out about timing constraints in detail? not > just syntax but some theory. and how are the constrains interpreted? is > the logic routed according to timing constraints? What if I use more > than 90% of the available resources? > > Also I am using an async fifo in my design. Is it necessary to use > timing constraints for this? > > Thanks in advance > Subhasri > The best timing constraint document I have read is ftp://ftp.xilinx.com/pub/documentation/misc/timingcsts6i.pdf 187 pages of the stuff. KunalArticle: 94095
On 5 Jan 2006 08:17:58 -0800, fourbeans@gmail.com wrote: >I've known lots of ASIC designers that name their device something cool >like vader or dilbert. Do people name their FPGA designs as well? >Anyone know how or why this got started other than the fact that EEs >are geeks? Was is driven by marketings folks, or maybe the mood the >designer was in at the time of the design such as ATI's Rage? ASICs are like your children, it takes such a long and ardious time to make them and once you tape them out you can really never get rid of them and you can only fix their small mistakes by making small minor changes without touching their base. You just learn their quirks, make changes in other pieces of their environment (fix firmware, change pcb, etc) to accomodate them. That's why people name their ASICs. FPGAs are at most like a pet you buy for one of your children. If it becomes too much of a hassle, you just return it or flush it down the drain and get another one. That's why you don't find named FPGA designs too often.Article: 94096
Hi Rob, Unfortunately I cannot help answer your question, but felt I should respond because I am interested in knowing the answer to the "clock skew" question as well. I have been attempting to find an answer using the Xilinx Timing Analyzer, with no answer so far. Have you had any luck? Best, Brendan "Rob" <robnstef@frontiernet.net> wrote in message news:fj%uf.2788$OU3.1435@news01.roc.ny... > Hello. > > How can I see what the the clock skew is between a set of register? The > clock is an output of a DCM. Also, how can I force the PAR to maintain a > certain timing spec? > > Thanks, > Rob > >Article: 94097
> What should I read to find out about timing constraints in detail? not > just syntax but some theory. and how are the constrains interpreted? If you are just begining, I would suggest going to the Constraints Guide. Help - Online Documentation - go to page 3 and Constraints Guide - then go to Timing Constraints Strategies - which is page 131 of 888 in my system. I also think that "Understanding Setup and Hold Times" by Claude Gaschet Xilinx XL35-40.PDF is a nicely written article. If you can't find it on Google or at www.xilinx.com let me know. > Also I am using an async fifo in my design. Is it necessary to use > timing constraints for this? Using an async fifo is what constraints are all about. You will have two "clock domains", probably one writting and one reading. That will mean at least four lines of UCF file code, two for each domain, sort of like this: NET "clock1_in" TNM_NET = "clock1_in"; TIMESPEC "TS_clock1_in" = PERIOD "clock1_in" 20 ns HIGH 10; NET "clock2_in" TNM_NET = "clock2_in"; TIMESPEC "TS_clock2_in" = PERIOD "clock2_in" 5 ns HIGH 2.5; Then you may want an OFFSET to address the setup time for incoming data: OFFSET = IN 1 ns BEFORE "clock2_in"; This will move fabric registers toward the inputs. Good luck, Brad Smallridge brad at aivision.comArticle: 94098
Using the internal 50 MHz clock of the Spartan 3 board, my design synthesized to a speed of 200MHz . If I want my design to synthesize using a new clock( say 4 times the clock freq provided by the board(200MHz)), what should I do? I instantiated the BUFG_DFS_SUBM in my design, which does produce a 200MHz clkfx signal, after a time lag of 950ns. Could you tell me what the LOCK signal is? What is it role and how to use it? Now in my design, in place of using the "clk" of the board, if I use the "clkfx" that I just generated, will my design now synthesize to a higher speed? or is there something else I need to do? Also what is the Xilinx Clocking Wizard? When is it used..what purpose? What does the. xaw file do?Article: 94099
"Antti Lukats" <antti@openchip.org> wrote in message news:dpigr1$dms$01$1@news.t-online.com... > "gja" <gja@hotmail.com> schrieb im Newsbeitrag > news:nq%uf.3818$DY3.3339@fe09.lga... > > I'm looking for some suggestions as to what else to look at to fix this > > problem: > > > > Using a Virtex II xc2v40 and xcf02s prom connected in master serial mode. > > JTAG is also implemented. We've built around 50 of these boards without > > this problem so I believe it's just this particular board. It > > intermittently doesn't configure on power up. > > > > A power chip holds INIT_B low until 3.3v is 3v to delay configuration, not > > really needed since power ramps up in around 5ms. When it fails, I see on > > a scope that INIT_B never goes high after power is up and PROG is high. > > PROG is pulled up to 3.3v thru 4.75k. When it works, INIT_B goes high > > within 5ms of PROG going high. > > > > As a test, I connected PROG to GND with a wire and then powered up the > > board. After say 5 secs, I disconnected GND, and sometimes INIT_B would > > go high as expected, But sometimes it would remain low. If it went high, I > > could pulse PROG low and INIT_B would work as expected everytime. > > > > When the fpga is in its nonworking state, it doesn't respond on the JTAG > > port either. > > > > I lifted the prom pin and the power chip connected to INIT_B to verify > > that when it fails, it's the fpga that is holding INIT_B low and not the > > other chips. > > > > Any ideas on what else to look at? > > > if INIT_B does not go high there isnt much too look at - init output and its > corresponding bit in IR capture readback and in configuration status > register does indicate "internal housecleaning complete" if it remains Low > then FPGA is basic internal failure mode > > only power supply and PROG_B can possible prevent the INIT_B from going low > (or malfunctionining FPGA) > > if JTAG works at all you can check the init_b bit in IR capture, if JTAG > doesnt work at all, then I assume bad FPGA or bad power supply > > -- > Antti Lukats > http://www.xilant.com > > Do you think it's a fair test to gnd the PROG_B signal and release it about 10secs after power is on? Holding PROG_B low basically holds off configuration also? Does that negate the powerup requirements?
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