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cdsmith69@gmail.com wrote: >>What did you use to design the 16V8/22V10's ? >>Why not use ABEL, for the 9536 ? >>-jg > > > Most commonly was ICT pals with their WinPlace software, but I did use > some AMD pals and their ABEL software, way back in about 1995. > > Neither of these programs will work for the 9536. You do realize Xilinx has ABEL flows for their CPLDs ? [ Scan for .ABL files, in their examples directories] You'll find the learning curve much shorter, and ABEL is fine at the smaller end of the scale.Article: 94126
No, I haven't. I know how to do it with Quartus (frankly, I think they do a better overall job with timing constraints). All I want to do is get the fanout timing from an output of a DCM--why is so difficult? "Brendan Illingworth" <billingworth@electrascan.com> wrote in message news:_8idnY4IAKE4yyDeRVn-pQ@comcast.com... > Hi Rob, > > Unfortunately I cannot help answer your question, but felt I should > respond > because I am interested in knowing the answer to the "clock skew" question > as well. I have been attempting to find an answer using the Xilinx Timing > Analyzer, with no answer so far. Have you had any luck? > > Best, > Brendan > > > "Rob" <robnstef@frontiernet.net> wrote in message > news:fj%uf.2788$OU3.1435@news01.roc.ny... >> Hello. >> >> How can I see what the the clock skew is between a set of register? The >> clock is an output of a DCM. Also, how can I force the PAR to maintain a >> certain timing spec? >> >> Thanks, >> Rob >> >> > >Article: 94127
Definitely Altera. "Thomas Entner" <aon.912710880@aon.at> wrote in message news:43bc292b$0$16891$91cee783@newsreader01.highway.telekom.at... >> I'm looking at doing some basic CPLD designs via Schematic Entry. Who >> has easier to learn/use schematic entry software, Xilinx or Altera? > > Altera > > Regards, > > Thomas >Article: 94128
troy.scott@latticesemi.com wrote: > In the current release (ispLEVER v5.1) the MachXO device family does > require a Verilog HDL or VHDL synthesis front-end like Precision RTL or > Synplify. You can use the schematic editor, however, there's currently > no library for gate-level design so it's best used as a block-diagram > editor. In the design flow the schematic editor produces a structural > model that's read by logic synthesis. I use it today with the latest > FPGA families (including XO):to organize RTL modules or those modules > generated from IPexpress the module/IP core manager. > > Meanwhile another option for someone who's trying to migrate a > 74xx-class design is a 3rd party EDA schematic front-end like Aldec, > Altium (Protel), or Orcad which can also generate EDIF 2 0 0 or > structural HDL you can import into FPGA tools. Altium in particular is > focused on making this "board-level" design style easy. > > Troy Scott > Lattice Semiconductor TME Thanks Troy - you might get them to change the WEB page, so someone who takes what it says, at face value, is not misled. i.e. make it clear that whilst MachXO is called a CPLD for sales, from a TOOL chain viewpoint, it is a FPGA : Presently, ABEL flow _excludes_ MachXO, but includes all "product term" CPLDs Do you know if Lattice plan to support ABEL flows for MachXO, to better tap into the CPLD user base ? -jgArticle: 94129
On Wed, 4 Jan 2006 13:16:44 +0000 (UTC), "Bill Davy" <Bill@SynectixLtd.com> wrote: >"Totally_Lost" <air_bits@yahoo.com> wrote in message >news:1136368133.136751.34120@g44g2000cwa.googlegroups.com... >> ok, sorry for the brief break ... in 1980 Wang was chewing up the >... >> Replacing over a decade of selectric typewriters, and several years of > >And how many had an 8051 to interface a Selectric to a Centrnics port as a >printer? I actually did my own design from scratch, complete with all the careful testing with an oscilloscope of the reed relay signals in the IBM electronic model 85 I was working on, using an 8051 to interface it to a serial port. Included both hardware and software handshaking and buffers to handle the slow output rate of the typewriter. Worked first time, too!! Used it for years as my printer, capable of handling multi-part forms when needed. I can't imagine how many folks did Selectric conversions -- it was because of them (and my inability at the time to find a design specifically for the electronic series that followed it) that I tried my hand at the unit I owned. I knew I should be able to get it working and, sure enough, I did. That was my very first design from scratch of any significance in electronics. I remember it well. JonArticle: 94130
Hi Patrik, I'm sorry I cannot offer any advice on your question, however I can tell you that marking a request as "URGENT" is the surest way to have it ignored. As the old saying goes, "A lack of planning on your part does not constitute an emergency on mine.". A potential footnote to that is, "(unless you're paying)". Regards, John Patrik Eriksson wrote: > In my design I use the block sync and the 64B/66B descrambler and > bypasses the 64B/66B decoder in the Rx direction of the MGT. > > In the Tx direction I bypass the 64B/66B encoding and applies the > sync header in the fabric i/f. I use the gearbox and the scrambler. > > I want to use the Rx buffer clock correction function and I have defined > a 66-bits pattern used for this purpose as follows: 0x01_5555000000000000 > > My problem is to get a correct match of the pattern. In my simulation > the pattern is matched independent of the sync header, i.e. both 01 and > 10 matches. I have configured the MGT as follows: > > CLK_COR_SEQ_1_1 = "11001010101" > CLK_COR_SEQ_1_2 = "10001010101" > CLK_COR_SEQ_1_3 = "10000000000" > CLK_COR_SEQ_1_4 = "10000000000" > CLK_COR_SEQ_1_MASK = "0000" > CLK_COR_SEQ_2_1 = "10000000000" > CLK_COR_SEQ_2_2 = "10000000000" > CLK_COR_SEQ_2_3 = "10000000000" > CLK_COR_SEQ_2_4 = "10000000000" > CLK_COR_SEQ_2_MASK = "0000" > CLK_CORRECT_USE = true > CLK_COR_MAX_LAT = 48 -- According to UG035 v1.5 table 1-5 > CLK_COR_MIN_LAT = 32 -- According to UG035 v1.5 table 1-5 > CLK_COR_SEQ_2_USE = false > > I have also tried to use the opposite syncheader value for my sequence > (10) but it still fails. > > Is it possible to say which serial bits that are matched with which bits > of the generics/attributes debending of the diffrent configurations? It > should be some kind of mux that connects the bits to the comparator logic. > > Looking forward for Your answers. > > Best Regards > Patrik Eriksson > ------ > Patrik ErikssonArticle: 94131
I have been playing around with a script provided by Synplicity to synthesize EDK projects using synplify. It basically replaces the directive in the makefile to point all synthesis actions to synplify. Actually, everything is synthesized in XST first, but the synplicity script deletes the ouput of that synthesis and uses synplify. So Synplify synthesizes the cores (all except the encrypted microblaze) and you end up with a bunch of ngc files for the cores and a system.edn file. All this works fine. Once xflow is invoked, there are errors before it completes. I believe the first thing that xflow invokes is NGDBuild.exe. This should read in all the ngc files and the system.edn and then build a master netlist, right? Well it reports 4 errors. The following is one of them: ERROR:NgdBuild:604 - logical block 'tx_data_control/tx_data_control/USER_LOGIC_I' with type 'user_logic_work_tx_data_control_wrapper_structure_0' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'user_logic_work_tx_data_control_wrapper_structure_0' is not supported in target 'spartan3'. I have searched Xilinx' website and this forum, and there are reports of this problem, but none of the fixes seem to work...or even seem appropriate for what I am seeing. I DO NOT know if ngdbuild is outputting the first 4 errors it gets and then quits or if there are actually only 4 cores that are having the problem. They are all custom IP cores that are attached to the OPB bus. I have other cores that are attached to the bus too, but I don't get errors with them. So unless ngdbuild is only showing the 1st 4 errors, there is a problem with these 4 cores, but I can't figure it out. The only thing I can think of is that there may be a limit to the number of characters allowed in the "type" field, but that doesn't seem right. Any help would be appreciated!Article: 94132
On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >Mike Treseler <mike_treseler@comcast.net> wrote: >> Austin Lesea wrote: > >> > I would invest my time in learning a HDL: VHDL or Verilog. > >> Good advice, but allow several months. > >But schematic entry oftem leads to non-registered designs, where you should >allow several month of debugging too... Why? Logic is logic. We do lots of complex designs, state machines and all, in schematic form, and they come up in days or hours. JohnArticle: 94133
Hello, I have to design a board with a PCI interface which shall be compliant with a larg range of PCI versions ! 3.3V 32bits / 33Mhz 5V 32bits / 33Mhz 3.3V 64 bits / 66 Mhz The board should use V2P xilinx FPGA so what bothers me is the 3.3V and 5V compliance. Is there a simple solution to achieve this ? Thanks. Stéphane.Article: 94134
I am starting a new design and would like to connect the Virtex-4 PowerPC to another external device with a PCI bus. The IP cores I find on the Xilinx web site seem to suggest a connection from the PLB to the OPB though a bridge, and then another bridge from the OPB to the PCI bus. Is this not a major performance bottleneck? Why not connect the PCI to the PLB directly? In the IBM/AMCC processors that I have worked with, the 405GP and 440GX, the PCI (and PCI-X) bridges are connected to the PLB, not the OPB. The OPB in these designs is used only for low speed peripherals. I am about to negotiate an agreement with Xilinx to purchase of a number of IP cores, but I am not clear on all that I would need to implement a complete PCI solution. Can anyone advise? The device I am attaching the Virtex-4 to is an AMCC PPC440GX with a PCI / PCI-X interface. No other devices on this bus. I am still not sure if I want to make it a 32 or 64 bit connection, extra bandwidth is good but the extra pin requirements and PCB routing challenges are bad. Realistically, what kind of performance can I expect? Is it at all realistic to except the external device to be able to receive full rate data from 2 GMACs inside the Xilinx? What about data transfer speed (block copy) from the external device to a 64 bit DDR memory controller on the PLB? Tom.Article: 94135
Yes, using external I/O buffer for the I/O of the bus and connecting them on the V/IO of the PCI bus. The only compliance problem might be the clock since you must have a single load on it. Using a zero delay buffer 5 v compliant that should be possible.Article: 94136
John Larkin <jjlarkin@highnotlandthistechnologypart.com> wrote: > On Wed, 4 Jan 2006 22:08:26 +0000 (UTC), Uwe Bonnes > <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: > >Mike Treseler <mike_treseler@comcast.net> wrote: > >> Austin Lesea wrote: > > > >> > I would invest my time in learning a HDL: VHDL or Verilog. > > > >> Good advice, but allow several months. > > > >But schematic entry oftem leads to non-registered designs, where you should > >allow several month of debugging too... > Why? Logic is logic. We do lots of complex designs, state machines and > all, in schematic form, and they come up in days or hours. If you do registered designs and don't relay on some function having some definite delay, things will be fine. However many TTL designs are created different... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 94137
Hi Andrew,
It has been a few years since I looked at the FLI but wouldn't it be easier
to just allocate an integer array using mti_malloc, read and write from the
array as normal followed by converting the integers to/from signals?
Example,
Allocate memory:
static unsigned int *buffer;
if ((buffer=(unsigned int *)mti_Malloc(MAXCOOR*sizeof(unsigned int)))==NULL)
{
mti_PrintMessage("*** MTI Memory Allocation failure ***\n");
mti_FatalError(); // Do not continue
}
Convert signal before writing to array:
x=conv_std_logic_vector(ip->x);
buffer[i++]=x;
// Convert std_logic_vector into an integer
mtiUInt32T conv_std_logic_vector(mtiSignalIdT stdvec)
{
mtiSignalIdT * elem_list;
mtiTypeIdT sigtype;
mtiInt32T i,num_elems;
mtiUInt32T retvalue,shift;
sigtype = mti_GetSignalType(stdvec); // signal type
num_elems = mti_TickLength(sigtype); // Get number of elements
elem_list = mti_GetSignalSubelements(stdvec, 0);
shift=(mtiUInt32T) pow(2.0,(double)num_elems-1);// start position
retvalue=0;
for (i=0; i < num_elems; i++ ) {
if (mti_GetSignalValue(elem_list[i])==3) {
retvalue=retvalue+shift;
}
shift=shift>>1;
}
mti_VsimFree(elem_list);
return(retvalue);
}
Hans
www.ht-lab.com
"Andrew Greensted" <ajg112@ohm.york.ac.uk> wrote in message
news:dpjh7q$iv6$1@pump1.york.ac.uk...
> Hi All,
>
> Just a (hopefully) quick question regarding accessing arrays using
> Modelsim FLI.
>
> I've created an memory block signal as follows:
>
> // std_logic literals
> char * std_logicLiterals[9] = { "'U'", "'X'", "'0'", "'1'", "'Z'", "'W'",
> "'L'", "'H'", "'-'" };
>
> // Create a type representing std_logic
> mtiTypeIdT std_logicType = mti_CreateEnumType(1, 9, std_logicLiterals);
>
> // Create a std_logic_vector(15 downto 0)
> mtiTypeIdT memWordType = mti_CreateArrayType(0, 15, std_logicType);
>
> // Create a block of RAM (array) 4096 deep
> mtiTypeIdT memDataType = mti_CreateArrayType(0, 4095, memWordType);
>
> // Create Memory Data
> memData = mti_CreateSignal("memData", region, memDataType);
>
> I want to be able to drive and fetch values from this signal.
> The functions available to so this seem to want to work with the signal
> array as a whole, rather than just accessing single words.
>
> mti_GetArraySignalValue() looks like it will only fetch the whole block.
>
> As the memory signal array is 16x4096, this is quite a lot of memory to
> allocate and deallocate in a process function.
>
> So, is there a way to both get and drive a single word value without
> having to fetch and write the whole block of memory.
>
> Thanks
> Andy
>
> --
> Dr. Andrew Greensted Department of Electronics
> Bio-Inspired Engineering University of York, YO10 5DD, UK
>
> Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk
> Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112
Article: 94138Hans wrote: > It has been a few years since I looked at the FLI but wouldn't it be easier > to just allocate an integer array using mti_malloc, read and write from the > array as normal followed by converting the integers to/from signals? > :-) That is exactly what I had been doing... The problem is, I wanted to create the memory block as an actual signal so that I could access its contents with modelsim as if it was a standard VHDL module. At some point I'll be replacing the FLI block with actual VHDL, so I wanted the two to look (from modelsim's perspective) the same. Doing it this way would also means I can more easily display memory content on the modelsim wave and list windows. Thanks for the suggestion though. Andy -- Dr. Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, YO10 5DD, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112Article: 94139
Hi All, I want some guidence for encoding schemes used in ethernet I know that for gigabit ethernet mostly the 8b10b encoding scheme is used and also I have heard about 64b/66b scheme. which one is actually used....? If I need to send my data on ethernet which one I should use and while receiving any data, is there any method for detecting that the receiving data is coded in which scheme...? Thanks & Regards KedarArticle: 94140
Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > Yes, using external I/O buffer for the I/O of the bus and connecting > them on the V/IO of the PCI bus. No. We had that on this newsgroup on a regular basis. The pci standard states explicitly that there may be no discrete components connected to the signals. You can not be fully compliant to 5V PCI with a V2P. It is general consensus to ignore that rule but you better not use the PCI logo to avoid cease and desist letters of your competitors. Kolja SulimaArticle: 94141
Xapp462 (bottom page 59) says "The DFS clock outputs, CLKFX and CLKFX180, remove some amount of incoming clock jitter...." but I cant find any numbers.. Does anyone know?Article: 94142
Hi, The encoding is handled by the PHY. Are you implementing the PHY on an Fpga? AlanArticle: 94143
well, by 'you' I meant the organisation not the individual; I think this forum is a great place for vendors to get some feedback... Now, I stop it: I'll just pick my VISA and buy one of the usual dev kits... it's not a matter of free stuff or not: Tiny is beautiful, and I'm sure that the sample pack can give a lot of ideas to embed FPGAs everywhere. Cheers, Ralph.Article: 94144
Brendan, Brendan Illingworth wrote: > I need to know the expected signal skew inside the XC2VP30 (FF1152 package) > for the various types of routing resources. Eg. the trace delay in units of > time/distance. Has anyone encounter this spec? Routing delays are more a function how many switch boxes you cross, than the length of the wire, use timing analyser to calculate delays (or FPGA editor) ie. a segmented route of the same length with a long line has a significantly different delay. > > Additionally, do any of tools provided with ISE 7.1 allow for simulation of > an array of synchronous F/F's with all inputs tied to the same net such that > SOME F/F's will capture a logic '1' while others will capture a '0' due to > the propagation delay of the route? if you drive all the FFs from the same source you'll add more skew due to increased fanout. > > Have fun, AurashArticle: 94145
You can use bus switches to limit voltage allowing 5V operation. Technically by PCI spec they aren't allowed but we do on our development boards as do a number of our competitors and have never seen a problem. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost FPGA Development Board. http://www.enterpoint.co.uk "sjulhes" <t@aol.fr> wrote in message news:43be196a$0$7176$636a15ce@news.free.fr... > Hello, > > I have to design a board with a PCI interface which shall be compliant > with > a larg range of PCI versions ! > 3.3V 32bits / 33Mhz > 5V 32bits / 33Mhz > 3.3V 64 bits / 66 Mhz > > The board should use V2P xilinx FPGA so what bothers me is the 3.3V and 5V > compliance. > Is there a simple solution to achieve this ? > > Thanks. > > Stéphane. > > >Article: 94146
Why don't you use a Gigabit PHY (for example Marvell 88E1111) ? Then you only have to care about the interface FPGA <--> PHY. Rgds Andr=E9Article: 94147
On Fri, 06 Jan 2006 10:50:11 +0100, Kolja Sulimma <news@sulimma.de> wrote: >Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: >> Yes, using external I/O buffer for the I/O of the bus and connecting >> them on the V/IO of the PCI bus. >No. We had that on this newsgroup on a regular basis. >The pci standard states explicitly that there may be no discrete >components connected to the signals. What's their definition of a discrete component..? I suspect they are talking about resistors etc. Does it actually say that each signal must go to a single chip ? If not, then I see no problems with signals going to different (buffer) chips.Article: 94148
My understanding is that you can only load once each line that's it ...Article: 94149
On Sat, 24 Dec 2005 09:24:21 -0500, "Chuck F. " <cbfalconer@yahoo.com> wrote: >Anton Erasmus wrote: >> "Monte Dalrymple" <monted@systemyde.com> wrote: >> >> [snipped] >> >>> I doubt that those schematics survive though, as they predated >>> the era of document control at Zilog. >> >> I often wonder how many products never got developed further >> because of lost documents at companies. Also how many companies >> can truly recover if somwhow they had to start from scratch with >> only their documentation in config control. > >Believe it or not, adequate documentation and control predates the >use of computers by a considerable margin. It involved such things >as file cabinets with suitably dimensioned drawers to hold original >drawings, prepared on paper and mylar, sometimes with India Ink, >the use of Ozalid machines, proper parts list, etc. Interestingly, the classic drawing cabinet, to hold drawings hanging from four fingers for easy access, is credited by some sources to ... Charles Babbage. - Brian
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Compare FPGA features and resources
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