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Bryan Hackney wrote: > bill.sloman@ieee.org wrote: > > Bryan Hackney wrote: > > > >>bill.sloman@ieee.org wrote: > >> > >>>Bryan Hackney wrote: > >>> > >>> > >>>>SioL wrote: > >>>> > >>>> > >>>>>"Lanarcam" <lanarcam1@yahoo.fr> wrote in message news:1137771805.545861.31220@g49g2000cwa.googlegroups.com... > >>>>> > >>>>> > >>>>> > >>>>>>Bryan Hackney wrote: > >>>>>> > >>>>>> > >>>>>> > >>>>>>>And, um, what has Africa ever contributed to the world? > >>>>>> > >>>>>>No idea? > >>>>> > >>>>> > >>>>>Homo Sapiens? > >>>>> > >>>>>Supposedly the first man or woman came from there. > >>>>> > >>>> > >>>>That's not certain, > >>> > >>> > >>>Try looking at the evidence from the DNA, dummy. > >> > >>Make some sense, asshole. > > > > > > A response that emphasises your lack of education, anus. > > > > > >>>>but we do know where Newton, Galileo and Chebyshev are from. > >>> > >>> > >>>Not really - we haven't got DNA from any of them, but we can be pretty > >>>confident that their ancestors came out of Africa. > >>> > >> > >>Are you saying that an African's DNA is somehow a precursor to yours? > > > > > > And yours, and everybody else's. Those Africans lived in Africa more > > than 100,000 years ago - how much more is subject to debate. > > > > > >>Are you a Nazi? > > > > > > No. Check with Jim Thompson. He calls me a socialist - and is ignorant > > enough to think that he is calling me communist by implication. > > > > > >>I stated obvious facts about African culture, and you start talking about DNA. > > > > > > Odd, that. You produce a few idiotic statements about human culture - > > the sort of racist rubbish that the Nazi's used to peddle - then extend > > that to make an absurd claim about Africa in general, which I happily > > sent up, and now you think "I" might be a Nazi. > > > > Go away and learn something. Darwin's Law of Evolution might be a good > > place to start. > > > > You are an over-the-top fool. Not a judgment which anyone is going to take seriously. Try posting anonymously in future - that way your opinions will be taken more seriously. > I had no idea. Didn't stop you running off at the mouth. > I never would have responded. 100% hindsight. Try to keep that idea in mind, all the same - it came a bit late, but the basic idea is sound. -- Bill Sloman, NijmegenArticle: 95401
Brian Davis wrote: > Symon wrote: > > > > As penance, I'll still get the dessert AND write a little article about it > > for the FAQ. (The fpga-org.com FAQ that is!) > > > Probably a bit OT for comp.arch.fpga; might I suggest instead the > FAQ at schwarzwaldkirschtortemitschlagsahne.org > > Brian For the hard of German, I make that "Black Forest Cherry Cake with Whipped Cream". Incredibly, the domain has not yet been snapped up... RobinArticle: 95402
<bill.sloman@ieee.org> wrote in message news:1137821560.131641.325030@g44g2000cwa.googlegroups.com... > > Jim Thompson wrote: > > On Fri, 20 Jan 2006 10:04:52 -0800, Don Bowey <dbowey@comcast.net> > > wrote: > > > > >On 1/20/06 8:58 AM, in article > > >1137776297.373102.256560@f14g2000cwb.googlegroups.com, "amyler@eircom.net" > > ><amyler@eircom.net> wrote: > > > > > >> If you were a european I'd credit you with subtle use of irony.... > > >> > > >> But I'm sure you're a nice guy really :-) > > >> > > > > > >No, he isn't. > > > > > [snip] > > >Don > > > > You don't think I'm a nice guy? Why? > > Neither nice nor all that full of insight. > > I wonder how he is doing with his scheme to report me to the current > version of the committee for Un-American activities ... No black > helicopters so far, and the Australian security services didn't bother > searching my suitcases when I entered the country a week or so ago. > > -- > Bill Sloman, Nijmegen > No search, but I'm sure you were asked if you were carrying any fresh fruit.Article: 95403
In article <YVVAf.14717$Jd.13902@newssvr25.news.prodigy.net>, Joerg <notthisjoergsch@removethispacbell.net> writes >Hello Ray, > >> >> A few points here: >> 1) You can obtain a PE license in any state that adheres to the NSPE >> guidelines without a degree if you have 20 years experience in the >> field. That invalidates your concern about ABET certification, since >> most engineering schools in the US have had the certification for the >> past 20 years. >> > >Which leave out anyone with a degree from a foreign school. Not in the UK They "recognise" a lot of over seas universities. > 20+ years >ago government bodies told students it would be good to gain overseas >experience and even study there. So, what do we tell them now? That they >shot themselves in the foot and shouldn't have listened? Only if you don't recognise foreign universities. Or forigen qualifications. >Other states don't, and I sure won't ever live there. I wonder what world you do live in... :-) >> 6) Some of the medical firms I've dealt with specifically do require a >> PE on a project involving medical equipment that could potentially >> endanger a patient. I'm not sure if it is a regulatory requirement or >> not, but it was a requirement from somewhere. ... > >I have never encountered that. We live by standards such as UL2601, FDA >regulations and so on. the FDA ones don't seem to bad. >As I replied to Chris before a PE license can oblige you to mandatory PL >coverage. Just for the fun go out and try to find an underwriter. I did, >until I had blisters from dialing. Zilch. Nada. You can get it in the UK It will get better as more people are required to be a PE/C.Eng etc -- \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \/\/\/\/\ Chris Hills Staffs England /\/\/\/\/ /\/\/ chris@phaedsys.org www.phaedsys.org \/\/\ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/Article: 95404
On Mon, 23 Jan 2006 21:10:06 +0800, "Rob" <rdsfal@yahoo.com.au> wrote:
>
><bill.sloman@ieee.org> wrote in message
>news:1137821560.131641.325030@g44g2000cwa.googlegroups.com...
>>
>> Jim Thompson wrote:
>> > On Fri, 20 Jan 2006 10:04:52 -0800, Don Bowey <dbowey@comcast.net>
>> > wrote:
>> >
>> > >On 1/20/06 8:58 AM, in article
>> > >1137776297.373102.256560@f14g2000cwb.googlegroups.com,
>"amyler@eircom.net"
>> > ><amyler@eircom.net> wrote:
>> > >
>> > >> If you were a european I'd credit you with subtle use of irony....
>> > >>
>> > >> But I'm sure you're a nice guy really :-)
>> > >>
>> > >
>> > >No, he isn't.
>> > >
>> > [snip]
>> > >Don
>> >
>> > You don't think I'm a nice guy? Why?
>>
>> Neither nice nor all that full of insight.
>>
>> I wonder how he is doing with his scheme to report me to the current
>> version of the committee for Un-American activities ... No black
>> helicopters so far, and the Australian security services didn't bother
>> searching my suitcases when I entered the country a week or so ago.
>>
>> --
>> Bill Sloman, Nijmegen
>>
>
>No search, but I'm sure you were asked if you were carrying any fresh fruit.
>
Slow-man IS a fruit ;-)
...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |
It's what you learn, after you know it all, that counts.
Article: 95405"Spehro Pefhany" <speffSNIP@interlogDOTyou.knowwhat> schreef in bericht news:5uj9t1dkjk5q89v8t977rqi4ts3bag7n6a@4ax.com... > On Mon, 23 Jan 2006 09:46:44 +0100, the renowned "Frank Bemelman" > <f.bemelmanq@xs4all.invalid.nl> wrote: > > ><bill.sloman@ieee.org> schreef in bericht > >news:1137987045.839508.7650@o13g2000cwo.googlegroups.com... > >> > >> Good for Slovenia! The Netherlands is acquiring a culture of eating > >> well - we now have three restaurants with three Michelin stars - but > >> there is a long way to go. It a Dutch person recommends a restaurant to > >> you, you can be fairly sure that the decor, ambience and service will > >> all be okay, but the food can be total rubbish. > > > >It is indeed a long way to go, if the goal is three Michelin star food > >for everyone, everyday. > > > >Sheesh! > > > >;) > > Doesn't sound like a bad goal. Instead of food insecurity you'd have > to worry about the prevalence of gout. I'm getting more worried about my wallet, and what's in it. Bill is a snob of course, as most Michelin star restaurants customers are. Last friday I had the pleasure of a dinner at Ron Blaauw's Palazzo, in Amsterdam. http://www.egol.de/palazzo/amsterdam/gaenge/e_gaenge_8_a.php Ron Blaauw is good for 1 star, so the food was excellent. But at this level, the amount of joy has not much to do with the food. It's a sum of everything that surrounds it, and probably the most important ingredient of any good dinner is how you and your guests are feeling themselves. Most of the better restaurants here charge 20-25 euro for a main dish, and you can expect excellent food for that. Entrees and desserts for 10-12 euro. A bottle of good wine, 30-35 euro. Paying double or triple get's you into the Michelin star places, but gives diminishing returns. Of course you can spend all evening there trying to find something you can complain about, such as a tiny spot on the table ware, the wine being 2 degrees too cold, the haricots verts too long or too short and what have you, and you will not be able to find anything wrong. But that is not my definition of a perfect dinner ;) -- Thanks, Frank. (remove 'q' and '.invalid' when replying by email)Article: 95406
"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message news:CtwAf.12759$_S7.2836@newssvr14.news.prodigy.com... > Hello Chris, > >> >> The C.Eng requires a degree, More to the point a suitable degree from a >> recognised university. > > That's just one of the problems. Here in the US they often require ABET > compliance of your course work. For many older engineers that is not quite > possible because even top notch universities didn't have some ABET cert > 20+ years ago. Also, you'd exclude pretty much all foreign universities. > That is hardcore discrimination and can (and would be) litigated. > > >> You also need three supporters who are also C.Eng and are prepared to >> sign off on your work experience. > > That's the 2nd problem: There is no critical mass here. The classical > chicken and egg situation. I know a whopping two licensed engineers but > both in the wrong field since they are civil engineers. I don't know any > licensed EE personally (ok, if I make it to one of Jim's parties some day > I would know at least one) and have never come across one in my work. So, > where would someone like me or all my colleagues obtain three supporters? > The PE 's giving you refeence/verification do NOT have to be EEs. I just was approved to take the exam this April and 2 of my references were licensed mechanical PEs, not EE. Don't let this deter you....you can find PEs of any field and use for reference. PaulArticle: 95407
Hi Peter, I haven't worked with V4 yet, but in my V2 designs I usually found that the tools will pack into IOB registers if it is possible. The problem is finding out why it isn't possible, when they don't. In one case the problem was routing. In V2 (and possibly V4) IOB's come in pairs with some shared routing resources. In this case you may have all of the required register resources available in an IOB, but no way to route to them because of routing usage in the adjacent IOB. The acid test is usually to instantiate the IOB registers and look at error messages when the register cannot be packed as assigned. Another problem I found was limited set/reset routing capability among the IOB registers. Often set/reset terms are not important for one register and you can fix the problem by sharing them with another register or removing them (no set/reset term still means the register gets initialized at configuration time, though). Hope this gets you closer, Gabor Peter wrote: > Hello Group, > > I'm having difficulty convincing Xilinx ISE (8.1SP1 WebPack) PAR to pack > some of my signals into the IOBs of an XC4LVX25-FF668. A simple > demonstration case is the MIG 1.4 dimm72 VHDL design for the ML461 > memory eval board. The FPGA editor shows that most of the DDR command > bus outputs correctly push their registers into the IOBs; however the > DDR_CS and DDR_ODT output get registered within the fabric. The > resulting skew between DDR_CS and the rest of the command bus outputs > becomes fatal when generating cores for DDR systems with multiple ranks > (chip-selects). The skew of 2ns or so is clearly visible in timing > simulations, and my DDR2 model throws a tantrum about invalid setup time > on DDR_CS. > > I have tried seducing ISE into pushing the DDR_CS registers to the IOBs > by setting XST "Pack I/O Registers into IOBs" to both "Auto" and "Yes". > I have set XST register balancing to "No" and to "Yes" with Move > First/Last Flip-Flop Stage disabled. I am also enabling the MAP option > to Pack I/O Registers/Latches into IOBs. I am new to Xilinx FPGAs. > With Altera I would enable Fast Inputs/Outputs in Quartus, and all the > registered I/O would get pushed to the pads. Am I missing something > obvious? > > One thing I did notice: DDR_CS (and ODT) is different from the rest of > the command bus in that it is directly fed a combinatorial term, whereas > the rest of the command outputs are just relatches of signals registered > on previous clocks. Should this make a difference? It seems to me > that a combinatorial term could be routed from a slice to an I/O > register, just as easily as a registered signal could... > > Any thoughts or meditations are appreciated, > > -PeterArticle: 95408
Antti Lukats wrote: > just for fun I wrote down how I see it possible to have different FPGAs to > be cut out from single wafer covered with completly repeating pattern > > http://help.xilant.com/RAA > > I am not including the text here as I may edit the original even before the > post is appearing in the NG > Antti: How did you get that site to look like a Wikipedia site? I love it! -EliArticle: 95409
"Eli Hughes" <emh203@psu.edu> wrote in message news:dr2rmt$1ekc$1@f04n12.cac.psu.edu... > Antti Lukats wrote: >> just for fun I wrote down how I see it possible to have different FPGAs >> to be cut out from single wafer covered with completly repeating pattern >> >> http://help.xilant.com/RAA >> >> I am not including the text here as I may edit the original even before >> the post is appearing in the NG >> > > Antti: > > How did you get that site to look like a Wikipedia site? I love it! > > -Eli > http://en.wikipedia.org/wiki/MediaWiki I guess!Article: 95410
"Eli Hughes" <emh203@psu.edu> schrieb im Newsbeitrag news:dr2rmt$1ekc$1@f04n12.cac.psu.edu... > Antti Lukats wrote: >> just for fun I wrote down how I see it possible to have different FPGAs >> to be cut out from single wafer covered with completly repeating pattern >> >> http://help.xilant.com/RAA >> >> I am not including the text here as I may edit the original even before >> the post is appearing in the NG >> > > Antti: > > How did you get that site to look like a Wikipedia site? I love it! > > -Eli > thats REAL easy, just upload mediawiki files and run admin\install.php :) http://sourceforge.net/projects/wikipedia/ in order to have short URL I also changed later the .htaccess in subdomain http document root, as I did not recall the mysql admin root on my own server so I had to create the database from phpmyadmin, however the wiki install script can do it fully automatically also. if you (or someone else) is looking for web presence provider (web server, database, CVS, etc..) then our server is underloaded and has lots of free space, I am having trouble to fill the 40GB disk space and traffic quato is also not used at all -- Antti Lukats http://www.xilant.comArticle: 95411
"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag news:43d4f2e3$0$15793$14726298@news.sunsite.dk... > "Eli Hughes" <emh203@psu.edu> wrote in message > news:dr2rmt$1ekc$1@f04n12.cac.psu.edu... >> Antti Lukats wrote: >>> just for fun I wrote down how I see it possible to have different FPGAs >>> to be cut out from single wafer covered with completly repeating pattern >>> >>> http://help.xilant.com/RAA >>> >>> I am not including the text here as I may edit the original even before >>> the post is appearing in the NG >>> >> >> Antti: >> >> How did you get that site to look like a Wikipedia site? I love it! >> >> -Eli >> > http://en.wikipedia.org/wiki/MediaWiki I guess! > guessed correctly. its the only wiki that makes sense. I have tried many different, some other may have some other nice features, but MediaWiki really is the one to use -- Antti Lukats http://www.xilant.comArticle: 95412
Hi, on xapp623 on PDS there are all the step to define the number and the values of decoupling capacitors. This number depends on how many Vcco you need to connect for each bank, and the latter is function of the outputs implemented. But, if I use all the I/O pins of a bank as input, how many Vcco pins should I use? Thanks, MarcoArticle: 95413
"John D. Davis" <johnd@stanford.edu> schrieb im Newsbeitrag news:Pine.GSO.4.44.0601181400370.9227-100000@elaine15.Stanford.EDU... > Is your library for the CRC generation available to others. > > JOhn http://help.xilant.com/Xilinx:Configuration:CRC the code snippet that does calc the CRC is at the above link, bitpatch utility with the ability to inject fixed CRC is scheduled for release as well -- Antti Lukats http://www.xilant.comArticle: 95414
>> Hello Group, >> >> I'm having difficulty convincing Xilinx ISE (8.1SP1 WebPack) PAR to pack >> some of my signals into the IOBs of an XC4LVX25-FF668. A simple >> demonstration case is the MIG 1.4 dimm72 VHDL design for the ML461 >> memory eval board. The FPGA editor shows that most of the DDR command >> bus outputs correctly push their registers into the IOBs; however the >> DDR_CS and DDR_ODT output get registered within the fabric. The >> resulting skew between DDR_CS and the rest of the command bus outputs >> becomes fatal when generating cores for DDR systems with multiple ranks >> (chip-selects). The skew of 2ns or so is clearly visible in timing >> simulations, and my DDR2 model throws a tantrum about invalid setup time >> on DDR_CS. >> >> I have tried seducing ISE into pushing the DDR_CS registers to the IOBs >> by setting XST "Pack I/O Registers into IOBs" to both "Auto" and "Yes". >> I have set XST register balancing to "No" and to "Yes" with Move >> First/Last Flip-Flop Stage disabled. I am also enabling the MAP option >> to Pack I/O Registers/Latches into IOBs. I am new to Xilinx FPGAs. >> With Altera I would enable Fast Inputs/Outputs in Quartus, and all the >> registered I/O would get pushed to the pads. Am I missing something >> obvious? >> >> One thing I did notice: DDR_CS (and ODT) is different from the rest of >> the command bus in that it is directly fed a combinatorial term, whereas >> the rest of the command outputs are just relatches of signals registered >> on previous clocks. Should this make a difference? It seems to me >> that a combinatorial term could be routed from a slice to an I/O >> register, just as easily as a registered signal could... >> >> Any thoughts or meditations are appreciated, >> >> -Peter > Hi Peter it seems that you need to ask mr Lakshmi Gopalakrishnan what the means with his comment: // added for deep designs " the CS FF could be in IOB only if registers are duplicated, otherwise defenetly not as the outputs of those regs are used again in the design as inputs. as long as register duplication does not work there is no hope to see the CS output flops in IOBs -- Antti Lukats http://www.xilant.comArticle: 95415
Robin Bruce wrote: > I am compelled to agree with Peter here. unless any forum is moderated, this abuse will happen, creating more threads to complain about it is just more polution ... unless the group wishes to moderate, and has people willing to do it, complaining is senseless. > The post is undoubtedly irrelevant, arguably stupid - certainly > ignorant. There are xenophobic generalisations, and by about the 80th > post I was convinced it was racist. I go to comp.arch.fpga in the hope > of finding a thread that might aid me in my research, or educate me on > an area of FPGA design of which I'm ignorant. I do not expect to see > posts from people espousing racist anthropoligical theories. absoulutly true ... but not the whole thread, or even vary many of the authors in the thread ... the brash branding of the entire thread, even if dominated by a couple non-PC posters I take offensive, as one of the posters in that thread. > It seems to me that Peter has earned his right to criticise this post > through the countless hours he has spent helping comp.arch.fpga to > become a respected resource to the FPGA community. Sure he has the right, just as they do ... as do we to object about creating yet another thread to hash it out. Posting directly in the thread asking for some order might have been a LOT better.Article: 95416
Hi We work with a XCF01S and a Spartan 3 XC3S200. JTAG works with 2.5V, Spartan Vcco (INIT_B and DIN/D0) has 3.3V. The connections between XCF and Spartan are according the application note for 3.3V output (INIT_B) to 2.5V input CE/RES. Programming the Flash and booting from Flash works fine. Programming the FPGA works only, when we have the same code in the Flash. When we try to load a different code (as is in the Flash) per JTAG to the FPGA, the FPGA doesn't start up. Does anybody know what's going wrong? LuigiArticle: 95417
Sorry, I forgot to mention: The hardware is Dual AMD 3800 with 2GB RAM. Everything else is snappy and extremely fast. It was fine with ISE 7.1 but 8.1 broke it. I even installed the service pack 8.1.01, which didn't bring any help.Article: 95418
"luigi" <luigi.zadra@bluewin.ch> schrieb im Newsbeitrag news:1138031781.352244.275760@g14g2000cwa.googlegroups.com... > Hi > We work with a XCF01S and a Spartan 3 XC3S200. > JTAG works with 2.5V, Spartan Vcco (INIT_B and DIN/D0) has 3.3V. The > connections between XCF and Spartan are according the application note > for 3.3V output (INIT_B) to 2.5V input CE/RES. > > Programming the Flash and booting from Flash works fine. > Programming the FPGA works only, when we have the same code in the > Flash. > When we try to load a different code (as is in the Flash) per JTAG to > the FPGA, the FPGA doesn't start up. > > Does anybody know what's going wrong? > > Luigi > yes. I know ==> I am anybody am I? :) there is xilinx AR on this, their suggested solution is to change FPGA MODE pin setting. similar or even worse happens with S3e and Parallel flash, the configuration from Parallel flash (if located at close to the start address) prohibits the FPGA from being configured over JTAG and as Flash programmer over FPGA JTAG indirect so flash programming also fails. we have special workaround for this that puts the parallel flash into read id mode and clears FPGA config and then reconfigures FPGA with Flash programming IP and then programs flash. for Platform flash, you must erase platform flash and force FPGA reconfiguration then it will be possible to reconfigure over JTAG again -- Antti Lukats http://www.xilant.comArticle: 95419
On Sun, 22 Jan 2006 11:33:35 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon@My-Web-Site.com> wrote: >>But what is this obsession with US juvenile nutrition? It's a weird, >>recurrent theme. >> >>John > >Slow-man is running out of things to harp about and is now grasping at >straws. > Sure looks that way. JohnArticle: 95420
luigi wrote: > Hi > We work with a XCF01S and a Spartan 3 XC3S200. > JTAG works with 2.5V, Spartan Vcco (INIT_B and DIN/D0) has 3.3V. The > connections between XCF and Spartan are according the application note > for 3.3V output (INIT_B) to 2.5V input CE/RES. > > Programming the Flash and booting from Flash works fine. > Programming the FPGA works only, when we have the same code in the > Flash. > When we try to load a different code (as is in the Flash) per JTAG to > the FPGA, the FPGA doesn't start up. > > Does anybody know what's going wrong? > > Luigi > Change the mode pins on the FPGA AurashArticle: 95421
Jeff Cunningham wrote: > Marketing? Heck I would call it outright fraud. The silliness with gate > counts is at least somewhat understandable since there is no really > meaningful conversion. But if a cookie manufacturer sold boxes of 27 > cookies but stamped on the box that there are 30 inside, isn't that > considered a crime? They can't defend themselves by saying in the small > print that their cookies are 12% better than the competition, and they > count as 1.12 each. The real scam in this, is not solidly disclaiming that you are very likely to be unable to route a fully used part because it lacks routing resources. AND that you are very likely to be unable to use all the pins in many designs because you will exceed the maximum number of toggles per I/O bank. AND that you are very likely to be unable to use all of the LUT's and FF's concurrently as you can not get enough power into the device if it's even close to mostly active as they assume a very high percentage of idle or low speed logic. AND that if you do run it close to max power, it may not be possible to keep it cool. All of this comes out as you read application notes and use the online power estimator, but little if any is visible from the data sheets or other design materials that one would use up front for initial parts selection. So, if they want to take every advantage number wise to claim usable gates, then they also need to very clearly at the same time explain each of the cases that may force the number of REALLY USEABLE gates to be significantly smaller. Consider a reconfigurable computing application where you fill the device with small very active computational cores that are very active logic wise ... this drives the dynamic power requirements and heat load thru the roof, forcing the part to be seriously derated. With applications like this it's fairly easy to end up with applications that might have toggle rates that are very very high as a percentage of the device. or just try and use it as a huge digital delay register with programable taps ... Nearly every LUT and FF is part of a shift register ... at any speed which is a significant percentage of rated clock speed the power and heat will force the design to be seriously derated. When you start to look at the current profile around clock edges to deliver the total power requirements the power estimator gives for these kind of applications, it's pretty clear that much power will hit the power pins only a fraction of the clock duty cycle, even if spreading the current with multi-phase clocks. They do not provide any package level power models to simulate that die isn't seeing much larger ripple than can be observed on the host pcb due to spiking current profiles. The extreme of this farse would be a vendor claiming six times the logic resources, and 1/4 the price, but only offering routing to allow 1% of the resources to be used ... I'm sure the same vendor would be at the front of the pack to set the record straight about requiring the derating of the part due to resource limitations.Article: 95422
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:nfr0t1dvp60bh54ate35numiecflucipar@4ax.com... > On Fri, 20 Jan 2006 03:43:58 GMT, "HoustonEngineer" <xxx@yyy.com> > wrote: > > >Here is an observation - what do y'all think ? > > > >1 - Indian / Chinese / East European /etc people are at least as smart and > >hardworking as Westerner's / Japanese > >2 - However, they work for something like $10% of what we will (or could > >live on) > >3 - Our major advantage (in terms of these newsgroups) is our experience > >with these subjects/technologies/methods/products > >4 - On these newsgroups, many of the questions originate from people in > >India, China or Eastern Europe and are answered by Westerners > >5 - Are we shooting ourselves in the foot ? > > > >I'm not suggesting this is a bad thing - after five years in the US I am > >actively looking for opportunities elsewhere - I just thought it was an > >interesting question. > > > Is it our destiny to be rich and well fed, while the rest of the world > stays poor and hungry? Sure - for as long as the rest of the world insist on their right to choose a looser culture! > Must we always be the elite? Of Course - That is one of the advantages of having a civilisation. > Is the world > economy a zero-sum game, where we want 90% of the winnings? No, the world economy is very far from a zero sum game - the cake can grow larger if it is allowed to - but most of the time people that are fearful of change will setup systems to keep things the same as they always was and you get the living standard that was and not what could be. i.e: Why subsidise european sugar farmers when sugar can be had in Brazil cheaper - it is maybe 30000 people in the whole of the EU!! or: Why block the internet because it is "un-islamic" - if Islam is so allmighty it should be able to stand alone!! The cake grows when trade and information is allowed to flow freely and it shrinks when the flow is restricted by taxes, political- or cultural barriers. The poorest and indeed the worst performing countries are the most closed ones! So, if some chinese or indian snags my idea and build a business from it, Fine. Then maybe I can sell him some other things - since he is now monied and can afford them. That is how it works. > > John > >Article: 95423
Marco, All of them. We do all testing with all Vcco/gnds connected. There is something called SSI, simultaneously switching inputs. If the inputs have overshoot or undershoot, or some small ringing (as they all do unless perfectly matched), then there will be currents flowing which will create ground/Vcco bounce. Just because it is an input is no reason to think it doesn't need all its Vcco pins. Austin Marco wrote: > Hi, on xapp623 on PDS there are all the step to define the number and > the values of decoupling capacitors. This number depends on how many > Vcco you need to connect for each bank, and the latter is function of > the outputs implemented. But, if I use all the I/O pins of a bank as > input, how many Vcco pins should I use? > Thanks, Marco >Article: 95424
<bill.sloman@ieee.org> wrote in message news:1138020331.150253.5950@g44g2000cwa.googlegroups.com... > > Jim Thompson wrote: >> >> Slow-man is running out of things to harp about and is now grasping at >> straws. > > Jim Thompson hasn't a clue about the subject under discussion, but we > get his two cents worth anyway. I had hoped that he was still busy > trying to get my security cleaances revoked, but it seems now he wants > to be futile someplace else. Children, children - play nice. I find it odd that grown men, and no doubt entirely mature and sensible grown men, revert to kindergarten tactics when arguing via this protective barrier we call the Internet. To say "it's the nature of usenet" doesn't cut it - we're still people, no matter what the medium. Is dignity disposable? And no doubt I'll get flambéed now for pointing this out... Steve http://www.fivetrees.com
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