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"Brian Davis" <brimdavis@aol.com> schrieb im Newsbeitrag news:1136552186.711153.183580@g44g2000cwa.googlegroups.com... > Antti Lukats wrote: >> >> you could try there >> http://www.xilinx.com/s3ediscount >> but I am afraid it may as well not lead to the actual online entry form >> :( >> > > I received the sample pack in the mail yesterday (from Avnet/US); > the $25 discount offer on the case says it's valid until the end of > January, but if you click the link it says: > "The introductory pricing period for the Spartan-3E Kit is now over" > > Over before it started, eh... > > The other funny thing was, when I took the board out of the case there > was a strategically placed piece of electrical tape on the board whose > only purpose seemed to be to obscure the "Linear Technology" logo > on the silkscreen. Avnet is not selling Linear ! Tthey sell power supply solutions from TI, so I am not surprised. Maybe they did also take out the Linear Tech's ad booklet from the DVD box !? AnttiArticle: 94201
I had posted earlier my issues with Fpga card. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534630e805751a/21f880630f20ca74?q=fpga+pci&rnum=1#21f880630f20ca74 The AMIRIX fpga card uses powerspan II pci bus switch fro Tundra. The powerpc inside teh fpga has linux running..I have some data in my PLB master/slave module which has to be transferred to the host pc. So I was suggested to llok into DMA transfer part. I went through the powerspan II manual . It doesnt provide the details of data cycle for the DMA . i.e it only says to write the DMA configuration registers with the source address , destination address... and then raisethe go signal. Now my problem is that the source address needs to be the on-board RAM address. I dont want to use the onboard RAM.I dont want to use the powerpc either. I wanted to write a module in vhdl to do the confguration adn the forward the data to the bridge. I dont know whether this is possible. I I dont have experience in this field. How can I do a transfer of data from my master/slave module to the host computer? Is there a way ? Thanks, NiteshArticle: 94202
hi, as far as i know this is because u r not using those RAMs (the synthesize tools will optimize those are not using in your design). to remove such optimisation u can untick the options in the synthesize(properties) like register duplication and equvalent register removal.Article: 94203
On 5 Jan 2006 06:36:39 -0800, "hitsx@hit.edu.cn" <hitsx@hit.edu.cn> wrote: >Now I want to design a RISC cpu for study the cpu architecture, and I >am puzzled about how to start? >Whether should I start with a RISC 16 bit cpu, including just serveral >instructions like add, substract, multiply and divide? >And I wonder whether I should introduce the pipeline and superscalar >into the architecture? The best place for you to start is http://www.fpgacpu.org/xsoc/cc.html Enjoy!! Philip Philip Freidin FliptronicsArticle: 94204
On Fri, 6 Jan 2006 16:37:52 -0800, "Brendan Illingworth" <billingworth@electrascan.com> wrote: >Hi All, > >I am using Xilinx ISE 7.1 and ModelSim XE III 6.0 to analze flip-flop and >routing behavior in a Virtex II part. Ports that are declared in my VHDL >entity declaration are simulated and shown in the wave window in ModelSim. >My question is this; how does one specify in Xilinx ISE additional signals >(that are not routed to IOB's) to be simulated in ModelSim? Using the "add >probe" feature seems to route the signals to IOB pads and then simulates the >result of that, I need to see the signal inside a slice (or at least right >before or after the slice). In Modelsim, once the design has been loaded, using the GUI interface, you can open windows displaying the design structure (as a directory type tree), and the named signals. Navigate to the design sub-unit you need to monitor; its signals are listed in the "signals" window. Select those you need, right click, and "add selected signals to Wave window". Now simulate and they will be displayed. If you missed some, add them, restart, and simulate again. You can also do the same via TCL script of course; the GUI approach simply generates the relevant script commands. Or you can save the Wave window format as a ".do" script to recreate this test later. Caveat: above refers to ModelSim SE; I believe it's true of XE but I'm not 100% certain) - BrianArticle: 94205
Search the keyword "keep" or "preserve" in the tool manuals and go from there. HTH, Jim for "zephyrer" <zephyrer@gmail.com> wrote in message news:1136598989.134301.62220@g44g2000cwa.googlegroups.com... > Hi, I have a problem that after Synplify or XST optimizing, my 16x8 RAM > is reduced to 1x8. This is not my hope. How to avoid this? >Article: 94206
Hi, "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:8cfvr1tslmm23tqn196n631hvfoi96r3d5@4ax.com... > In Modelsim, once the design has been loaded, using the GUI interface, > you can open windows displaying the design structure (as a directory > type tree), and the named signals. Navigate to the design sub-unit you > need to monitor; its signals are listed in the "signals" window. Select > those you need, right click, and "add selected signals to Wave window". > > Now simulate and they will be displayed. > > If you missed some, add them, restart, and simulate again. > > You can also do the same via TCL script of course; the GUI approach > simply generates the relevant script commands. Or you can save the Wave > window format as a ".do" script to recreate this test later. > > Caveat: above refers to ModelSim SE; I believe it's true of XE but I'm > not 100% certain) Sure, it also applies for MXE. > > - BrianArticle: 94207
John Larkin wrote:
> I don't have time to learn an HDL. I read the Xilinx book, draw
> schematics (on paper!), and hand them to a minion to enter and
> compile.
Ah! The academic solution.
Where have all the minions gone?
Long time passing ...
-- Mike Treseler
Article: 94208Eli Hughes wrote: > Hello: > > I have absolutely no experience in ASIC design. I do however have > experience in FPGA. I have a CPU design that is currently working in a > Xilinx FPGA. The design fits in a spartan3 XCS200 (144pin Package). > > I want to migrate to a fully custom chip in a different package. My > design only has 10 pins that are used for signals so I want to get into > a very small package such as a SOIC20 or a micro lead frame (QFN) 32 > package. > > > Is it possible to take a synthesizable netlist to an ASIC vendor and get > a custom chip in a custom package? What kind of Costs should I expect? > Right now the FPGA solution is too big and to expensive for the runs I > need. The Spartan chips need to get to around $4 (and in a smaller > package) to become cost effective (rather than $20). Also, I want to > get rid of the configuration FLASH to save $$ (Hence the ASIC) You do not mention your volumes : ASICs (and even some FPGA-ASIC alternatives, as well ) have substantial NRE (setup) costs, as well as minimum volumes. FPGA vendors boast about sub $3 'future-price' devices, and also have flows that lower prices for stable code and high volume. - but their high volume, and your high volume, may be different :) For cheapest config, look at SPI FLASH devices. -jgArticle: 94209
On Thu, 05 Jan 2006 01:40:11 +0000, mk wrote: > On Wed, 04 Jan 2006 12:18:48 -0800, Mike Oxlarge > <oxlargeMike@yahoo.com> wrote: > >> However, I'm now trying to implement what mk suggested: > > To be frank I am not sure what your code is trying to do but let me > start it here and you can fix it the way you want: > <snip> > > As there is no specific reason I can see for you to have the negedge, > put all your code into the posedge. If the behavior is not what you > want, change it till you get it right. One thing you can do is to put > all the code between the first else to the end of code in a > combinational always block so that not all variables are registered or > you don't have to wait for unnecessary cycles to get curval+1 etc. > > HTH. Thanks for setting me straight with not using a mixed phase approach. I had only used it because I had seen it used as an example somewhere on the internet. It was probably either a bad example, or I just didn't get the point of the code. I do see the need to keep to a single clk edge, and to use a combinational block (or combinational plus sequential) to calculate my next value. Many thanks to you, and everyone else who offered guidance and advice. -MOArticle: 94210
john wrote:
> Hello,
>
> I have interfaced a 8 bit parallel data bus and a clock signal of the
> USB device to a CPLD. I need to store 32bits of data in a buffer. And
> then serially shift out the 32 bits. The loading of the data into the
> buffer can only be done by using the clock coming from the USB device
> because when USB generates data it generates clock with it. So I
> decided to use another clock to serial out the data. The problem is the
> handshaking between the USB process and the serial out process. The two
> processes have different clocks so the serial out process could miss
> the signal form the USB process that the buffer is ready to be serial
> out.
> Please advice a solution, thanks
>
> John
>
Add a flip flop clocked by the usb clock domain that toggles (changes to
opposite state) each time the usb data is written to the register. Then
synchronize the toggle signal to your local clock domain by passing it
through a flip-flop or two clocked by the local cloc domain. Then after
the signal is syncrhonized, delay it one more clock, and use the
exclusive or of that signal to clock enable a second rank register. The
xor will produce a 1 clock wide pulse in your local clock domain that
happens well after the data is available at the outputs of the first
rank register. This is reliable as long as the local clock domain is
clocked several times between each usb transfer. In the case of your
shift register, that clock enable can be the load pulse to your shift
register. it would look something like this:
Process(usb_clk)
begin
if rising_edge(usb_clk) then
if we='1' then
capture_register<= usb_data_in;
toggle_ff <= not toggle_ff;
end if;
end if;
end process;
process(lcl_clk)
begin
if rising_edge(lcl_clk) then
sync_ff <= toggle_ff;
sync_z <= sync_ff;
ld_ena <= sync_ff xor sync_z;
if ld_ena='1' then
shift_register <= capture_register;
else
shift_register<=
'0'&shift_register(shift_register'left downto 1);
end if;
end if;
end process;
By just toggling the state of the toggle signal, you guarantee you will
not miss the write event regardless of the clock frequencies provided
the local clock period is shorter than the write interval.
Article: 94211Absolutely.Article: 94212
>The solution is simple, but far from obvious. You need to >download and apply the patch for ISE 7.1 or install the >latest service pack (4). There is a bug that inverts all of >the outputs of CPLDs (with no service pack and also >maybe SP1). Bingo. That fixed everything. After downloading the 7.1.04 update, which was something like 325 megabytes, nearly as big as the full download, everything is working fine. My counter counts right, the outputs aren't inverted, and I can even directly assign pins to a value and have it work. >Xilinx has refused to post this information to their download >page. I even talked to a factory FAE and he could not get >them to post it. The only way you can find out about it is to >search their site for key words that match the article. I spent a long time a couple nights ago searching their whole knowledge base section and reading everything I could find on the 9500 family CPLDs and never found this information. I only found it after I went to the download page for the service pack, and found the link that said something like "read this before installing" and somewhere in there was a list of what the update fixed, and in there was a short sentence or two saying that it fixed an issue with CPLD outputs being inverted. It never did mention fixing the problem where I couldn't directly assign a pin to 1 or 0 and have it work. Either way it came out as a high. Right now, there isn't much I can say in polite company about how this makes me feel. This bug has cost me several days time. If I had been working on a real project at work, instead of hobby tinkering at home, it would have cost the company a lot of money in engineering time. I think it is rather irresponsible of them to not at least have a notice on the download page for 7.1 saying you NEED the update to 7.1.04 if you are using CPLDs. And what they really should have done is taken down the 7.1 update and replaced it with a 7.1.04 full download, and also have the 7.1.04 update available for those who already have 7.1 installed. Many thanks to you Marc, and to everyone else who posted their ideas. Now I can get around to doing something useful and maybe fun with this CPLD.Article: 94213
I had posted earlier my issues with Fpga card. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534630e805751a/21f880630f20ca74?q=fpga+pci&rnum=1#21f880630f20ca74 The AMIRIX fpga card uses powerspan II pci bus switch fro Tundra. The powerpc inside teh fpga has linux running..I have some data in my PLB master/slave module which has to be transferred to the host pc. So I was suggested to llok into DMA transfer part. I went through the powerspan II manual . It doesnt provide the details of data cycle for the DMA . i.e it only says to write the DMA configuration registers with the source address , destination address... and then raisethe go signal. Now my problem is that the source address needs to be the on-board RAM address. I dont want to use the onboard RAM.I dont want to use the powerpc either. I wanted to write a module in vhdl to do the confguration adn the forward the data to the bridge. I dont know whether this is possible. I I dont have experience in this field. How can I do a transfer of data from my master/slave module to the host computer? Is there a way ? Thanks, NiteshArticle: 94214
Mike Harrison schrieb: > What's their definition of a discrete component..? > I suspect they are talking about resistors etc. > Does it actually say that each signal must go to a single chip ? > If not, then I see no problems with > signals going to different (buffer) chips. Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > My understanding is that you can only load once each line that's it ... That is bad enough. Why should a microswitch be a sginificantly lower load to a signal than an FPGA or ASIC? An IDT quickswitch can have up to 7pF capacitance. "Section 4.4.3.4 Signal Loading Shared PCI signals must be limited to one load on the expansion board. [...] It is specifically a violation of this specification for expansion boards to: * Attach an expansion ROM directly (or via bus transceivers) on any PCI pin. * Attach two or more PCU devices on an expansion board [...] * Attach any logic [..] that "snoops" PCI pins. * Use PCI component sets that place more than one load on each PCI pin: e.g. separate address and data path components. * Use a PCI component that hast more than 10pF capacitance per pin. * Attach any pull-up resistors or other discrete devices to the PCI signals, unless thay are placed *behind* a PCI-to_PCI bridge." Kolja SulimmaArticle: 94215
Nitesh Because all the addresses on the PCI bus are set by a mixture of card requirements and software allocation during PCI configuration you will need software/driver to read the allocation and give the relevant details to your card for the DMA transfer. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 PCI Development Board. http://www.enterpoint.co.uk "Nitesh" <nitesh.guinde@gmail.com> wrote in message news:1136630712.085169.325340@f14g2000cwb.googlegroups.com... >I had posted earlier my issues with Fpga card. > > http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/73534630e805751a/21f880630f20ca74?q=fpga+pci&rnum=1#21f880630f20ca74 > > The AMIRIX fpga card uses powerspan II pci bus switch fro Tundra. The > powerpc inside teh fpga has linux running..I have some data in my PLB > master/slave module which has to be transferred to the host pc. So I > was suggested to llok into DMA transfer part. I went through the > powerspan II manual . It doesnt provide the details of data cycle for > the DMA . i.e it only says to write the DMA configuration registers > with the source address , destination address... and then raisethe go > signal. Now my problem is that the source address needs to be the > on-board RAM address. I dont want to use the onboard RAM.I dont want to > use the powerpc either. I wanted to write a module in vhdl to do the > confguration adn the forward the data to the bridge. I dont know > whether this is possible. I > > I dont have experience in this field. How can I do a transfer of data > from my master/slave module to the host computer? > Is there a way ? > Thanks, > Nitesh >Article: 94216
One feature to look for is if your data is likely to have a lot '0's either by error or otherwise then to use a algorithm that has a starting preload of all '1's in the CRC. '0's then have an effect on the CRC generated right from the start of the data and hence errors can be detected. If you have a preload of '0's that isn't the case. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "rickman" <spamgoeshere4@yahoo.com> wrote in message news:1136591102.008773.180960@g43g2000cwa.googlegroups.com... >I am looking at using a CRC to provide single bit error correction and > multiple bit error detection. I have worked with CRCs before and know > how to implement them. But I am lacking some of the theoretical > background on how to choose the polynomial. My data packets are a > total of 191 bits with a 31 bit header containing the CRC and 160 data > bits. The header will have its own error correction. I am trying to > determine an optimal CRC polynomial for the whole packet. Currently > there is space in the header for a CRC-8. I may be able to find a few > spare bits to make the CRC 10 or 12 bits if I have to. > > Any pointers to show me how to evaluate a polynomial? Or any shortcuts > that can be recommended? I guess this has been done before. >Article: 94217
Jerzy Gbur wrote: > Peter Alfke napisa=B3(a): > > Jerzy, if you check with a high-impedance oscillosope probe, you cannot > > detect the difference between an active High (10 Ohm) or 3-stated with > > a weak pull-up (multi-kilohms). > > To see the difference, load the pin with a kilohm to ground... > > Peter Alfke > > > > Thanks all of you. > It's great pleasure to have answers so soon. > > I work on this project whole last year, so belive me, I've read V2 > datasheets :) > It's almost finished. > We have problems with other chip which is partially controlled by V2. > And there I use scope on that line where I saw what I wrote in my > previos post. So... > > 1. It was scope, > 2. I didn't try to check it by resistor pulldown, > 3. HSWAP_EN=3D'1' or NC - must check it on schema at work, but not before > next tuesday :( > 4. Checked lines was V2-outputs/others chips inputs - not pulled/up/down > externally. > 5. M2=3D'1' M1=3D'1' M0=3D'0'. - Slave SelectMap mode. > > As I wrote earlier I'll be at work next tuesday, and I'll try to use > your advices. > I'll post results on this topic. > > Thank you once more. > Best Regards > > Jerzy Gbur Jerzy, I advise you to check out Xilinx Answer record 18277 http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=3D1&iCountryID= =3D1&getPagePath=3D18277 -NewmanArticle: 94218
Hi, I designed a 7th order FIR filter using MATLAB fdatool and obtained the VHDL code using the HDL Coder. I think that in the following part of the code there is a problem (Delay pipe line is an 8 element array, whose elements are 16 bit vectors. filter_in is a 16 bit vector): IF reset = '1' THEN delay_pipeline(0 TO 7) <= (OTHERS => (OTHERS => '0')); ELSIF clk'event AND clk = '1' THEN IF clk_enable = '1' THEN delay_pipeline(0) <= signed(filter_in); delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); END IF; END IF; This part simply shifts previous inputs and should be saving the new input (filter_in) into delay_pipeline(0) (which it does). However, after delay_pipeline(0) <= signed(filter_in);, it says delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6);. As far as I know, the statements in a process are sequential. So, if you change delay_pipeline(0) right at the beginning, isn't the old value of delay_pipeline(0) totally gone? Because, afterwards delay_pipeline(0) (its new value) is assigned to delay_pipeline(1). I think that the order of the statements needs to be changed like: delay_pipeline(1 TO 7) <= delay_pipeline(0 TO 6); delay_pipeline(0) <= signed(filter_in); so that the seven previous inputs are stored in the array elements with indices from 1 to 7 and the new(current) input is stored in the element with index 0. I couldn't be sure. Can anyone help me? It is very crucial to me that I understand it correctly. Thanks in advance... EmelArticle: 94219
All, The PCI standard is written to create and protect ASSP and ASIC device sales, and is specifically worded to prevent alternate solutions. Regardless, FPGAs find there way into many PCI applications. Austin Kolja Sulimma wrote: > Mike Harrison schrieb: > >>What's their definition of a discrete component..? >>I suspect they are talking about resistors etc. >>Does it actually say that each signal must go to a single chip ? >>If not, then I see no problems with >>signals going to different (buffer) chips. > > > Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > >>My understanding is that you can only load once each line that's it ... > > > That is bad enough. Why should a microswitch be a sginificantly lower > load to a signal than an FPGA or ASIC? An IDT quickswitch can have up to > 7pF capacitance. > > > "Section 4.4.3.4 Signal Loading > Shared PCI signals must be limited to one load on the expansion board. [...] > It is specifically a violation of this specification for expansion > boards to: > * Attach an expansion ROM directly (or via bus transceivers) on any PCI pin. > * Attach two or more PCU devices on an expansion board [...] > * Attach any logic [..] that "snoops" PCI pins. > * Use PCI component sets that place more than one load on each PCI pin: > e.g. separate address and data path components. > * Use a PCI component that hast more than 10pF capacitance per pin. > * Attach any pull-up resistors or other discrete devices to the PCI > signals, unless thay are placed *behind* a PCI-to_PCI bridge." > > > Kolja SulimmaArticle: 94220
>You could also move to ISE 8.1 ? >-jg I thought about that when I saw that the 7.1.04 update was something like 325 megabytes. I figured maybe a full download of 8.1 wouldn't be much bigger. But then I figured I'd end up having to learn a whole new user interface, or there would be some other bugs that would cause problems. Does 8.1 pretty much look like 7.1, so it wouldn't be too confusing to upgrade?Article: 94221
Emel wrote:
> I couldn't be sure. Can anyone help me? It is very crucial to me that I understand it correctly.
In that case, I would get a vhdl simulator and test the code.
-- Mike Treseler
Article: 94222In article <43bdc395$1@clear.net.nz>, no.spam@designtools.co.nz says... > > You do realize Xilinx has ABEL flows for their CPLDs ? > [ Scan for .ABL files, in their examples directories] > > You'll find the learning curve much shorter, and ABEL is fine > at the smaller end of the scale. I did realize that at first, but then I promptly forgot. :-) Besides, I really wanted to learn VHDL for when I progress on to bigger and better things.Article: 94223
In article <43bf7a85@clear.net.nz>, no.spam@designtools.co.nz says... Well, I've been trying to post with google groups, but I see that even after several tries my recent messages aren't showing up. Who knows, maybe someday they will make it here from google's servers. If you see multiple replies from me that are similar, that is why. Now I've downloaded and installed a proper newsreader so I shouldn't have to mess with google groups anymore. > You could also move to ISE 8.1 ? > -jg I thought about that when I saw that the update from 7.1 to 7.1.04 was something like 325 megabytes, and thought that maybe the full 8.1 download wouldn't be much more. But then I figured that I'd probably find a whole new user interface that I'd have to learn, or there would be other new bugs in the software, and I would just update to 7.1.04 and get my CPLD working. Does 8.1 look and work pretty much the same as 7.1?Article: 94224
I tried to post this yesterday through google groups and it looked like it went, but now it doesn't show so I'm posting again with a real newsreader... In article <Xhjvf.193181$V7.130092@news-server.bigpond.net.au>, spam@tritium.com.au says... > My guess is that you haven't defined which pin on the outside of your > CPLD is connected to which signal on the inside of your CPLD. You've > ended up with random signals to random pins, defined by the fitting tool > to whatever made it's life easiest. The mapping will change every time > you modify and resysnthesise the code. > > You need to add a .ucf file to your project with the signal->pin > mappings in it. I almost did that, but not quite. :-) The first time I got a project to go through the synthesize and fit I generated a programming file, and I was about to double click on Configure Device (iMPACT) and I suddenly thought "How does it know what pins I want my signals on?" :-) So I looked at the ISE quick start tutoral I had gone through a few weeks back when I first downloaded and installed ISE and figured out how to create UCF. I still need to figure out how to put timing stuff into the UCF so I an do proper timing based simulations. I went through the ISE 7.1 quick start tutorial, but maybe I should spend some time going through the full ISE tutorial...
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