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wtxwtx@gmail.com writes: > Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in > patent claims? Because patents are written to be legal documents, not engineering documents. Legal documents are written using traditions that have evolved over hundreds of years. Since patent examiners, lawyers, and judges all expect patents to be written in a certain way, if you submit an application that isn't written that way, you're just wasting money.Article: 93876
<wtxwtx@gmail.com> schrieb im Newsbeitrag news:1136243041.134288.208780@g44g2000cwa.googlegroups.com... > Hi Antti, > There is popular saying in China that if you visited the U.S., but have > never been in Las Vegas, you would be counted as one who has not > visited the U.S. Because Las Vegas is its crown. I have never been in > Las Vegas, but no sorry for it. > > I would like to say if you want to be a real ASIC/FPGA engineer, you > must read CPU86. Because it is the Bible in ASIC. It is the birth place > of full CPU industry. > > Thank you, Antti, for the excellent gift for new 2006. > > Weng > Hi Weng, thanks for the nice words - well those should be addressed to www.ht-lab.com ! I only wrote some review about the CPU86 anad am hosting some files for download. Antti PS I have been to Las Vegas.Article: 93877
Eric Smith wrote: > wtxwtx@gmail.com writes: > >>Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in >>patent claims? > > > Because patents are written to be legal documents, not engineering > documents. Legal documents are written using traditions that have > evolved over hundreds of years. Since patent examiners, lawyers, and > judges all expect patents to be written in a certain way, if you > submit an application that isn't written that way, you're just wasting > money. Again, that is what i call "patent-ese". Instead of "many" or "multiple" one sees "a plurality of". Like i said, follow the terminology and useage that you find in other patents that are closely related to your particular idea.Article: 93878
Hello, We'll have to design a new board which will have a PCIe interface. There will be a xilinx FPGA V2P or V4 because of PPC use, MGT needs and DDR interface. I read that FPGA SERDES were not fully compliant with PCIe. Can someone tell me on which points ? So if the solution is to have an external PHY, what would be the part that would be not too expensive and easily available ?? Thanks for your advises. Stéphane.Article: 93879
> hello friends, > > For better security, I am porting a design from Xilinx (Spartan3) to > Actel (ProAsic3E). The Actel part is very nice and works great. The > only problem i have had is that the design becomes bigger and slower > than expected. Now, I do understand that some parts of this design > translate to bigger logic on the Actel part. > obviously, i need to read more on the subject (and i have read a lot of > actel docs already). so please enlighten me with all your > actel-specific optimizations tricks, general optimizations guidelines > and any other information that may be useful. > > in fact, any material about coding style and area optimization is most > welcome. Well the part might be great, but it is tools & the part that give you the best solution. If Spartan 3 can't satisfy your security needs, you might consider Stratix II, which also has some nice features to solve both the optimization (ALM they call it) and the security issue (non-volatile 128-bit AES key) *and yes I am an Altera engineer*Article: 93880
"sjulhes" <t@aol.fr> schrieb im Newsbeitrag news:43ba2de0$0$7180$636a15ce@news.free.fr... > Hello, > > We'll have to design a new board which will have a PCIe interface. > There will be a xilinx FPGA V2P or V4 because of PPC use, MGT needs and > DDR > interface. > > I read that FPGA SERDES were not fully compliant with PCIe. > Can someone tell me on which points ? > > So if the solution is to have an external PHY, what would be the part that > would be not too expensive and easily available ?? > > Thanks for your advises. > > Stéphane. > Hi Stephane, some advice/hint 1) V4 RocketIO (eg MGT) have BETTER(does not mean FULL!) PCIe compliance then the V2Pro MGT 2) before doing any V4 MGT design, check that you can actually get V4 MGT production silicon in time for your project, if not then use V2Pro 3) there are 3 PCIe PHYs known to be somewhat available, Philips (Datasheet under NDA), TI (no info on TI web!!), Genesys - buy now button on hitechglobal but it only leads to 'call' not to online ordering, datasheet status unknown ---- NO PCIe is easily available 4) PLXtech PEX8111 1-lane to PCIe to PCI this possible the easiest solution, silicon available from online store 5) PLXtech PEX831 PCIe to local bus bridge, datasheet under NDA, also package is way larger than PEX8111 (I assume its multi-die BGA!) if you need MGT, PPC and relativly short time to market then my choice would be: V2Pro + PEX8111 Antti www.xilant.comArticle: 93881
"Karl" <karlIGNORETHISPART@chello.nl> schrieb im Newsbeitrag news:1136276112.311477.283990@g14g2000cwa.googlegroups.com... >> hello friends, >> >> For better security, I am porting a design from Xilinx (Spartan3) to >> Actel (ProAsic3E). The Actel part is very nice and works great. The >> only problem i have had is that the design becomes bigger and slower >> than expected. Now, I do understand that some parts of this design >> translate to bigger logic on the Actel part. >> obviously, i need to read more on the subject (and i have read a lot of >> actel docs already). so please enlighten me with all your >> actel-specific optimizations tricks, general optimizations guidelines >> and any other information that may be useful. >> >> in fact, any material about coding style and area optimization is most >> welcome. > > Well the part might be great, but it is tools & the part that give you > the best solution. If Spartan 3 can't satisfy your security needs, you > might consider Stratix II, which also has some nice features to solve > both the optimization (ALM they call it) and the security issue > (non-volatile 128-bit AES key) > > *and yes I am an Altera engineer* > and a good one you are - I did never realize that Altera did build in real non volatile key storage into S-II !! this means that S-II is not really RAM only technology and includes eeprom/flash technology on the same die as well, this is pretty nice as using external battery as it is required for key storage for Xilinx FPGAs is kind a pain -- Antti Lukats http://www.xilant.comArticle: 93882
Thank you for your answers. Well it seems that unless you are ATI or Nvidia having a PCIe board running is not that easy ! But I guess the first thing to check is what are these compliance differences on V4, to see if they are acceptable for this design. Can someone tell me where I can find information on this ? Thanks. Stéphane. "Antti Lukats" <antti@openchip.org> a écrit dans le message de news: dpdbrr$ofq$01$1@news.t-online.com... > "sjulhes" <t@aol.fr> schrieb im Newsbeitrag > news:43ba2de0$0$7180$636a15ce@news.free.fr... > > Hello, > > > > We'll have to design a new board which will have a PCIe interface. > > There will be a xilinx FPGA V2P or V4 because of PPC use, MGT needs and > > DDR > > interface. > > > > I read that FPGA SERDES were not fully compliant with PCIe. > > Can someone tell me on which points ? > > > > So if the solution is to have an external PHY, what would be the part that > > would be not too expensive and easily available ?? > > > > Thanks for your advises. > > > > Stéphane. > > > Hi Stephane, > > some advice/hint > > 1) V4 RocketIO (eg MGT) have BETTER(does not mean FULL!) PCIe compliance > then the V2Pro MGT > 2) before doing any V4 MGT design, check that you can actually get V4 MGT > production silicon in time for your project, if not then use V2Pro > 3) there are 3 PCIe PHYs known to be somewhat available, Philips (Datasheet > under NDA), TI (no info on TI web!!), Genesys - buy now button on > hitechglobal but it only leads to 'call' not to online ordering, datasheet > status unknown ---- NO PCIe is easily available > 4) PLXtech PEX8111 1-lane to PCIe to PCI this possible the easiest solution, > silicon available from online store > 5) PLXtech PEX831 PCIe to local bus bridge, datasheet under NDA, also > package is way larger than PEX8111 (I assume its multi-die BGA!) > > if you need MGT, PPC and relativly short time to market then my choice would > be: V2Pro + PEX8111 > > Antti > www.xilant.com > >Article: 93883
hi I have a question: what is the proper way to generate c slow clock. I have a spartan 3 development board with a 50 MHz external clock. What i need is a 4MHz clock for an SPI interface. Since the DCM's can only deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to devide this clock some more. how is this done properly? a counter? Or is ther any other sollution? Thanks UrbanArticle: 93884
"sjulhes" <t@aol.fr> schrieb im Newsbeitrag news:43ba3f51$0$7178$636a15ce@news.free.fr... > Thank you for your answers. > > Well it seems that unless you are ATI or Nvidia having a PCIe board > running > is not that easy ! > > But I guess the first thing to check is what are these compliance > differences on V4, to see if they are acceptable for this design. > Can someone tell me where I can find information on this ? > > Thanks. > > Stéphane. both V2Pro and V4 can be and have been used for working PCIe solution V2Pro requires external clock recovery V4 possible not any more there are other minor issues that are not a show stopper for MGT based PCIe design V4 MGT claim to have fixed most (all ?) missing PCIe compliance issues there are some docs about that on the xilinx web if you search really closely but for V4 MGT-PCIe first thing todo is CHECK production V4MGT availability !! after that it makes sense to check the tech specification , also consider the cost (both onetime license and FPGA % cost) for FPGA PCIe IP-Core -- Antti Lukats http://www.xilant.comArticle: 93885
"Antti Lukats" <antti@openchip.org> wrote in message news:dpdc4r$ga6$03$1@news.t-online.com... > this is pretty nice as using external battery as it is required for key > storage for Xilinx FPGAs is kind a pain > ...but the battery solution has the potential to be more secure than having a non-volatile key that can be found by dismantling the device. How much pain would there be if someone stole your design? Cheers, Syms.Article: 93886
"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag news:43ba4f5e$0$15794$14726298@news.sunsite.dk... > "Antti Lukats" <antti@openchip.org> wrote in message > news:dpdc4r$ga6$03$1@news.t-online.com... >> this is pretty nice as using external battery as it is required for key >> storage for Xilinx FPGAs is kind a pain >> > ...but the battery solution has the potential to be more secure than > having a non-volatile key that can be found by dismantling the device. How > much pain would there be if someone stole your design? > Cheers, Syms. generically, yes but if Altera did it correctly (key storage on-die not separate die inside the bga package, some other things to be done RIGHT) then its almost as safe as battery. correctly implemented nonvolatile storage for keys would be secure for almost all applications. -- Antti Lukats http://www.xilant.comArticle: 93887
>I have a question: what is the proper way to generate c slow clock. I >have a spartan 3 development board with a 50 MHz external clock. What i >need is a 4MHz clock for an SPI interface. Since the DCM's can only >deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to >devide this clock some more. how is this done properly? a counter? Or >is ther any other sollution? Is it really a clock? Are you clocking FFs and state machines with it? If so, you need to worry about skew. I'd expect it's just a signal named "clock" coming out of a FSM. Or maybe that's just the way I'm thinking of it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 93888
Hi,
we all know how to count to 10 right?
I did think I can at least until I did see how
a binary counter works in Spartan3e - I am still confused:
the code in FPGA is at the end of the message,
it really is a very normal counter and should count
0,1,2,3,4,5,6,7... ?
well it doesnt, it counts
0,5,2,3,4,1,6,7... !
I have verified this behaviour multiply times and its still
counting this weird sequence where 1 and 5 are changed.
strange thing is that when I load the FPGA after loading the
counter design with another known good bitstream then the
second design works incorrectly about half of the outputs
are not toggling. This only happens when configuring with
non-impact tools. When the 2 designs are loaded with impact
then the second works properly. The weird counter works the
weird way no matter what tool is used to load the FPGA.
So as a real new year surprise I have now really seen an
FPGA that gets configured with partial/damaged bitstream
and still starts and reports done=1
Any suggestions what is wrong?
Is my counter RTL code wrong?
I have tested the wrong count both from my program and with
impact in JTAG debug mode, it really really counts wrong.
It can be that the FPGA is internally damaged as it
was almost the only IC that survived after on-board
switching supply got holes into the plastic and
Strataflash failed to respond to QRY (partially damaged
still responds to ID read).
hum when I have known fabric failing FPGA then its
really nice to work on FPGA test patterns to see
if they catch the failure
Antti
--------------- cut here ---------------------
LED(6 downto 0) <= ADDR(6 downto 0);
Process_DRCK1 : process (DRCK1) is
begin
if (SHIFT='0') or (SEL1='0') then
ADDR <= "0000000000000000000000000";
else
if DRCK1'event and DRCK1 = '0' then
ADDR <= ADDR + "0000000000000000000000001";
end if;
end if;
end process Process_DRCK1;
Inst_BSCAN : BSCAN_SPARTAN3 port map (
TDO1 => TDO,
TDO2 => '0',
DRCK1 => DRCK1,
DRCK2 => open,
RESET => RESET,
SEL1 => SEL1,
SEL2 => open,
SHIFT => SHIFT,
TDI => open,
UPDATE => open
);
--------------- cut here ---------------------
Article: 93889A nice way is to generate a clock enable 1 in N from a counter and use in a outer IF statement to enable anything within any given process statement. The advantage of this is you can different effective clocks in one design but in reality a single clock. This avoids clock boundary crossing, and variable timing, issues that can get by generating a clock direct from a counter. Sometimes this will generate a slightly bigger logic size but not necessarily as the Spartan-3 flip-flop has effectively a clock enable built in. This enable is sometimes used by synthesisers in generating a function not immediately thought off as a clock enable but equally not and hence "free" to use. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Board. http://www.enterpoint.co.uk <u_stadler@yahoo.de> wrote in message news:1136280209.379940.143780@o13g2000cwo.googlegroups.com... > hi > > I have a question: what is the proper way to generate c slow clock. I > have a spartan 3 development board with a 50 MHz external clock. What i > need is a 4MHz clock for an SPI interface. Since the DCM's can only > deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to > devide this clock some more. how is this done properly? a counter? Or > is ther any other sollution? > > Thanks > Urban >Article: 93890
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dpdmcl$6rv$00$1@news.t-online.com... > Hi, > > we all know how to count to 10 right? > > I did think I can at least until I did see how > a binary counter works in Spartan3e - I am still confused: > the code in FPGA is at the end of the message, > it really is a very normal counter and should count > > 0,1,2,3,4,5,6,7... ? > > well it doesnt, it counts > > 0,5,2,3,4,1,6,7... ! > > I have verified this behaviour multiply times and its still > counting this weird sequence where 1 and 5 are changed. please dis-regard my prev. posting, it was incorrectly sent as reply and the issue with the counter seems to be solved it really is a damaged internal FPGA structure, by floorplanning the counter into different locations I can produce various types of wrong counting sequences. So issue solved I think. AnttiArticle: 93891
Hi Robert, It is interesting to note that the styles for patent writing are changing with time. In old patents, 'said' was used for 'the'. Now I found in more patents approved in 2005, they only use 'the', never use 'said'. It is very often now that a full sentence usually follows the 'wherein', instead of many separate words followed by descriptive words. Thank you. WengArticle: 93892
On a sunny day (2 Jan 2006 15:04:01 -0800) it happened wtxwtx@gmail.com wrote in <1136243041.134288.208780@g44g2000cwa.googlegroups.com>: >Hi Antti, >There is popular saying in China that if you visited the U.S., but have >never been in Las Vegas, you would be counted as one who has not >visited the U.S. Because Las Vegas is its crown. I have never been in >Las Vegas, but no sorry for it. > >I would like to say if you want to be a real ASIC/FPGA engineer, you >must read CPU86. Because it is the Bible in ASIC. It is the birth place >of full CPU industry. > >Thank you, Antti, for the excellent gift for new 2006. > >Weng > Is there any reason I should be interested in a segmented processor? And I have been in Vegas, tried a Dutch quarter in one of the slot machines, all alarms went of. Weird place. LOL ;-)Article: 93893
Did you set the "Clock Mode Register" corresponding to your single-edge/dual edge clocking ? And the "DVI PLL Filter Register" corresponding to your frequency ? Rgds Andr=E9Article: 93894
<ALuPin@web.de> schrieb im Newsbeitrag news:1136294247.789067.18020@g14g2000cwa.googlegroups.com... >Did you set the "Clock Mode Register" corresponding to your >single-edge/dual edge clocking ? And the "DVI PLL Filter Register" >corresponding to your frequency ? > >Rgds >André the clock mode is set properly, but I did not touch the DVI PLL Filter Register leaving at factory default thanks for suggestions Antti PS your email is non-responsive, please email me in privateArticle: 93895
"Antti Lukats" <antti@openchip.org> wrote in message news:dpdl5e$hhg$01$1@news.t-online.com... > "Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag > news:43ba4f5e$0$15794$14726298@news.sunsite.dk... >> "Antti Lukats" <antti@openchip.org> wrote in message >> news:dpdc4r$ga6$03$1@news.t-online.com... >>> this is pretty nice as using external battery as it is required for key >>> storage for Xilinx FPGAs is kind a pain >>> >> ...but the battery solution has the potential to be more secure than >> having a non-volatile key that can be found by dismantling the device. >> How much pain would there be if someone stole your design? >> Cheers, Syms. > > generically, yes > > but if Altera did it correctly (key storage on-die not separate die inside > the bga package, some other things to be done RIGHT) then its almost as > safe as battery. correctly implemented nonvolatile storage for keys would > be secure for almost all applications. > The key storage is on-die, so it matches what you want Antti. Vaughn Betz Altera v b e t z (at) altera.comArticle: 93896
When I try to generate a programming file for my FPGA project I get the following error: ERROR:Place:419 - The design contains 4 BRAM components that are configured as 512x36 BRAMs and 9 multiplier components. The multiplier site adjacent to the location of a 512x36 BRAM component must remain free because of ressource sharing. Therefore a device must have at least 13 multiplier sites for this design to fit. The currently chosen device has only 12 multiplier sites. Phase 1.1 (Checksum:98d993) REAL time: 3 secs I use XILINX ISE 6.3.03i. Is there a way to make my design fit inside the FPGA without reducing the number of multipliers?Article: 93897
Hi, different people at different ages have different meaning of FUN. Too my very surprise Xilinx Spartan3e Sample Pack has been proved itself to be fun for my younger son who is 3.5 years old and for myself. The Sample Pack comes with 2 designs loaded, first the running LEDs starts, on push of the button Dice game is loaded using the Multi Boot Feature. So while I was working with the board my son did come to look what I am doing, and he played with the board pretty long time showing real interest in it. I had the secondary design image in the top flash erased so each time my son triggered multi boot I had to reconfigure the FPGA manually with either the running LEDs or Dice game. I was doing it with Sample Pack standaalone utility that displays the LED status on screen in near realtime. So I explained to my son that the LEDs on the board are also displayed on screen so we pushed in turns and then looked to monitor to see the number of the Dice game. Also it was amazing to see how my son tried to figure it out, following the power supply cables from the board, then the JTAG cable from board to Cable IV and then to the PC. Like trying to follow the electrons without really knowing that. All this play did keep my son interested way beyound I would have expected. Actually I got tired before he did. So even if that Rotating LEDs + Dice game looked a bit silly for me at the first look, it is not so bad choice, at least those of us with kids may find that the Sample Pack entertainment level is pretty good. Now, lets see what fun has the board provided for me. First I did burn the board in with cheap power supply and had to replace the switching supply and the StrataFlash on the board. That wasnt fun. After that the board seemed to work. At least the running LED and Dice did work ok. But in the matter of fact the FPGA was damaged as well. After figuring it out that the FPGA fabric is really faulty Iimpact verify says 460000 bits out of 560000 have verify errors !!! I was able to rewrite my RTL code to be more fault tolerant and after that it works. So I fixed an faulty FPGA to work by re-implemnting a design. Doing that was FUN for me. I hope that Spartan3e can provide some fun times for all ages and levels of expertize. -- The faulty FPGA on my board doesnt mean that the Spartan3E are bad, actually it shows that FPGAs are very good and useable even on an board where almost all other silicon was severly damaged due to power surge. The FPGA survived at least partially and is still at least partially useable. -- Antti Lukats http://www.xilant.comArticle: 93898
Hi Antti, One month ago I sent a post asking for why Intel 386 uses at least 2 clocks for any instructions. Now I may have a chance to learn it from its internal structure. Even now the latest Intel chip reaches 4GHz, and numerous changes and inventions, but its basic principles are still there. I have read PC AT BIOS, DOS code, Keyboard code, Unix source code, C++ source files. All of them contributes to my deep experiences. CPU86 is not an exception. "You are taller after you stand on giants' shoulder." Who says this? Thank you again, Antti, for the excellent gift for the new 2006. WengArticle: 93899
<wtxwtx@gmail.com> schrieb im Newsbeitrag news:1136297256.268161.64320@g44g2000cwa.googlegroups.com... > Hi Antti, > One month ago I sent a post asking for why Intel 386 uses at least 2 > clocks for any instructions. Now I may have a chance to learn it from > its internal structure. > > Even now the latest Intel chip reaches 4GHz, and numerous changes and > inventions, but its basic principles are still there. > > I have read PC AT BIOS, DOS code, Keyboard code, Unix source code, C++ > source files. All of them contributes to my deep experiences. CPU86 is > not an exception. > > "You are taller after you stand on giants' shoulder." Who says this? > > Thank you again, Antti, for the excellent gift for the new 2006. > > Weng > Hi Weng, I have tried todo x86 IP-Core myself, but I had a totally different approuch the core I had was able to execute most instruction sequences up to 15 bytes long within 1 clock regardless of byte align by using special wide BRAM cache block for instruction storage, what I did is also available http://gforge.openchip.org I did not finish my core, the most of testing I ever did was to read SystemACE and display some data from it on TFT display on ML300 :) my code isnt much useful, but maybe that wide BRAM cache idea is -- Antti Lukats http://www.xilant.com
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z