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On 21 Nov 2005 13:58:11 -0800, "JustJohn" <john.l.smith@titan.com> wrote: > My original point is that the place/route tools do not analyse clock >setup and hold paths through an async reset. Assuming that you're talking about Static Timing Analysis tools (as opposed to P&R), this is not true in general. Definitely not true for standard cell flows and even in case of FPGA case, if you set the right parameters, it's not true. You maybe hiding it by not constraining your external reset pin with the clocks of the flops it arrives at. You can get around this by driving your async reset input of flops with a synchronized version of your reset pin. This way your internal reset signal is sourced by a clock and it is also helpful in that it reminds you to do this for every clock domain where reset is used.Article: 92076
hii > As I indicated, the synthese process converts the VHDL code into a > format applicable to the logic family. The synethesizer must be aware > of the resources available in the device, e.g. how many global clock > buffers are available, or are global resets available, etc. well, the synthesis report mentions everything, how many gclk, slices, lut's, multipliers.. according to that we have to modify the design. > If you are interested in the nuts and bolts of synthesis, a good place > to start may be in compiler algorithms as this is basically what the > synethizer is. i dint actually understand by what you said regarding compiler algorithms ... actually i was thinking of getting an idea the steps from coding till porting the code in the hardware.. if i can get this info on net... any material which will explain step by step after the coding and testing of the code in testbench till porting it on hardware. would be very greatful if u can suggest me with any link of a pdf file that can solve my problem... thanks TAKE CAREArticle: 92077
Hi, I'm intersting to know which architecture is used to create an IP cores : adder/substracter 6.0 ...Thanks.Article: 92078
Abbs schrieb: > ... > well, the synthesis report mentions everything, how many gclk, slices, > lut's, multipliers.. according to that we have to modify the design. > > ... > > i dint actually understand by what you said regarding compiler > algorithms ... actually i was thinking of getting an idea the steps > from coding till porting the code in the hardware.. if i can get this > info on net... any material which will explain step by step after the > coding and testing of the code in testbench till porting it on > hardware. > > would be very greatful if u can suggest me with any link of a pdf file > that can solve my problem... > Hi Abbs, if I understand your question right, you are wondering what the synthesis tool is making out of your source code. And you want to know this before synthesis, so you can estimate the effects of your source code on the synthesis result. Well, there's the IEEE synthesis standard for vhdl (IEEE 1076.6)that explains in detail what kind of hardware is generated from a synthesizable statement. This information is not vendor specific, and the synthsis tools often make use of vendor specific features when applicable, but it's a good start point. Another important thing is the setting of the synthesis tools options. e.g. in XST you can choose how many Clockbuffers should be used and wether BRAMS schould be used for logic or not and much more. Study these options and if you are still in doubt about some of your result put that small part of your project in a separated project and study the efffects of different coding styles and/or options by looking ath the RTL and Technology schematics created by the synthesis tool (the 7.1 rtl view sometimes misses to plot some inverters though) and compare these results. There's a lot to learn... have a nice synthesis EilertArticle: 92079
Hi, I've been using the uart_tx and uart_rx core EDIF's provided by Xilinx in xapp223. These are great for my Virtex-II development, and they obviously don't work for the Virtex-4. I like the simplicity of these cores and want to change as little of my old code as possible. Does anyone know/have a free/$ replacement to these EDIF's that work for the Virtex-4? -AndrewArticle: 92080
It has three rows of text printed on the back, and they are "TIOPA 690 3BZL9". I have this chip, but it was fixed to my board by some other people. Datasheet or any description that can help me is welcome.Article: 92081
On Tue, 22 Nov 2005 16:17:04 +0800, "Frank" <Francis.invalid@hotmail.com> wrote: >It has three rows of text printed on the back, and they are "TIOPA 690 >3BZL9". >I have this chip, but it was fixed to my board by some other people. > >Datasheet or any description that can help me is welcome. > does it look like this http://focus.ti.com/lit/ds/symlink/opa690.pdf ?Article: 92082
I have changed from Quartus II 4.2 to 5.1. Now I am getting much more
warnings ;-). My design works normally but the warning of the fitter I do
not understand:
Warning: Performance of this circuit may degrade because the Fitter
Delay Information is not loaded.
The Quartus Help says:
CAUSE: Certain devices are only used internally by either product
engineering or the timing modelling group. The Fitter Delay Information is
not built for such devices to save build time. This can also happen when the
user sets an INI that explicitly disable FDI loading.
ACTION: If an INI is explicitly set to disable FDI loading, try
removing it.
I can't find any setting for this. I'm using an APEX20KE EP20K200EFC672-3
which is not only "used internally" I think.
Please help, Manfred
Article: 92083Did you try generating same for Virtex-4 in Xilinx CoreGen?Article: 92084
hi again, I need this because I must know if the core -when designed- was optimazed for area or for delay .Article: 92085
A/ Forget the ASIC.. Design the FPGA.. then work out how to translate that
into an ASIC. The two are so totally different that if you try to design
for both you will ultimately fail.
B/ The double latch.....
clk_transfer : process (rst, clk) is
begin
if (rst = reset_active_c) then
tmp <= (others => '0');
data_out <= (others => '0');
elsif rising_edge(clk) then
tmp1 <= data_in;
data_out <= tmp1;
end if;
end process clk_transfer;
data_out = data_in after a little delay.
No doubt there will be debate to see if there should be a tmp2. I actually
have a standard block called meta_data and meta_clk which get called..
meta_data is for data signals.. i.e. static lines. meta_clk converts the
incoming signal to an edge which is phase aligned to meta_data.
The above is similar to these two routines.. but I can't guarantee it is
identical as they are at work and I haven't touched the blocks in a number
of years. (So I don't remember what's inside.. just that they work).
C/ See meta clock... I have an E1 card.. it has a 32.768 MHz, 2.048 MHz (E1
ref), 1.5432 MHz (T1 ref), 16.384 MHz, 4 x 2.048 MHz TX clocks and 4 x 2.048
MHz RX clocks. Only the 32.768 MHz and the two references are related...
all the rest are independent... So who said you need lots of clock lines?
Everything is "meta_clk" or "meta_data" up to the 16.384 MHz which is the
bus timing. The 32.768 MHz is used as a stable system reference along with
the E1 & T1 references. Also the 32 MHz is used to calculate the accuracy
of the 4 E1 ports by a simple long duration counter. The counter is
accurate to 1 ppm but the reference is good to 25 ppm. Room temperature
showed about 5-10ppm clock speed error :-)
So ... provided your "reference" is faster than you actually clocks, there
is no problems... just treat all clocks as edge generators which translates
into clock enables.
Simon
"huangjie" <huangjielg@gmail.com> wrote in message
news:1132568034.262632.53520@z14g2000cwz.googlegroups.com...
Thanks for your suggestion !
But first ,how to use "the infamous double latch" ?
second, my asic does not have only one 125M clk, instead it have 5
more ,
and all of them are input from external chip and have no any frequency
or phase
relations.
Simon Peacock ??:
> So clock everything at 125 MHz and use clock enables. Then use FIFO's or
> the infamous double latch to transfer between the 33MHz and 125Mhz clock
> domains.
>
> Simon
>
> "huangjie" <huangjielg@gmail.com> wrote in message
> news:1132535246.171569.78800@f14g2000cwb.googlegroups.com...
> > Unfortunatly,the clock does not slow enough,eg, one at 125M,pci at
> > 33MHZ.
> > Since they are interface to other device they can't slow down.
> >
Article: 92086If the Xilinx widow is minimized.. you should notice the window you are working in become responsive again :-) pop up windows are a strict no no.. Protel hates them, I have also had them pop up behind other windows... if you happen to click at the wrong time... or you just press return as the window pops up.. :-) Simon "Gabor" <gabor@alacron.com> wrote in message news:1132584267.548807.155370@f14g2000cwb.googlegroups.com... > > Fred wrote: > > "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message > > news:dlskc7$610$1@news.datemas.de... > > > On a sunny day (Mon, 21 Nov 2005 12:48:13 -0000) it happened "Fred" > > > <fred@nowhere.com> wrote in <4381c20e$0$23287$db0fefd9@news.zen.co.uk>: > > > > > >>I find it frustrating that there is no way or telling if a compilation has > > >>ended or not. I can't find any feature in ISE which makes a sound when > > >>it's > > >>finished. I am aware that some might find this an annoying feature but > > >>would save me periodically checking to see if it's finished or come to an > > >>end early due to a mistake. > > >> > > >>Any ideas? > > > I'd think that hanging a themocouple with level detector on the processor, > > > or heat exhaust, was a nice lunch 'time project ;-) > > > > > > In Linux you could use grep or awk on the output of 'top': > > > > > > CPU states: 0.5% user, 2.7% system, 15.4% nice, 81.1% idle > > > > > > look for > X percentage idle, and use keyboard beep: > > > echo -e "\a" > > > > > > .... > > > > > > > A utility to see if a file had been modified would be a possible method. > > I usually start the build by double-clicking "Generate PROM, ACE, or > JTAG File" > which will pop up an iMPACT window when finished. Sound would be > nicer, though > because I'm usually typing something when the window pops up and takes > over > the focus... >Article: 92087
What happened to the text on the front of the chip.. if its been "erased" then you are trying to reverse engineer a design.. that will void the warrantee :-) Simon "Frank" <Francis.invalid@hotmail.com> wrote in message news:4382d2ca$1@news.starhub.net.sg... > It has three rows of text printed on the back, and they are "TIOPA 690 > 3BZL9". > I have this chip, but it was fixed to my board by some other people. > > Datasheet or any description that can help me is welcome. > > >Article: 92088
there are async resets ... and async resets... In all the designs at work async resets are used throughout... except, as has been pointed out, where the result of the flip flop can be guaranteed after a few clock cycles. Where few is a debatable number. There is a big BUT to this... if the clock is continuous, then the async reset actually comes from a reset synchroniser, that is the clock using the reset generates the reset. If the clock is gapped (e.g. SPI clock) then the reset is async. And yes... there is one reset per clock line. My preference is to use the double latch system ... "rst_in" clears both latches and one latch cascades into the other.. shift register style... the result is the reset for that clock. Simon "Andy Peters" <Bassman59a@yahoo.com> wrote in message news:1132594075.241306.92660@g47g2000cwa.googlegroups.com... > Mike Treseler wrote: > > Hal Murray wrote: > > > I thought that consensus here was to use the global > > > reset hardware to (asynchronously) force your state > > > machines into a known state and then use a local > > > FF that has been synchronized to get out of that state. > > > > I don't think I'm contradicting that idea. > > The asynch reset gives you a starting > > point for simulation. After this, well-designed > > control logic will use an idle state for > > specific synchronous initialization. > > You're right, Mike; the async reset is helpful for simulation. Looking > back at my recent designs, I see a pattern. All of my state machines > have a safe reset state. A slow reset (where some of the state flops > reset before others) on a one-hot machine decodes as an illegal state > so the machine automatically bounces to the reset state. Once > everything is reset then the machine synchronously transitions to an > "idle" state where it stays until other logic tells it to do something > interesting. > > For things like loadable registers, the power-on reset is helpful, and > the usual template of > > myreg : process (clk, reset) is > begin > if (reset = '1') then > register <= INITVAL; > .... > > tells the synthesis tool to use INITVAL as the power-on default as well > as the async reset value. Ususally the rest of the logic doesn't > depend on these values, and the registers are loaded before they're > used. > > -a >Article: 92089
Depends who wore the core doesn't it ? If its the Xilinx core then it is optimised for the architecture you tell core generator to generate. Xilinx cores tend to be hand fitted to be the most optimal solution for the device. Simon "nezhate" <mazouz.nezhate@gmail.com> wrote in message news:1132652381.391939.181780@g47g2000cwa.googlegroups.com... > hi again, I need this because I must know if the core -when designed- > was optimazed for area or for delay . >Article: 92090
Try to edit the EDIF, change the part in the edif with virtex4, and give
it a try, it should retarget.
Aurelian
fad wrote:
>Did you try generating same for Virtex-4 in Xilinx CoreGen?
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 92091For generating the core I used coregenerator of Xilinx. I even searched for more references in their Datasheet and there is nothing. I generate this core (32 bits-adder unregistred) in order to design an other 32 bits adder with 3 input ports, then I must optimize it.Article: 92092
nezhate schrieb: > For generating the core I used coregenerator of Xilinx. I even searched > for more references in their Datasheet and there is nothing. > I generate this core (32 bits-adder unregistred) in order to design an > other 32 bits adder with 3 input ports, then I must optimize it. > In xilinx FPGAs there aren't really any architecture options for single cycle adders. The special carry chain hardware is so much faster per bit than LUT-logic that the break even point between carry ripple adders and more sophisticated adder architectures happens at relativly large bit counts, if ever. Kolja SulimmaArticle: 92093
It sounds like you use a device in your project that the new version of quartus is claiming wasn't meant to be synthesized into real logic, rather than claiming that your APEX device wasn't meant to be used. Did you try searching in Altera's online knowledge base?Article: 92094
Andrew Lohbihler wrote: > > I've been using the uart_tx and uart_rx core EDIF's provided > by Xilinx in xapp223 <snip> >Does anyone know/have a free/$ replacement to these EDIF's > that work for the Virtex-4? > see Ken Chapman's old post pointing to the VHDL equivalent of the XAPP223 UARTS, which can be found in the Picoblaze sources: http://groups.google.com/group/comp.arch.fpga/msg/0d3017a2beb810fd BrianArticle: 92095
[F'up2 cut down to single group --- should have been done by OP.] In comp.arch.embedded Simon Peacock <simon$actrix.co.nz> wrote: > What happened to the text on the front of the chip.. if its been "erased" > then you are trying to reverse engineer a design.. that will void the > warrantee :-) And it may void all your "get out of jail free" cards, too. Most people consider that the more serious danger. -- Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de) Even if all the snow were burnt, ashes would remain.Article: 92096
"Simon Peacock" <simon$actrix.co.nz> wrote in message news:4382ea2a$1@news2.actrix.gen.nz... > What happened to the text on the front of the chip.. if its been "erased" > then you are trying to reverse engineer a design.. that will void the > warrantee :-) > > Simon > > It stands for TI Op Amp, chip number 690.Article: 92097
Hello,
I just got a new FPGA board (from Avnet, Xilinx Virtex4). The problem is
that I never programmend a FPGA before. I use VHDL for programming and
Precision from Mentor for synthesis. Xilinx ISE 7.1 is used for
place-and-route. On the FPGA board is a push button. Within my VHDL code I
defined a process, which is sensitive to the rising edge of the signal
associated with that push button (I want to know, when the button is
pushed).
pb_proc: process (push_button) is
begin
if push_button'event and push_button='1' then
....
The problem is, that Precision recognizes that signal and the associated pad
as a clock input and the during place-and-route operation, ISE produces the
following error message:
ERROR:Place:645 - A clock IOB clock component is not placed at an optimal
clock IOB site The clock IOB component <push_button> is placed at site
IOB_X2Y112. The clock IO site can use the fast path between the IO and the
Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If
this sub optimal condition is acceptable for this design you may set the
environmentvariable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this
message to a WARNING and allow your design to continue.
If I use the following constraint during synthesis, the error is reduced to
a warning, but the input is still regarded as a clock.
set_false_path -through { push_button } -design gatelevel
My questions are:
1) Is every input signal, to whose signal flanks the VHDL code is sensitive
to, automatically a clock? What's the best way to prevent this during
synthesis? Do I actually have to prevent it?
2) How can I set the environmentvariable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING?
I'm using the Linux version of ISE and using ISE from within Precision. I'm
sure that there is a menu entry to set that variable, but I don't start ISE
direct, but from within Precision. So I'd like to know in which
configuration file I can place that variable setting. Also I'd like to know
which additional environmentvaribles exist. I couldn't find a list or
anything in the documentation.
Thank you,
Andreas
P.S.: another question of topi: When I setup my Design, I have to chose
technology(Virtex-IV), Device(4vlx25ff668) and Speed Grade(-10 or -11).
Which speed grade do I have to choose? Does the board support -10 and -11?
Whats better? What is the speed grade exactly? Do I have to/Can I determin
the supported speed grades of my board somehow?
Article: 92098Manfred, This warning does not apply to families prior to Stratix. The appearance of this warning will, in no way, alter the performance or run-time of your compilation. This warning will be removed in the next Quartus II service pack (i.e. 5.1 SP1). - Mark [mbourgea (at) altera <dot> com]Article: 92099
We currently use a software application (called DataCaptor) to read the MIB-RS232 output of a patient monitor (the Philips MP30). We are considering replacing the DataCaptor software with an FPGA but this has probably never been attempted. Does anyone have any experience interfacing an FPGA to patient monitors? Thank you.
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