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Hi All, If any of you folks know how, to calculate the best case timing parameters for a Xilinx FPGA (for eg: Global clock to out -- the pin to pin output parameter ) ? Googling through the archives , I came across this post from Austin Lesea posted in 2001. Article: 37740 "We did not tend to specify minimums (although we do now, more and more in the newer parts) because it wasn't supposed to matter. Now that it does, we do provide that information once the process is stable (the part is in manufacturing as a regular product, not ES material)...." But the device data sheets for a very much in production device like Virtex-II Pro doesn't provide any best case /Min values for the clock to out parameter. Also ,Another document that gives a lot of info. about approximating the best case timing is the xcell article http://www.xilinx.com/xcell/xl21/xl21-40.pdf . But, is this document relevant for the latest Xilinx FPGAs ? Thanks, AjayArticle: 91601
Somebody has some of the old parts up for auction on eBay, if you are interested: http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=7561910161 DerekArticle: 91602
I think I wrote that article in XCell. If you follow the reasoning, you will agree that it has to apply to all CMOS manufacturing. It is not even Xilinx-specific. Assuming the best-case (min) delay to be a quarter of the worst case (max) delay still seems to be a conservatively realistic assumption. My real question is: Why do you care? What are you gambling on? Min delays do not matter in a synchronous design. Peter Alfke, Xilinx ApplicationsArticle: 91603
Hal Murray wrote: >> I'm currently doing some research into Intellectual Property for SoC >> designs and just wanted to get a feal for the things that are important >> to people who actually purcahse/use IP. For example support from the >> vendor after sale seems to be important from people I have already >> spoken to. > > The top of my list would be a clean design. In particular, the > interface to your block of logic. Correctness is important, and also clear and correct documentation. (You would think this was implied, but...) JeremyArticle: 91604
Peter - On 9 Nov 2005 11:30:24 -0800, "Peter Alfke" <peter@xilinx.com> wrote: >I think I wrote that article in XCell. >If you follow the reasoning, you will agree that it has to apply to all >CMOS manufacturing. It is not even Xilinx-specific. >Assuming the best-case (min) delay to be a quarter of the worst case >(max) delay still seems to be a conservatively realistic assumption. > >My real question is: >Why do you care? What are you gambling on? >Min delays do not matter in a synchronous design. Sure, they do. You need them to calculate hold margins. Even if the receiving device's hold time is zero (and sometimes it isn't), you need to ensure that clock skew doesn't exceed minimum path delay. I'm not just trying to be picky here--this is important. Bob Perlman Cambrian Design WorksArticle: 91605
Terradestroyer@gmail.com wrote: > Strange request but I'm looking for an fpga board that pretty much only > has an fpga (perferably xilinx because i've only worked with xilinx so > far) a prom and just a whole lot of i/o pins that are easily > accessible. > I've done all i can on my protoboard (digilent spartan 3 board) and now > i need to move to a more finished device. Problem is designing such an > intricate pcb (espically with bga) for someone who hasn't done bga > stuff before but requires many i/o pins and have never done a board > more than 2 layers is leaving me a little challenged. So I'm hoping a > small board that will give me most of the I/O's in headers would be > available, but as of yet I haven't found any. > Does any know any that exsists? Not exactly pin headers, but the zefants are worth a look: http://www.zefant.de/en/index.php -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 91606
Peter Alfke wrote: > I think I wrote that article in XCell. > If you follow the reasoning, you will agree that it has to apply to all > CMOS manufacturing. It is not even Xilinx-specific. > Assuming the best-case (min) delay to be a quarter of the worst case > (max) delay still seems to be a conservatively realistic assumption. > > My real question is: > Why do you care? What are you gambling on? > Min delays do not matter in a synchronous design. On the same die, probably not, in absolute number terms, but some min delay is necessary. However, move across die and process, and it can become important if some devices HOLD times have finite post-edge windows. -jgArticle: 91607
Hello, how can I initialize a 8k*8 Block RAM with an Intel Hex-File? Thanks for any hint. UdoArticle: 91608
Yes, I agree. Inside the chip, we make sure that the delay tolerances on a global clock are less than the min delay clock-to-Q, and we can guarantee that, since delays track inside the chip. Between chips, the min delay is important since the clock delay differences are determined by the pc-board, and the transmitting device may also have nothing in common with the receiving device (neither temperature nor processing, although probably voltage). That's why source-synchronous design is now popular (sending the clock together with the data) and IDELAY in Virtex-4 gives you the ability to delay clock or data by a precise amount, so that you can achieve near-optimal relative timing. Peter AlfkeArticle: 91609
Vanheesbeke Stefaan wrote: >"Philip Freidin" <philip@fliptronics.com> wrote in message >news:kjp2n1hrhl6jvmldnbapl8mjcd3hs0v202@4ax.com... > > >>While this may not be what you want to hear, you may be better off >>figuring out your desired function, and starting a new design with >>current products. This is not easy either, as you probably have >>existing boards, and everything runs at 5V . There are no current >>products that will fit into the old footprint of the 3020A, and >>almost none of the current products tolerate 5V. >> >> >> > >The bad thing is that we need a last production batch of 500 pieces for >spare parts, the project is dead already for some time ... > > > > > If you only need 500 parts, one last time, and never again, have you checked all the "obsolete parts specialists"? There are outfits that have huge stocks of old Xilinx parts. I don't use parts this old, but still use some 5 V original Spartan chips, and these outfits have been quite helpful. Highmont in Australia was the last outfit I used. JonArticle: 91610
JASH wrote: >Hi... >I am having a quite similar issue... >I am using FPGA board Gigilent XS10... with xilinx spartan >FPGA.XCS10... >I used FS 1.5e and FS2.1E... But then I downloaded web pack 6.xx. >Surpeise was that this version didnot supported Spartan XCS10, not even >Spartan -II.... I wish Xilinx Management should think on that, although >they have made the components obsolete, but poor people like us are >still learning on the same... >Well then... what to do next... What i did was a little nasty.... >Webpack 6.xx supported Vertex - II... And so did previous version FS >3.3 (which a good man donated me). I made my design in 6.xx on device >V-II, opened the project in FS 3.3 and then changed the device to >Spartan XCS10-PC84..... It worked... Just remenber that keep the gate >count under final target device.... and configure the pinouts in each >implementation repeatedly..... >If u have XNF file it should work... but can you send me little more >detail on versions... I am a little shaky in understanding your >requirements. > > Wow! This is an amazing discovery! I've been using a 1997 or so version of ISE so I can keep support of the old 5V parts. JonArticle: 91611
Henry wrote: >I'm looking for some suggestions/recommendations with CPLD's and development >software. > > > >I'm new to CPLD's and a couple projects of mine will involve redesigning >existing "though hole" hardware using a CPLD. I've researching some Xilinx >products, and believe the 9500 series will do everything I need, as my needs >really aren't that great. My only issue with the ISE software is I need to >recreate all the TTL IC logic from scratch, which will prove to be very time >consuming. I was hoping to find a design package that would already have >existing "groups" of TTL logic designed so I won't have to take as much time >with the schematic design and layout. For example in ISE it took me about >15 minutes just to draw the logic to a 74LS245. Only took me 3 minutes to >"wire" it up. > > > >Any recommendations on other companies, other software and your experiences >with them would be appreciated. > > Hmm, I'm pretty sure the version of ISE I am using has a library of "X74xxx" parts. It does not have all of them, just a representative selection. But, I have implemented a lot of simple control interface circuits using the 9500 series this way. Look through the libraries provided for X74 parts, they may be at the very end of a HUGE list. You may also have elected to not install those libraries when you installed the ISE package. I just checked, and the x74_245 is not in the list, but it is a pretty simple device, and can be replaced with a buft8 and a bufe8, I think, depending on how the enable pin is used. Many of the counters, decoders, encoders and other more complex functions ARE included in the TTL schematic library. This is in Ver 4.2i, one of the last to support the 5V parts. JonArticle: 91612
Dave Roberts wrote: >Hello, > >I'm trying to force a long logic delay in a Xilinx FPGA using a chain of >inverters. However, these seem to get optimised out of the design. Can >someone tell me how to specify that certain signals are not to be optimised? > > > There's supposed to be a "keep" option that prevents signals from being optimized away. It seems, though, that unless the signal with the "keep" directive is connected to an external pin, it gets optimized away anyway. As long as you have spare pins, you can send the signal to an I/O pin, and then read it back from the same pin. For longer delays, I have used a resistor between two pins, using the capacitance of the input pin as the C of an R*C time constant. You can get delays up to microseconds this way, but I usually use it for delays under 20 ns. This is essential with some interface CPLDs where there is no clock whatsoever except the strobes from the bus. JonArticle: 91613
You can also try syracusesemiconductors.com or call them at 603-897 1280 and ask for Joe. Very helpful guy. Peter AlfkeArticle: 91614
Hello, I am able to compile the kernel succesfully. Now I have one more problem. I load the bit file and download the kernel. The following screen appears on my minicom and then goes dead. Enter Desired System ACE CF Configuration <0-7>. 0: ACE-loader. 1: Linux w/PCI. 2: VxWorks w/PCI. 3: QNX Demo. 4: Linux EDK Base Build. 5: VxWorks EDK Base Build. 6: User Configuration A. 7: User Configuration B. Select: loaded at: 00400000 008CB1E0 board data at: 008C8138 008C8150 relocated to: 00405308 00405320 zimage at: 00405813 004DE42A initrd at: 004DF000 008C7382 avail ram: 008CC000 10000000 Linux/PPC load: console=ttyS0,9600 root=/dev/xsysace/disc0/part2 rw Uncompressing Linux...done. Now booting the kernel It gets stuck on booting the kernel. Any suggestions.... Thanks NiteshArticle: 91615
As posted above, Ethereal can detect any frame if the capture and display filters are clear... but it assumes that the NIC card in your machine actually receives/accepts the packet. If the packet must meet the minimum and maximum size requirements (try 70 bytes for example) and has a proper FCS. You may be able to configure your Ethernet board to accept error packets, which might help troubleshoot the problem. You didn't say which OS you were using, if you were capturing in "promiscuous" mode (may require admin rights), and if you have a direct (cross-over) connection or are going through a switch or hub. Have you verified that you can receive the 'same' frame if it is sent via a different source (not your FPGA)? "ashwin" <achiluka@gmail.com> wrote in message news:1131549976.998254.72060@f14g2000cwb.googlegroups.com... > Hello everyone, > I am trying to implement ethernet MAC on a fpga using vhdl. I have a > transmit module which generates the ethernet frame and transmits to the > PC through the ethernet cable. > The ethernet frame consists of preamble, sfd, destination(MAC), > source(MAC), length,data,crc. I am using ethereal to detect this frame > > I definitely think that my crc is right. But i am not able to detect > any frames in the ethereal. > I understand that by default ethereal has been set to detect ethernet > frame of layer 3 or above. > > But the ethernet frame which i am sending is layer2. How do i change > my options in ethereal so, that i can detect this type of frame. > > Ashwin >Article: 91616
Hello, I currently work on Rocket IO in vertex II pro with eval board. I succeed loopback test in parallel mode, but when I extend to the serial path, it didn't work quite well. In particular, When push the reset button, everything become chaos. So, I have to push it several times to get the system back. Once it get back, it receives data correctly. I couldn't find the mistake. I terminated SMA and gave reset signal after dcm phase is locked. Does anybody has any reference code to start with ? Any inputs will be appreciated. Jdon.Article: 91617
I wrote: > The problem is that you don't save any significant cost by having the > same size package with fewer balls or pins. So if the die size requires > a package 20mm on a side, it may as well have more than 350 balls, even > if some customers don't end up using all of them. Tobias Weingartner wrote: > There is a cost associated with me trying to acquire the resources and > planning necessary to have a 1000+ pin FPGA mounted, routed and fed. On > the other hand, 144 pins, or even 208 pins in a quad flat pack is pretty > much doable... Sure, but if the part doesn't fit in the die cavity of the package, it ain't gonna happen.Article: 91618
Hi Parag , I am using 2.4.26 kernel. I am also trying it with the monta vista preview kit as told by peter. I will try the pci example with the montavista kernel. For the pci parameters eroor what I did was I copied the parameters from the xparameters_ml300.h file patch given by Andrei Konovalov on http://galileo.gamepoint.com.au/pub/linux/kernel/people/akpm/patches/2.6/2.6.9-rc4/2.6.9-rc4-mm1/broken-out/ppc32-xilinx-ml300-board-support.patch NiteshArticle: 91619
I am outputting a data with a clock 12.5MHz, which will latch the data into external chip whose input delay is unknown. I am trying to connect eight FPGA IO pads to the same clock, and delay each of them 1/8 of my main clock period, i.e. 10 ns, expecting one of them will work correctly. What constraint can I use in UCF file? Thanks in advanceArticle: 91620
"Frank" wrote: >I am outputting a data with a clock 12.5MHz, which will latch the data >into external chip whose input delay is unknown. I am trying to connect >eight FPGA IO pads to the same clock, and delay each of them 1/8 of >my main clock period, i.e. 10 ns, expecting one of them will work correctly. >What constraint can I use in UCF file? Not the right way to solve the problem, as the delay can vary by a lot depending on part, VCC and temperature. For a suggestion of better idea, first, what part? Second, what other clocks do you have available? If you have a 50 MHz clock available, the design can move an output by 10 ns by just changing the clock edge, and by 20 ns by delaying to the next clock. A "DCM" might help as well. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 91621
Frank wrote: > I am outputting a data with a clock 12.5MHz, which will latch the data > into external chip whose input delay is unknown. I am trying to connect > eight FPGA IO pads to the same clock, and delay each of them 1/8 of > my main clock period, i.e. 10 ns, expecting one of them will work correctly. > What constraint can I use in UCF file? > > Thanks in advance > > > Hi Frank, I guess you want to be able to constrain the maximum clock to data delay of your FPGA output. If not ignore this message :-) You can use the OFFSET - OUT - AFTER constraint in the UCF file to do that. eg. NET "<data_output_pin>" OFFSET = OUT 5 ns AFTER "<Clock_Pin>" HIGH;Article: 91622
My mistake, MultiLINX runs from 2.5V - 5.0V, thus 3.3V solves my problem. "Francis" <FrancisChee@h0tmail.cxm> wrote in message news:dkssgd$b2b$1@reader01.singnet.com.sg... > I am using MultiLinx to program my XC2V1000 thru JTAG connector. > I got TMS, TCK, TDI, TDO correctly, but unable to find the 3.3V and GND. > Without this 3.3V, I can detect devices on two out of three JTAG ports on my > board, and I need the third port to work. > > I am applying a 2.5V on the PWR & GND of the SelectMAP(?) connector on > my Multilinx and it drew 0.9A power. I am unable to find another power > supply > to make 3.3V now. :( > > What can I do with this situation? > > Thanks > > > >Article: 91623
Do you have a faster clock available (50 MHz or 100 MHz) ? Are you sending data to a latch or to an edge-triggered flip-flop or register? With a flip-flop or register, just use the opposite clock polarity, i.e. the clock edge that did NOT generate the output data. That edge is 40 ns later than the data change, and that should be a very safe margin. Peter Alfke, Xilinx ApplicationsArticle: 91624
"Kunal Shenoy" <kunal.shenoy@xilinx.com> wrote in message news:dkud96$sp91@cliff.xsj.xilinx.com... > Frank wrote: > > I am outputting a data with a clock 12.5MHz, which will latch the data > > into external chip whose input delay is unknown. I am trying to connect > > eight FPGA IO pads to the same clock, and delay each of them 1/8 of > > my main clock period, i.e. 10 ns, expecting one of them will work correctly. > > What constraint can I use in UCF file? > > > > Thanks in advance > > > > > > > Hi Frank, > I guess you want to be able to constrain the maximum clock to data delay > of your FPGA output. If not ignore this message :-) > You can use the OFFSET - OUT - AFTER constraint in the UCF file to do that. > eg. NET "<data_output_pin>" OFFSET = OUT 5 ns AFTER "<Clock_Pin>" HIGH; Thank you, I used to think OFFSET gives a maximum delay, which means an offset value of 60ns or 70ns gives same result, since the real offset is 50ns. Am I right? I will try out this OFFSET technique.
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