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You can use the attribute syn_keep in your HDL source to preserve a net for later use with timing constraints. jacob.bower@gmail.com wrote: > Does anyone here know if it is possible either using XST or Synplify > Pro to flag a small number of specific nets to be ignored timing-wise > in future place and route without preserving heirarchy during > synthesis? > > Currently I'm using TIGs in my UCF file, but by the time the design has > gone through XST/Synplify the nets I need to flag have dissapeared and > my design is unrouteable. If I turn on heirachy preservation though, my > design doubles in size and overmapps my target FPGA. > > Any help appreciated. > > Thanks. >Article: 99251
Hi Gang ! I am using ISE 8.1sp2 and ISE 7.1sp4 (same challenge with both versions). I have an output bus, looks like this: FF->Comb. Logic->IOB This is a 8 bit bi-directional bus, and I am having a rally hard time meeting timing on it. I am convinced that the FPGA can actually do it, but I think I am not using the tools properly to their fullest capability. The clock period for this bus is 16.6nS, the UCF file looks something like this: NET "phy_data<*>" OFFSET = OUT 8.8ns BEFORE phy_clk; The mapper thinks there is no timing problem, and reports: COMP "phy_data<6>" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.615ns | 0.815ns COMP "phy_data<2>" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.631ns | 0.831ns COMP "phy_data<4>" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.943ns | 1.143ns COMP "phy_data<3>" OFFSET = OUT 8.8 ns BE | -8.800ns | -9.982ns | 1.182ns COMP "phy_data<5>" OFFSET = OUT 8.8 ns BE | -8.800ns | -10.045ns | 1.245ns COMP "phy_data<7>" OFFSET = OUT 8.8 ns BE | -8.800ns | -10.069ns | 1.269ns COMP "phy_data<1>" OFFSET = OUT 8.8 ns BE | -8.800ns | -10.131ns | 1.331ns FORE COMP "phy_clk" | | | (slightly edited to fit better) However, after P&R I get (in the par report): * COMP "phy_data<6>" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.362ns | -0.438ns * COMP "phy_data<2>" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.634ns | -0.166ns * COMP "phy_data<4>" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.667ns | -0.133ns * COMP "phy_data<5>" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.753ns | -0.047ns * COMP "phy_data<3>" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.783ns | -0.017ns COMP "phy_data<1>" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.849ns | 0.049ns COMP "phy_data<0>" OFFSET = OUT 8.8 ns BE | -8.800ns | -8.936ns | 0.136ns FORE COMP "phy_clk" | | | (slightly edited to fit better) I tried several different options for the tools, like setting the overall effort to high, but it seems not to help. It seems to me that it is a P&R problem, but if I could somehow tell the mapper to try to give me more slack on these IOs, it would also help. What strategies, options, tricks, would you guys recommend for this problem ? I would really like to avoid using the FPGA editor and guide files, if at all possible. The device is xc4vlx25, package sf363, speed -10, and is about 1/2 full with this design. All IOBs are locked. Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ******Article: 99252
Hihi, I was thinking about that at the time of the first announcement (a few months ago), but well I will sure look at it, and decide what todo (if). but funny you asked, I am considering adopting some micro for one specific FPGA right now, but it would need to fit with SDRAM controller into 3000LUTs and there must be uclinux support for it. its very tight if doable using existing cores so I may end up re-writing something AnttiArticle: 99253
Hi, I'm trying to do implement a buffer in Virtex II pro. My system has 8 bits 100 Mbps as an inputs and 16 bits 2.5Gbps as an outputs. Since size of inputs and outputs are different, I couldn't use asynchronous fifo which virtex provides. Does anyone have any reference I can start with? Dual port BRAM looks fine but data got distorted on simultaneous read and write process, because each process working at a different clock. Any comments will be appreciated. Jdon.Article: 99254
The simplest solution is to make the whole asynchronous FIFO 16-bit wide, and build a simple synchronous "pre-assembler" that composes a 16-bit input from two successive 8-bit inputs. CoreGen does the rest for you. Peter Alfke, Xilinx (from home)Article: 99255
Hi Mike,
Sorry for the vague code, below is a more complete version:
...
PROCESS (clock)
variable msgNum: Integer := 1;
BEGIN
...
for i in 1 to msgNum-1 loop -- this statement generates an
error "variable cannot
-- be used for range"
when generating power
-- report using
Xpower (possibly during synthesize)
...
end loop;
...
end process;
end architecture arch;
Any solutions would be greatly appreciated. Thanks
ywz
Article: 99256Thanks. But the problem of the asynch-FIFO 16 is that I couldn't prevent simultaneous read and write. When the process tries to read and write at the same time by chance, the output is distorted. How could I prevent this? "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1143007400.912744.78060@i39g2000cwa.googlegroups.com... > The simplest solution is to make the whole asynchronous FIFO 16-bit > wide, and build a simple synchronous "pre-assembler" that composes a > 16-bit input from two successive 8-bit inputs. CoreGen does the rest > for you. > > Peter Alfke, Xilinx (from home) >Article: 99257
Thanks. But the problem of FIFO16 is that I couldn't prevent simultaneous read and write. When the process tries to read and write FIFO at the same time by chance, the output is distorted. The 'empty' signal doesn't much help, because the speed difference of input and output clk is large(about 10 times). How do I prevent it? "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1143007400.912744.78060@i39g2000cwa.googlegroups.com... > The simplest solution is to make the whole asynchronous FIFO 16-bit > wide, and build a simple synchronous "pre-assembler" that composes a > 16-bit input from two successive 8-bit inputs. CoreGen does the rest > for you. > > Peter Alfke, Xilinx (from home) >Article: 99258
ywz.oct13@gmail.com wrote:
> Sorry for the vague code, below is a more complete version:
1. You don't need a declaration for
an integer loop variable, and I
expect that commenting that line will
eliminate the error.
-- variable msgNum: Integer := 1; -- comment out this line
2. Note that variable and signal
initializations are ignored
for synthesis.
-- Mike Treseler
Article: 99259On 2006-02-01, Sean Durkin <smd@despammed.com> wrote: > Instead, I suggest buying a Platform USB cable. Gives you much less > trouble in the long run, and works well on every modern machine. > ... if you can afford it, that is. I think it's $150, so about double > what the parallel cable costs. Plus, I'm not sure if it works under > Linux, but there have been discussions about that here lately. My latest experience is that it works in Linux, but only if you start impact in Windows first to initialize the firmware in the programming cable. If I don't boot Windows first, impact in Linux wants to upgrade the CPLD configuration which according to other posts on this newsgroup will break the programming cable. To be honest, at this point I prefer to use XC3SProg http://www.rogerstech.force9.co.uk/xc3sprog/index.html in Linux. Sure, it is rather slow since it uses the parallel cable IV in cable III mode, but it feels much more stable in Linux than impact does. /AndreasArticle: 99260
On 2006-03-20, GHEDWHCVEAIS@spammotel.com <GHEDWHCVEAIS@spammotel.com> wrote: > Hi, > > I bowsed through some threads about using the various Xilinx > programming cables. It seems like with my Linux notebook without a > parallel port I am doomend and not able to use any of them. > > At the moment I have a parallel cable IV and from what I read there is > no way that I will be able to use that with the notebook, even when > booting it with Windows, as no USB-to-Parallel adapter will work with > it. The notebook does not have a PCMCIA port, so such a parallel > adapter will not be an option either. > > Concerning the new Xilinx Platform USB cable I read that it does not > work under Linux, so here the only option would be to boot the notebook > with Windows to get that going. > > Is there really no way to get the parallel cable going with a > USB-to-Parallel adapter? I would try XC3SProg before giving up on the parallel cable. My feeling is that it might work since it uses system calls to set the parallel port instead of bit banging directly to the IO ports: http://www.rogerstech.force9.co.uk/xc3sprog/index.html /AndreasArticle: 99261
Roger Bourne wrote: > Hello all, > > Concerning digital filters, particurlarly IIR filters, is there a > preferred approach to implementation - Are fixed-point preferred over > floating-point calculations ? I would be tempted to say yes. But, my > google search results leave me baffled for it seems that floating-point > computations can be just as fast as fixed-point. > Furthermore, assuming that fixed-point IS the preferred choice, the > following question crops up: > If the input to the digital filter is 8 bits wide and the coefficents > are 16 bits wide, then it would stand to reason that the products > between the coefficients and the digital filter intermediate data > values will be 24 bits wide. However, when this 24-bit value is to get > back in the delay element network (which is only 8 bits wide), some > (understatemen) resolution will be lost. How is this resolution loss > dealt with? so it will lead to an erroneous filter? Since together with the decision to have float or fixed, the next question which is at least as important is how many bits you need. while the float part takes over the exponent adjustment, speak the shifting to the left or right, the number of bits in the mantissa or as fixed determine the dynamic range of your result. When the pressure to save some macrocells is there, then you should have a closer look what happens when you omit how many bits at what operation. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net *** Free account sponsored by SecureIX.com *** *** Encrypt your Internet usage with a free VPN account from http://www.SecureIX.com ***Article: 99262
santhosh_h_98@yahoo.com wrote: > Thanks for the answer. This works but this has a big problem. > Even if I have 2 AND gates in a design, when I export this as .eps > file, using the method you mentioned, and insert in LATEX it takes one > complete page. > > How can I copy just the part of the drawing as an .eps file ??? > > Please help. > Sant in ghostview you can export parts of a ps/eps file as an eps file, I'd guess you already have ghostview since you use latex -LasseArticle: 99263
> Did some company already implemented G.709 OTU-2 on Virtex-4 using the > RocketIO? even if ... Does anyone really have those Virtex4 in that super-speedgrade -12X? To me it sounds like they won't be available anytime soon ... :-( bye, MichaelArticle: 99264
> But the problem of the asynch-FIFO 16 is that > I couldn't prevent simultaneous read and write. > When the process tries to read and write at the same time by chance, > the output is distorted. You are sure you are using an async fifo from the core generator? And you connected the right clocks? bye, MichaelArticle: 99265
Stephane wrote: > Ivan wrote: >> Hi, Hi, > Actually, the explanation of these bitgen options in ISE is that it > takes in consideration only the major addresses of block type 0,1,2 in > hex value... but block types is not described here, and the hex chain > generation is not obvious... > I think you are refering to the XAPP452 ? > > Yes. I did not remember that it was an application note ;) Regards, IvanArticle: 99266
Would it be this paper? http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/fccm/1997/8159/00/8159toc.xml&DOI=10.1109/FPGA.1997.624623 Good post, thanks. RobinArticle: 99267
Andreas Ehliar <ehliar@lysator.liu.se> wrote: > I would try XC3SProg before giving up on the parallel cable. My > feeling is that it might work since it uses system calls to > set the parallel port instead of bit banging directly to the > IO ports: > http://www.rogerstech.force9.co.uk/xc3sprog/index.html I have extended xc3sprog to also use the FT2232. The software is in no good shape, but shared on request ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 99268
Thanks to both of you. That's what we were thinking and it's what we're investigating ... indeed that development board seems to have a 'weak' power supply ...Article: 99269
@all: You guys are a bit over my head. I need to do some more reading on this. Andreas Ehliar wrote: > I would try XC3SProg before giving up on the parallel cable. My > feeling is that it might work since it uses system calls to > set the parallel port instead of bit banging directly to the > IO ports: > > http://www.rogerstech.force9.co.uk/xc3sprog/index.html > > > /Andreas Now if I understand that right, this is a replacement for impact, allowing to program Spartan 3 devices over the parallel port. Is that really Spartan3 only or can I program my Spartan2 with that as well? For using it with an USB port, I would probably need to use it with Uwe's extension for the FT2232?Article: 99270
Would anyone know where to get the JTAG programming specs (and programming times, page sizes, etc) for the XC18V01? I'd like to create an application for re-programming a 18V01 that takes as input the Intel Hex (MCS) and outputs JTAG bit banging. Xilinx recommends (app note 58 and 500) generating SVF or XSVF and using the XSVF player for the JTAG bit-bang. Unfortunately the memory requirements of this player are excessive. So far most of my knowledge has been from studding the SVF file for the 18V01 that is generated by Impact - however - this isn't a good way to generate solid foundation for this project - and Xilinx has thus far been unwilling to provide these specifications. TIA, Chris Section of SVF file that program's a page: RUNTEST 1 TCK; RUNTEST 1 TCK; // Loading device with a 'faddr' instruction. SIR 8 TDI (eb) ; SDR 16 TDI (0060) SMASK (ffff) ; RUNTEST 1 TCK; RUNTEST 1 TCK; // Loading device with a 'fpgm' instruction. ENDIR IRPAUSE; SIR 8 TDI (ea) ; RUNTEST 1 TCK; RUNTEST 14000 TCK; // Loading device with a 'fdata0' instruction. SIR 8 TDI (ed) ; SDR 2048 TDI (0100401004010000000000000000000000000004010040100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000000000000) SMASK (ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff) ; ENDIR IDLE; XC18V01 BSD documents the following JTAG opcodes: Attribute INSTRUCTION_OPCODE of XC1801 : entity is "BYPASS ( 11111111)," & "SAMPLE ( 00000001)," & "EXTEST ( 00000000)," & "IDCODE ( 11111110)," & "USERCODE ( 11111101)," & "HIGHZ ( 11111100)," & "CLAMP ( 11111010)," & "ISPEN ( 11101000)," & "ISPENC ( 11101001)," & "FPGM ( 11101010)," & "FADDR ( 11101011)," & "FVFY0 ( 11101111)," & "FVFY1 ( 11111000)," & "FVFY3 ( 11100010)," & "FVFY6 ( 11100110)," & "FERASE ( 11101100)," & "SERASE ( 00001010)," & "FDATA0 ( 11101101)," & "FDATA3 ( 11110011)," & "FBLANK0 ( 11100101)," & "FBLANK3 ( 11100001)," & "FBLANK6 ( 11100100)," & "NORMRST ( 11110000)," & "CONFIG ( 11101110)," &Article: 99271
Hi all, I heard that Verilog has integer type. Someone said integer can be signed or unsigned. How to declear signed integer? And what's the difference with integer and reg signed [31:0](2's complement) ? Any suggestions will be appreciated! Best regards, DavyArticle: 99272
I was considering purchasing an AMD64 quad-processor system, but have no idea whether any of the FPGA development tool software would take advantage of multi-processors (Synplicity for Lattice, Actel, Xilinx, etc). Any ideas or recommendations?Article: 99273
Does not Altera also work with technology of partial reconfiguration?Article: 99274
xilinx prom programming speca are not public and can not be obtained :( antti
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