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Messages from 99675

Article: 99675
Subject: Re: WARNING:Xst:1778 - Inout <AddrBus>
From: "Isaac Bosompem" <x86asm@gmail.com>
Date: 27 Mar 2006 20:42:52 -0800
Links: << >>  << T >>  << A >>
I think it is doing this because you are not using it as an input. Also
if you are working with FPGA's I think it would be a good idea to only
use unidirectional ports in sub modules. While using bidirectional
ports for top level devices (SDRAM, SRAM, Flash, etc.)

-Isaac


Article: 99676
Subject: Re: spartan FPGA with PLCC package
From: John_H <johnhandwork@mail.com>
Date: Tue, 28 Mar 2006 05:07:20 GMT
Links: << >>  << T >>  << A >>
kulkarku@math.net wrote:
> i want to design the prototype board for spartan series FPGA which is
> least costly,for master serial mode of configuration i want to use
> PROM.I am looking for some through hole component like PLCC84 pin &
> PLCC 20 pin package.can u suggest me some.

Least costly:
   Buy a development board for $99.

Alternative for "your own" stuff:
   Use a new FPGA - Xilinx Spartan3(E?), Altera Cyclone-II, or Lattice 
ECP(2?) - in a TQFP package (still solderable by hand).  It's not 
through-hole but it's doable.  Good through hole support is mostly a memory.


And don't force everything to be 5V.

Article: 99677
Subject: Hand-drawn schematic symbols of ISE coregen cores revert to rectangles when underlying core parameters are changed!
From: "PeterC" <peter@geckoaudio.com>
Date: 27 Mar 2006 22:01:31 -0800
Links: << >>  << T >>  << A >>

Hi All,

My design flow includes a top-level schematic into which I place
symbols which represent lower-level modules, including coregen cores
(ISE7.1).

I have modified the schematic symbols for things like adders,
multipliers etc, to look like symbols typically found in arithmetic
texts.

Now, when one of the coregen core's' parameters are changed (say a bus
width) and the core is re-generated, the symbol for that core in my
schematic reverts to the nasty rectangle.

How can I avoid this, ie. how do I avoid having to re-draw my symbols
every time I change core parameters or add a port (say a ACLR) ?

Hope someone can help - seems like this should be possible.

Cheers,
PeterC.


Article: 99678
Subject: Re: Microblaze using SPI flash as instruction memory
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 28 Mar 2006 18:01:41 +1200
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> Thomas Entner wrote:
> 
>> Hi Karel,
>>
>> I cannot comment on Microblaze, but we do this with our 
>> ERIC5-processor (also in S3E 250/500 design). For better performance, 
>> we use 1 BRAM as cache, and the SPI-flash-interface is optimized for 
>> sequential accesses. BTW: The ERIC5 needs much less resources than 
>> Microblaze, so maybe you could get away with a S3E 250 (if every 
>> dollar counts ;-).
> 
> 
> What MHz can you stream from the SPI at, in sequential mode.
> I see there are now ~70MHz SPI device.
> 
> I wonder when we'll see DDR SPI devices ?
> They could do that with another read opcode..

Some more devices have since appeared :

Winbond now have a 150Mhz SPI memory (W25X family), that
uses dual pins (MOSI becomes an output, CLK @ 75MHz )

Atmel have a new AT25FS040, that hits 50MHz, and does not need
a padder byte on read - so turnaround is a bit faster.

One could use 2-3-4 of these small devices, to increase the
memory bandwidth.

-jg


Article: 99679
Subject: Re: How to write compact DFF chain?
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 27 Mar 2006 22:24:03 -0800
Links: << >>  << T >>  << A >>
Xpost from OP,  FUp2 comp.lang.vhdl

Davy schrieb:

> Sometimes I have to write long DFF chain like below:

In VHDL you would write

if reset_active then
  DFF <= (others =>'0');
 elsif rising_edge(Clk)
  DFF <= DFF( xxx downto 0) & input;
end if

If you don't like to change to VHDL than you should avoid posting in
the VHDL-group.

bye Thomas


Article: 99680
Subject: Re: Variable problem
From: ywz.oct13@gmail.com
Date: 27 Mar 2006 22:35:30 -0800
Links: << >>  << T >>  << A >>
Hi Mike,

for i in 1 to msgNum-1 loop  -- msgNum is used as a range for variable
"i"

commenting the declaration does not seem to work. The error generated
suggests that variables should not be used in range as the synthesis
tool is unable to allocate resources as range is not fixed (is that the
case??). How should I approach the problem then?

Another question (not related to the above): I need a shared variable 2
dimensional array for some concurrent processes which will update this
array; however from what I read, shared variables should not be used
for synthesis. What and how should I replace the shared variable with?
signals??

Btw, do you happen to know of any links where i can read up about the
very basics of vhdl and synthesis?

Thanks again.
ywz


Article: 99681
Subject: Please recomend textbook with AES encryption.
From: "Frank" <frank@yahoo.com.cn>
Date: Tue, 28 Mar 2006 14:49:05 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I am looking for textbook with detailed information on AES encryption
and decryption. I have Bernard Sklar's Digital Communications, but it
contains DES only.

Thanks in advance.



Article: 99682
Subject: Re: C-based FPGA programming/mixed languages
From: The Other Guy <tog@null.void>
Date: Tue, 28 Mar 2006 18:53:43 +1200
Links: << >>  << T >>  << A >>
manu wrote:
> Hello,
> I'm not sure synthesis tools exist for SpecC, since it was originaly 
> dedicated to system specification....

Hi,

Thanks for your response. It certainly explains why I can't see any 
documentation on SpecC and synthesis.

I will investigate SystemC some more, although as it is based on C++ 
classes, it was a route I was hoping to avoid (I prefer C). FpgaC 
appears to be able to output VHDL as well, but I have been unable to get 
any output from it that looks like it does anything other than 
initialize values to 0.

C -> VHDL is probably the best option, it will help me learn VHDL as I go.

The Other Guy

Article: 99683
Subject: Re: Verilog, PSL or SystemVerilog of OVL?
From: "ngsayjoe@gmail.com" <ngsayjoe@gmail.com>
Date: 28 Mar 2006 00:37:38 -0800
Links: << >>  << T >>  << A >>
I'd recommend you to go for SystemVerilog, as it's the hardware
language of the future.

Joe,
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Davy wrote:
> Hi all,
>
> I am a Verilog user.
> I want to use assertion based verification in my project. And I found
> OVL(Open Verification library).
>
> Do you think which one of the OVL is better? Verilog, PSL or
> SystemVerilog?
>
> And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in
> SystemVerilog again?
> 
> Best regards,
> Davy


Article: 99684
Subject: OPB monitor error
From: dumak23@yahoo.com
Date: 28 Mar 2006 00:43:33 -0800
Links: << >>  << T >>  << A >>
Hi all,

I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm
currently getting an error 1.11.3, which says I didn't increment the
ABus correctly during seqAddr bus access. The particular case I'm
looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using
sequential address, byte-enable transfer, and xfer_size is "byte." The
slave I wrote into is a full-word device that supports byte-enable. So,
there shouldn't be any need for conversion cycles, and so my next ABus
is 0x00000E6C. But apparently the OPB monitor flags this as an error. I
think it expects the ABus to be incremented only by 1, since the
previous xfer_size is byte. I think this is correct _if_ I'm using the
basic dynamic sizing and _not_ the byte-enable architecture.

Digging into the OPB monitor code, it seems that the process that
checks for this particular scenario only checks for the xfer_sizes and
xfer_acks - there's no references to byte-enable signals. The OPB
monitor version I have is 2.0.1, and it seems to be the latest version
that you can get from Xilinx.

Any help / input is greatly appreciated.

Thanks,

dumak23


Article: 99685
Subject: Re: C-based FPGA programming/mixed languages
From: =?ISO-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@mailtonne.de>
Date: Tue, 28 Mar 2006 10:54:29 +0200
Links: << >>  << T >>  << A >>
> My preference is to develop in C for now as the functionality required 
> is easily implemented in C, while learning VHDL is going to take quite 
> some time.

Usually the language VHDL itself is not the problem ...
You will have to learn a new syntax and if you start with a small 
example with a clocked process you should be able to successfully modify 
that within a few days ...


another problem is the tool-chain ... you just don't click make and 
everything is fine - the workflow is different, there are timing 
constraints to take care of and lots of warnings (and only few of them 
are relevant ;-)


The biggest problem comes with "thinking in hardware" which turnes out 
to be quite a problem for C-people ... the sequential way of planing 
your programm usually does not fit very well and will waste a lot of 
ressources ...
To get a deep understanding about whats really happening inside and why 
some description is not very clever will take you well above .5 years



I've never tried any of those high-level languages but I doubt they will 
solve the 2nd and 3rd problem ... they may hide it though ;-)


bye,
Michael

Article: 99686
Subject: Re: deglitching a clock
From: bill.sloman@ieee.org
Date: 28 Mar 2006 01:07:52 -0800
Links: << >>  << T >>  << A >>

John Larkin wrote:
> On 27 Mar 2006 15:00:52 -0800, bill.sloman@ieee.org wrote:
>
> >
> >John Larkin wrote:
> >> We have a perfect-storm clock problem.

<snip>

> If we wanted to spin the board layout, we could just put in the
> risetime-limiting inductor, or add a meaty clock buffer, or better yet
> add a series resistor, with maybe an optional cap to ground, to slow
> down the sig on the clock line, and then add a Tiny Logic schmitt
> buffer at each chip. But as I noted, the challenge here is to find a
> software-only fix.

This is the manager talking, rather than the engineer. This is a
hardware problem, and it sounds as if you've already spent more time on
trying to find a software sticking-plaster than is cost-effective.

Have you tried another brand of 16MHz clock oscillator? Farnell have
heaps of alternative parts avaialble off the shelf  in a variety of
packages.

If the part you are using really does have a built-in source
termination resistor - which does seem to be the most likely
explanation of the flat spot on the clock waveform at Fpga1 - swapping
to a different manufacturer might cure the problem.

-- 
Bill Sloman, Nijmegen


Article: 99687
Subject: Re: OPB monitor error
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Tue, 28 Mar 2006 10:10:20 +0100
Links: << >>  << T >>  << A >>
Hi dumak23
this looks wrong to me
"ABus = 32'h00000E69, and BE = 4'b0111"

is this a typo? you have 3 byte lanes enabled, I'm not an OPB expert but 
  I think it should be 4'b1000

Aurash

dumak23@yahoo.com wrote:
> Hi all,
> 
> I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm
> currently getting an error 1.11.3, which says I didn't increment the
> ABus correctly during seqAddr bus access. The particular case I'm
> looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using
> sequential address, byte-enable transfer, and xfer_size is "byte." The
> slave I wrote into is a full-word device that supports byte-enable. So,
> there shouldn't be any need for conversion cycles, and so my next ABus
> is 0x00000E6C. But apparently the OPB monitor flags this as an error. I
> think it expects the ABus to be incremented only by 1, since the
> previous xfer_size is byte. I think this is correct _if_ I'm using the
> basic dynamic sizing and _not_ the byte-enable architecture.
> 
> Digging into the OPB monitor code, it seems that the process that
> checks for this particular scenario only checks for the xfer_sizes and
> xfer_acks - there's no references to byte-enable signals. The OPB
> monitor version I have is 2.0.1, and it seems to be the latest version
> that you can get from Xilinx.
> 
> Any help / input is greatly appreciated.
> 
> Thanks,
> 
> dumak23
> 

Article: 99688
Subject: Re: OPB monitor error
From: "Guru" <ales.gorkic@email.si>
Date: 28 Mar 2006 01:16:39 -0800
Links: << >>  << T >>  << A >>

dumak23@yahoo.com wrote:
> Hi all,
>
> I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm
> currently getting an error 1.11.3, which says I didn't increment the
> ABus correctly during seqAddr bus access. The particular case I'm
> looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using
> sequential address, byte-enable transfer, and xfer_size is "byte." The
> slave I wrote into is a full-word device that supports byte-enable. So,
> there shouldn't be any need for conversion cycles, and so my next ABus
> is 0x00000E6C. But apparently the OPB monitor flags this as an error. I
> think it expects the ABus to be incremented only by 1, since the
> previous xfer_size is byte. I think this is correct _if_ I'm using the
> basic dynamic sizing and _not_ the byte-enable architecture.
>
> Digging into the OPB monitor code, it seems that the process that
> checks for this particular scenario only checks for the xfer_sizes and
> xfer_acks - there's no references to byte-enable signals. The OPB
> monitor version I have is 2.0.1, and it seems to be the latest version
> that you can get from Xilinx.
>
> Any help / input is greatly appreciated.
>
> Thanks,
>
> dumak23


Hi dumak,

Sorry I cannot help you, but I have some questions since you are doing
the thing that I want to do by myself. I have about the same problems.
I am exploring OPB Master capabilities designed with EDK's Create -
Import peripheral wizard. I inserted Chipscope  IBA/OPB core to my
desing to monitor OPB bus. The problem are the signal names in
ChipScope Analyzer - there are 80 of them with NO names attached. How
to correctly assign signal names (or should I make a custom core with
ChipScope Core Generator)?

Cheers, Guru


Article: 99689
Subject: Bidirectional signals with Altera Signaltap
From: "Guido" <gvaglia@gmail.com>
Date: 28 Mar 2006 01:20:51 -0800
Links: << >>  << T >>  << A >>
Dear all,
I am trying to using SignalTap to debug a design in which I have some
bidirectional ports.
Using both Pre-synthesis and Post-fitting (while using incremental
routing) Signal-Tap signals I am not able to find the IO port in order
to include it in the acquisition.
I tried to find some answer in Altera website or in the manual but I
found nowhere any reference to bidirectional ports and signaltap.
Is it a limitation of the software?
Is there a way to overcome it? Apart from introducing two more Input
and Output port for watching the signal in both phases?

Thank you all

Guido


Article: 99690
Subject: Re: Verilog, PSL or SystemVerilog of OVL?
From: "anupam" <meanupam@gmail.com>
Date: 28 Mar 2006 01:34:05 -0800
Links: << >>  << T >>  << A >>
hi,
I recommend system verilog .its more powerful and therefore a little
hard to learn.
With system verilog you can write your own assertions better than the
predefined ones.
PSL is almost same as System Verilog Assertions

regards,
Amupam Jain


Article: 99691
Subject: Re: Nios II - VHDL Source Code, Licensing
From: "Jon Beniston" <jon@beniston.com>
Date: 28 Mar 2006 01:40:29 -0800
Links: << >>  << T >>  << A >>
Yes. I think it's about $50k.

Cheers,
Jon


Article: 99692
Subject: Re: OPB monitor error
From: Zara <yozara@terra.es>
Date: Tue, 28 Mar 2006 12:51:03 +0200
Links: << >>  << T >>  << A >>
On 28 Mar 2006 01:16:39 -0800, "Guru" <ales.gorkic@email.si> wrote:

>
<...>
>
>Sorry I cannot help you, but I have some questions since you are doing
>the thing that I want to do by myself. I have about the same problems.
>I am exploring OPB Master capabilities designed with EDK's Create -
>Import peripheral wizard. I inserted Chipscope  IBA/OPB core to my
>desing to monitor OPB bus. The problem are the signal names in
>ChipScope Analyzer - there are 80 of them with NO names attached. How
>to correctly assign signal names (or should I make a custom core with
>ChipScope Core Generator)?
>


Look at a directory with a name of the sort
"implementation\chipscope_opb_iba_0_wrapper", you will sess a .cdc
file, this is the file to load from Chipscope analyzer with the signal
name assignment.

Best luck,

Zara

Article: 99693
Subject: Re: Xilinx Coregen
From: BaTT <>
Date: Tue, 28 Mar 2006 03:05:45 -0800
Links: << >>  << T >>  << A >>
You need IP update.

Article: 99694
Subject: Re: Altera web site inaccessible
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Tue, 28 Mar 2006 11:16:12 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Tue, 28 Mar 2006 02:33:35 +0200) it happened Ben Twijnstra
<btwijnstra@gmail.com> wrote in
<422e2$442865e9$d52e23a9$30495@news.chello.nl>:

>Hmmmm... Chello first routes to Level3, then the traces converge in New York
>(your hop 7, my hop 13). It all seems to have depended on router
>configuration. I guess Savvis will have had a fewrather angry phone calls
>from Altera ;-)

Possible, I dunno what was the reason, mmm I sure hope politics will not
screw up the name system, and countries will not start filtering traffic
from specific zones (like China is filtering). 
But maybe it was just something technical.

>BTW: what are you paying for that direct ADSL line?

Mmm have to look it up, lemme see.. 29.95 Euro / month.
I had about 8 or nine ISPs over the years, ALL of these sucked, had downtime,
incompetent helpdesks......
So far I have detected 2 glitches in the last one and a half years or so...
Just one minute interrups in the middle of the night.
Zero errors in ifconfig always.
Very good and a lot cheaper then an ISP.
Speed is now 512 / 3072, they keep increasing it every now and then, fixed IP.
Name server runs here too.
So, if you want to do this, and want to have your own domain name, you will
have to register a domain (is cheap), and perhaps run some nameservers 24/7.

Now for an interesting experiment, now I have Quartus in Linux wine win98
emulator in one screen, and Webpack 8.1i scripted in an other, on grml-Linux
on the same box.
So would it be possible to synthesize with Altera to EDIF, then use the EDIF
in Webpack to program a Spartan?
Have to look into that......
Just to get around some Webpack bug... hum... icarus seems to run out of
memory when trying to make EDIF..... 600MB should be enough?
LOL
hehe
Maybe it will work...



Article: 99695
Subject: actmap looks like not responding
From: praviendre@hotmail.com
Date: 28 Mar 2006 05:56:15 -0800
Links: << >>  << T >>  << A >>
im a final year student, and im trying to synthesis my floating point
adder. This has so many small modules, everything was synthesised and
they are ok.

My problem is the when im trying to synthesis the top design which
combines all the small modules it looks like the actmap programme is
not responding.

It goes fine until the

Logic Optimization and Mapping for (fpAdderSub)

BDD based synthesis
        BDD synthesis skipped

Library based synthesis

i think it looks like it has stuck after the Library based synthesis.
Because it doesn't performs any further action. i have waited like 60
minutes. 

any ideas??? pls reply  !!! Thanks a lot.

Prav


Article: 99696
Subject: actmap looks like not responding
From: praviendre@hotmail.com
Date: 28 Mar 2006 05:56:50 -0800
Links: << >>  << T >>  << A >>
im a final year student, and im trying to synthesis my floating point
adder. This has so many small modules, everything was synthesised and
they are ok.

My problem is the when im trying to synthesis the top design which
combines all the small modules it looks like the actmap programme is
not responding.

It goes fine until the

Logic Optimization and Mapping for (fpAdderSub)

BDD based synthesis
        BDD synthesis skipped

Library based synthesis

i think it looks like it has stuck after the Library based synthesis.
Because it doesn't performs any further action. i have waited like 60
minutes. 

any ideas??? pls reply  !!! Thanks a lot.

Prav


Article: 99697
Subject: Re: Hand-drawn schematic symbols of ISE coregen cores revert to rectangles when underlying core parameters are changed!
From: "Gabor" <gabor@alacron.com>
Date: 28 Mar 2006 06:39:20 -0800
Links: << >>  << T >>  << A >>
I haven't tried this, but I know that the COREgen system creates new
schematic symbols even when the I/O ports don't change.  I would
recommend to look at the file list for your COREgen modules and
figure out which one is the schematic symbol (should be easy to
find if you edit it after generating the core, just look by date).
Make
a copy of this file before you re-generate and restore it afterwards.
I don't think you should have a problem as long as the port names
and sizes don't change...

PeterC wrote:
> Hi All,
>
> My design flow includes a top-level schematic into which I place
> symbols which represent lower-level modules, including coregen cores
> (ISE7.1).
>
> I have modified the schematic symbols for things like adders,
> multipliers etc, to look like symbols typically found in arithmetic
> texts.
>
> Now, when one of the coregen core's' parameters are changed (say a bus
> width) and the core is re-generated, the symbol for that core in my
> schematic reverts to the nasty rectangle.
>
> How can I avoid this, ie. how do I avoid having to re-draw my symbols
> every time I change core parameters or add a port (say a ACLR) ?
>
> Hope someone can help - seems like this should be possible.
> 
> Cheers,
> PeterC.


Article: 99698
Subject: Specifying top level generics with XST 7.1
From: moogyd@yahoo.co.uk
Date: 28 Mar 2006 08:01:56 -0800
Links: << >>  << T >>  << A >>
Hello,

We have a parameterizable (via top level generics) VHDL design that we
are trying to put into an FPGA using the Xilinix XST (Version 7.1)
tools.

We can't find any way within the tool of specifying values for the
generics as part of the build process.

Are we not looking hard enough, or does the feature not exist ?

Thanks in advance,

Steven


Article: 99699
Subject: Re: deglitching a clock
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Tue, 28 Mar 2006 08:17:23 -0800
Links: << >>  << T >>  << A >>
On 28 Mar 2006 01:07:52 -0800, bill.sloman@ieee.org wrote:

>
>John Larkin wrote:
>> On 27 Mar 2006 15:00:52 -0800, bill.sloman@ieee.org wrote:
>>
>> >
>> >John Larkin wrote:
>> >> We have a perfect-storm clock problem.
>
><snip>
>
>> If we wanted to spin the board layout, we could just put in the
>> risetime-limiting inductor, or add a meaty clock buffer, or better yet
>> add a series resistor, with maybe an optional cap to ground, to slow
>> down the sig on the clock line, and then add a Tiny Logic schmitt
>> buffer at each chip. But as I noted, the challenge here is to find a
>> software-only fix.
>
>This is the manager talking, rather than the engineer. This is a
>hardware problem, and it sounds as if you've already spent more time on
>trying to find a software sticking-plaster than is cost-effective.

Spare me your armchair theorizing; it's not a "hardware problem" or a
"software problem", it's just a problem. We have, in a few hours,
found and tested an excellent FPGA-internal fix that we can pop into a
rom and mail to our customers. We'll include a couple of other nice
firmware improvements, while we're at it. Your definitions of
"manager" and "engineer" do not constrain my latitude to think.

>
>Have you tried another brand of 16MHz clock oscillator? Farnell have
>heaps of alternative parts avaialble off the shelf  in a variety of
>packages.

What's a Farnell?


>If the part you are using really does have a built-in source
>termination resistor - which does seem to be the most likely
>explanation of the flat spot on the clock waveform at Fpga1 - swapping
>to a different manufacturer might cure the problem.

I already explained: it's too fast and too weak to drive our
low-impedance clock line. It's wildly improbably that a $1.50, 16 MHz
xo would deliberately include a series terminator... what value would
they pick? And I already explained, several times, we don't want to
recall all the units in the field.

We could have sent them a small ferrite disk, to be glued into the top
of the board over the clock trace (we'd of course furnish a tube of
glue, no extra charge) that would fix it too. But I think the ROM swap
is more professional and managerial.

John




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