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Messages from 98550

Article: 98550
Subject: Re: Question about multi write ports RAM in FPGA?
From: "fpga" <hy34@njit.edu>
Date: 12 Mar 2006 12:38:35 -0800
Links: << >>  << T >>  << A >>
Thank you peter and Issac all. Yes, I want serverl read ports and
severl write ports for the RAM. So I think the only way I can do is to
use time multiplexing, which will limit the highest frequency I can
get.


Article: 98551
Subject: Re: ModelSim 6.0 v 5.7 Can't read file
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 12 Mar 2006 12:51:48 -0800
Links: << >>  << T >>  << A >>
Brad Smallridge wrote:
> Yeah. That runs. Funny.
> Here's my code:
> LIBRARY ieee;
> USE ieee.std_logic_1164.ALL;
> USE ieee.numeric_std.ALL;
> 
> ENTITY tb IS
> END tb;
> ...

Modelsim compiles and elaborates your tb ok up to the uut.
tb probably needs some code trace / debug to find
the problem. Good luck.

       -- Mike Treseler

PS: I would just covert the bmp file to a vhdl constant
array using a script [bash|perl|python|etc].

______________________________
76 Sun Mar 12 /evtfs/home/tres/vhdl/play> vsim -c tb
Reading /flip/usr1/modeltech/tcl/vsim/pref.tcl

# //  ModelSim SE 6.1c Nov 17 2005 Linux 2.6.5-7.201-smp
# Loading /flip/usr1/modeltech/linux/../std.standard
# Loading /flip/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /flip/usr1/modeltech/linux/../ieee.numeric_std(body)
# Loading work.tb(behavior)
# ** Warning: (vsim-3473) Component instance "uut : top" is not bound.
#    Time: 0 ns  Iteration: 0  Region: /tb  File: tb.vhd
VSIM 1> run 1
# ** Failure: bmp file not 24 bit type
#    Time: 0 ns  Iteration: 0  Process: /tb/tb File: tb.vhd
# Break at tb.vhd line 311
# Stopped at tb.vhd line 311


Article: 98552
Subject: Re: Question about multi write ports RAM in FPGA?
From: "JJ" <johnjakson@gmail.com>
Date: 12 Mar 2006 13:18:16 -0800
Links: << >>  << T >>  << A >>
If multi write means just 2 you are all set, if it means >2, besides
time based sharing you might also look at a recent (last week) thread
on incresing write ports by banking multiple BRAMs and using voting
logic. The difference between 1,2, 3+ is enormous if done in 1 clock. I
usually take several to mean >2.

See also Mar 6 "How do I make dual-port RAM from single port RAM?"

There were 2 interesting suggestions offered to allow 1 write port ASIC
rams to be used as an effective 2 port write ram but used 4 rams to do
this. The voting logic though still had to allow multi writes but is
only 1 bit wide. Perhaps these schemes can be used to allow >2 writes
per clock with even more voting logic. It will depend alot on your
reasons and conditions for wanting >2 writes. Typically high write
ports per clock are used in shallow datapath register files while low
write counts ports used in buffers etc.

What is your write port count and what is actual ram size and
application ?

John


Article: 98553
Subject: Re: Shift Register synthesis??
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 12 Mar 2006 13:23:00 -0800
Links: << >>  << T >>  << A >>
Alderaan wrote:

> How is it possible that using more slices and flip flops intead of the 
> LUT configured as SR it gets better performances? Could it be a 
> synthesizer error?

Without any speed or area constraints,
I expect that synthesis fit your first
version into an SRL with slower flops.
The second version would not fit an SRL
so you got real flops, which are faster
more portable, and easier to simulate.
Unless you are real short on flops, I would
leave it that way.

          -- Mike Treseler

Article: 98554
Subject: Re: Combinatorial Division?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 13 Mar 2006 10:35:07 +1300
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> The mercury delay lines were earlier, and were used only in
> "mainframes" of that day. Who wants to have a pot full of mercury
> sloshing around in a cash register? But this was before environmental
> concerns, when leaded gasoline was the best thing ever...
> 
> Did anybody mention the Williams tube? A CRT where you wrote to and
> read from the tube face.
>  It got killed by the early core memories, which in turn lived much
> longer than anybody had expected. Non-volatile storage with destructive
> read-out, just the opposite of SRAM nowadays.

  You could say core memory still lives on : in FRAM devices = identical 
property of magnetic domain storage with destructive read - only they
are now manufactured on a wafer, with additional process steps to insert 
the magnetic domain material, instead of physically wired.
  [ Bubble memory seems to have hit an evolutionary dead end..]

  I also see Intel reckons Ovionic (phase change) memory might yet fly...

-jg




Article: 98555
Subject: Re: Question about multi write ports RAM in FPGA?
From: "fpga" <hy34@njit.edu>
Date: 12 Mar 2006 14:05:11 -0800
Links: << >>  << T >>  << A >>
Thanks very much, John. My ram size is 256x32 and I want it has 4 read
ports and 3 write ports. The ram is gonna to be used as the local
vector register file in my vector coprocessor. My vector coprocessor
has different function cores, each has its own local vector register
(LVR). So these LVR need to provide ports to the function unit(2 read
ports, 1 write ports) and ports for transfer LVR data between this
cores (2 read ports, 2 write ports). I choose 2 read ports and 2 write
ports for data transfering because I believe it can bring much better
performance than 1 read port/1 write port design.

Also, multiple ports RAM (I don't decide the size and ports number yet)
will be used as the register file in superscalar machine.


Article: 98556
Subject: using EDK with the gcc -g option...
From: me_2003@walla.co.il
Date: 12 Mar 2006 14:05:24 -0800
Links: << >>  << T >>  << A >>
Hi all,
I have a little question regarding gcc, does the -g option for the
mb-gcc/powerpc-gcc compiler makes the executable code (xxxx.elf) bigger
? does it effect the memory size of my program and if so should I strip
it for my final version in order to save some BRAM space (after
finshing the debug stage) ? 
Thanks in advance, Mordehay.


Article: 98557
Subject: How to specify a package in Xilinx 8.1i
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 12 Mar 2006 14:07:21 -0800
Links: << >>  << T >>  << A >>
Hi,
I need your help.

I have 4 vhdl source files:
A-Package.vhd;
A1.vhd;
A2.vhd;
A3.vhd;

A-Package.vhd is a package defining all common functions and constants
used in all other modules.

If the 4 files are in the above order, Modelsim runs them without any
errors.

But with Xilinx 8.1i, errors happen.

The following is in more details.

In A1.vhd, it is a top module and there are generic definitions:
generic(
  DATABITS  : integer := DATA_BITS;
  MODEBITS : integer := MODE_BITS;
);

A2.vhd and A3.vhd are components called by A1.vhd and have the same
generic definitions:
generic(
  DATABITS  : integer := DATA_BITS;
  MODEBITS : integer := MODE_BITS;
);

I specify DATA_BITS/MODE_BITS in a global package A-Package.vhd.
constant	DATA_BITS  : integer := 6;
constant	MODE_BITS : integer := 3;

In instantiations in A1, A2 and A3:
generic map(
 DATABITS  => DATA_BITS,
 MODEBITS => MODE_BITS
)
port map(
...);

When running with ModelSim, there is no error, A-Package is first
compiled and DATA_BITS
and MODE_BITS are specified.

When running with Xilinx 8.1i, there are following warning and errors:
WARNING:Xst:616 - Invalid property "DATABITS 6": Did not attach to C0.
WARNING:Xst:616 - Invalid property "MODEBITS 3": Did not attach to C0.
WARNING:Xst:616 - Invalid property "DATABITS 6": Did not attach to C11.
WARNING:Xst:616 - Invalid property "MODEBITS 3": Did not attach to C11.
...
ERROR:NgdBuild:604 - logical block 'C0' with type 'ControlBlock_In_0C'
could not
   be resolved. A pin name misspelling can cause this, a missing edif
or ngc
   file, or the misspelling of a type name. Symbol 'ControlBlock_In_0C'
is not
   supported in target 'acr2'.
ERROR:NgdBuild:604 - logical block 'C11' with type 'ControlBlock_In_0C'
could
   not be resolved. A pin name misspelling can cause this, a missing
edif or ngc
   file, or the misspelling of a type name. Symbol 'ControlBlock_In_0C'
is not
   supported in target 'acr2'.

The problem is the ERROR MESSAGE DOESN'T CONTAIN THE MISSING OR
MISSPELLING PIN NAMES so that I cannot identify what pin is wrong.

I checked my instantiation code, and all pin names are matched. And
ModelSim
runs without errors. 

Thank you. 

Weng


Article: 98558
Subject: Re: EDK - PLB/OPB Bus questions.
From: me_2003@walla.co.il
Date: 12 Mar 2006 14:11:50 -0800
Links: << >>  << T >>  << A >>
>From the powerpc point of view Can I control these PLB features
(address decoupling / pipeling) i.e. are there any specific powerpc
command to tell the plb bus to operate this way or the other, or is it
entirly up to the bus configuration and cannot be controlled in
real-time ?
Thanks, Mordehay.


Article: 98559
Subject: Re: Question about multi write ports RAM in FPGA?
From: John_H <johnhandwork@mail.com>
Date: Sun, 12 Mar 2006 23:45:30 GMT
Links: << >>  << T >>  << A >>
fpga wrote:

> Hello,
> Is that possible to make a multi write ports RAM in FPGA by using
> distributed RAM or block RAM? It seems impossible to me. But using D
> flip flop to implement the multi ports RAM will costs too much resouce.
> Is there any suggestion to implement the multi write ports RAM in FPGA?
> Thanks a lot.

BlockRAMs are the easiest for a dual-port write.

For a non-multiplexed multiport write using distributed RAM, a little 
extra logic and a bunch more distributed memories can give you what you 
need.

Each port in an n-port distributed RAM canfiguration has one write and 
n-1 read from each of the other memories.  A write is done with the 
desired write data and an XOR of all the other reads.  A read is done 
with a read of all the memories.  As long as there are never writes to 
the same port, this sytem works gret; I've used it for multi-channel 
flags on both sides of a synchronous interface.

As long as you have the asynchronous distributed memories and enough 
setup for the write address, read, and XOR before the data is written, 
it all flows.

Article: 98560
Subject: Re: Question about multi write ports RAM in FPGA?
From: "fpga" <hy34@njit.edu>
Date: 12 Mar 2006 16:55:20 -0800
Links: << >>  << T >>  << A >>
Thank you very much.

Sorry I didn't clarify my requirement. I know it is easy for a
dual-port wirte and 1 wirte/multiple read RAM. But I need a RAM with >2
write ports and >2 read ports. Time-multiplexing is one choice, but it
may limited the system frequency.  Using voting logic as specified by
JJ maybe another choice.


Article: 98561
Subject: Re: using EDK with the gcc -g option...
From: "MM" <mbmsv@yahoo.com>
Date: Sun, 12 Mar 2006 19:58:19 -0500
Links: << >>  << T >>  << A >>
Of course enabling debugging information makes the file bigger, which in its
turn obviously requies more memory. The gcc has several levels of
optimization, which you can try enabling when you are done with your
debugging.

/Mikhail


<me_2003@walla.co.il> wrote in message
news:1142201124.740379.290280@j33g2000cwa.googlegroups.com...
> Hi all,
> I have a little question regarding gcc, does the -g option for the
> mb-gcc/powerpc-gcc compiler makes the executable code (xxxx.elf) bigger
> ? does it effect the memory size of my program and if so should I strip
> it for my final version in order to save some BRAM space (after
> finshing the debug stage) ?
> Thanks in advance, Mordehay.
>



Article: 98562
Subject: Re: How to specify a package in Xilinx 8.1i
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 12 Mar 2006 18:43:39 -0800
Links: << >>  << T >>  << A >>
Sorry. The problem is resolved.

The reason is that the project file doesn't contain the lower module
files while in its project file, lower level module names are shown.

Weng


Article: 98563
Subject: Re: FPGA imple. of aes
From: "manjunath.rg@gmail.com" <manjunath.rg@gmail.com>
Date: 12 Mar 2006 19:24:49 -0800
Links: << >>  << T >>  << A >>
Hello mordehay..
we are just graduate students doing this as a project..
i respect your intellectual property but we r not showing the code to
anyone nor  are we using it for other purposes like paper presentation
or contests..etc..
So you can be sure that it wont pass on to anyone else except me or
rather my group...hope you will provide us your implementation..
thanking you


Article: 98564
Subject: Re: Simulation of Xilinx Rocket IO
From: kedarpapte@gmail.com
Date: 12 Mar 2006 20:25:27 -0800
Links: << >>  << T >>  << A >>
Thanks to all,

I was able to get Rocket IO smart model simulation running in Modelsim
SE.

Thank you very much to you guys Mikhail and SEAN

Thanks
cu - Kedar


Article: 98565
Subject: Xilinx DDR SDRAM Controller
From: Remis Norvilis <norvilis@charter.net.removethis>
Date: Sun, 12 Mar 2006 22:32:32 -0600
Links: << >>  << T >>  << A >>
I am having a difficulty grasping project structure, generated by Xilinx
MIG007 software.
I?ve generated 16-bit data DDR1 SDRAM interface to Spartan3 xc3s500-4-efg208
device.
MIG user manual describes user signal interface and timing for ddr1_top
which is the main DDR SDRAM controller. But it?s hierarchically below
ddr1_test and mem_interface_top modules. These probably enhance user
interface or could be used for controller testing, I just can?t find any
documentation regarding their use. 
MIG007 also generated startup_spartan3 module, but here again no information
on how to use it.
I?d like to have a simple SRAM like user interface. If someone?s done this,
I would appreciate some pointers.

Article: 98566
Subject: Re: Question about multi write ports RAM in FPGA?
From: John_H <johnhandwork@mail.com>
Date: Mon, 13 Mar 2006 05:06:19 GMT
Links: << >>  << T >>  << A >>
fpga wrote:
> Thank you very much.
> 
> Sorry I didn't clarify my requirement. I know it is easy for a
> dual-port wirte and 1 wirte/multiple read RAM. But I need a RAM with >2
> write ports and >2 read ports. Time-multiplexing is one choice, but it
> may limited the system frequency.  Using voting logic as specified by
> JJ maybe another choice.

The method I suggested specifically works for your case.  You need a 
total of 9 dual-port distributed CLB SelectRAM memory sets for 3 Rd/Wr 
adresses and 1 Rd-only address.  If your 4 read addresses are unrelated 
to any of the 3 write addresses, you would end up with 6 dual-ports to 
support the 3 write ports and 3 dual-ports for each of your independent 
reads for a total of 18 dual-port CLB SelectRAM memory arrays.

For this to work, 1) you cannot write to the same location in more than 
one memory at the same time, 2) you have to XOR the input data with the 
data at the same location in memories related to the other write ports, 
and 3) your read values are the XORs of the data from each of the 
memories associated with the three write ports.

For a 4-bit with memory, assume the memories associated with the three 
write ports at entry 12 are

   MemA[12]==4'ha
   MemB[12]==4'h6
   MemC[12]==4'h0

Then a write to index 12 of Din==4'h7 at port B of your three-port write 
system would be

   MemB[12]<=(MemA[12]^MemC[12])^Din;
or
   MemB[12]<=(4'ha^4'h0)^4'h7;
which is
   MemB[12]<=4'hd;

So your following reads would be

   MemSys[12]==MemA[12]^MemB[12]^MemC[12];
or
   MemSys[12]==4'ha^4'hd^4'h0;
which is
   MemSys[12]==4'h7;

You wrote a value of 4'h7 into port B of your memory system and the 
later read of this location will be 4'h7.

If you want to have multiple writes to the same address location at the 
same time with the precedence set to a specific order, you can add 
additional logic to get the results you desire.

Article: 98567
Subject: What does a "1RW/1R Partial Write RAM Verilog HDL Model." usually. mean?
From: "Baddest Sinus" <Badsinus@yahoo.co>
Date: Mon, 13 Mar 2006 14:07:51 +0800
Links: << >>  << T >>  << A >>
Other peoples got the simulation model of this type of RAM from vendor, but
not the PDF or manual. What does the "1R partial Write" mean here? Is there
anything "common knowledge" which I haven't known yet?




Article: 98568
Subject: Re: fpga to 5v ttl logic
From: Kolja Sulimma <news@sulimma.de>
Date: Mon, 13 Mar 2006 08:28:12 +0100
Links: << >>  << T >>  << A >>
metal schrieb:
>>Why ? - noise immunity, ease of interface : have you ever tried to
>>find a power MOSFET that can be driven from 3.3V ?

But the additional circuitry required to drive the MOSFET from an FPGA
is so small and cheap compared to the power MOSFET that I do not see the
economic advantage of selecting the FPGA based on that criterion.
A driver in sc70-package will be hardly noticed in the layout next to a
power MOSFET and the additional cost of 3ct doesn't matter at all.

Inputs can be made 5V tolerant by a single resistors. These are
available at virtually no cost in 0.5mm pitch 8x arrays.

Schmitt-Triggers are only a little more cumbersome: You need a second
FPGA-pin and a single resistor. Or no additional pin and a driver in
sc70-package.

If you dot need more than a few dozens of these pins the cost will not
even add up to the price difference between a 3.3V and 5V part. And you
are much more flexibale because you can also support all the other
voltages that show up in the control industry: 5.2V (PECL), 6V, 6.2V,
12V, 15V, 24V....

Kolja Sulimma

Article: 98569
Subject: Re: Combinatorial Division?
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 13 Mar 2006 01:57:47 -0600
Links: << >>  << T >>  << A >>

>Did anybody mention the Williams tube? A CRT where you wrote to and
>read from the tube face.

Back in my youth, I worked with people who worked with them.  You
could read the bits off the face of the tube.

Best tale that I remember...

The face of the tubes was round.  Memory was 256 square or maybe
512.  The software guys were making a lot of noise about needing
more memory.  (Picture below says 2K bits.  Looks like 32x64.)

So the hardware guys added annother address extra bit.  Well sort of.
Only some of the new locations worked.  Those were the ones that
fit into the space between the old square and the enclosing circle.


Google is good:
  http://www.computer50.org/mark1/ip-mm1.crt2048.html
  http://www.computer50.org/kgill/williams/williams.html
"hence the official 1.2 millisecond instruction time"

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 98570
Subject: Re: using EDK with the gcc -g option...
From: me_2003@walla.co.il
Date: 13 Mar 2006 00:01:37 -0800
Links: << >>  << T >>  << A >>
Thanks alot....


Article: 98571
Subject: Re: LEON processor core
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 13 Mar 2006 02:24:08 -0600
Links: << >>  << T >>  << A >>
>well you need some initialized memory unless you are loading the sdram over 
>jtag debugger

Can you put the initial bits into the cache?
(and setup the extra bits for the cache to say they are valid.)

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 98572
Subject: Re: using EDK with the gcc -g option...
From: "Marco" <marco@marylon.com>
Date: 13 Mar 2006 00:26:34 -0800
Links: << >>  << T >>  << A >>
Hi, I usually compile without the -g option when I have made all the
debug I need.
So bigger version to test it, if it works, compile again and go with
the smaller.
Marco


Article: 98573
Subject: Re: LEON processor core
From: Ivan <gmivan@terra.es>
Date: Mon, 13 Mar 2006 09:01:42 GMT
Links: << >>  << T >>  << A >>
Hi,

you forgot to mention the MP (multiprocessor) support in LEON3 (up to 4 
microprocessors). Of course, you need to use the eCos version available 
for this MP system. I tested it 6 months ago and it works great. I think 
that now the support will be better than 6 months ago ;)

Regards,

Ivan


Martin Schoeberl wrote:
> I'm wondering why there are so few messages about LEON [1]
> in this group. LEON looks like a very solid design (used
> by the ESA) and it is available in a GPL version.
> Could be a vendor independent replacement of NIOS/MicroBlaze
> with a path to an ASIC.
> The configuration is done via a simple Tcl/Tk script and
> the Makefile contains several targets. Works out-of-the-box
> for available tragets. Adaption to a new FPGA board [2] took
> me a few (some) hours - not so bad.
> 
> What's your experience?
> 
> Martin
> 
> 
> [1] http://www.gaisler.com/cms4_5_3/index.php?option=com_content&task=view&id=13&Itemid=53
> 
> [2] http://www.jopdesign.com/nios.jsp 
> 
> 

Article: 98574
Subject: Re: fpga to 5v ttl logic
From: =?ISO-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@mailtonne.de>
Date: Mon, 13 Mar 2006 11:03:38 +0100
Links: << >>  << T >>  << A >>
> imho, fpga makers have dropped the ball, by totally ignoring the
> enormous markets of various mixed-signal products; where 5v is VERY
> common...along with generally noisy environments.

you are right ... not every application needs a high end FPGA!
we even use some of the old Spartan XCS40 - you can still buy them but 
ISE support was dropped long time ago :-(


bye,
Michael



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