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I forgot to add that these links are also in the pinout section (Module 4) of both the Spartan-3 and Spartan-3E data sheets.Article: 98751
metal wrote: <snip> > ps; jim is right, I had specifically mentioned a 64-128 cell part; > not a 3,000 register fpga. In which case, using cells for timers eats > up a $10 chip REAL fast....while the silicon cost for a few 16b hard > counters on a chip like that would be near-zero... In the current CPLD area, there are two lower cost solutios to this. Xilinx's larger CoolRunner2 (but NOT the 32/64MC ones IIRC) have a tapped dedicated divider, so you can get a simple CLK/n without loosing macrocells. Atmel's macrocells allow you to logic double, so you can bury simple counter registers, and still use the OR portion or the IO pins. Not quite free, but does allow you to use a smaller CPLD. -jgArticle: 98752
Kolja Sulimma wrote: > > Schmitt-Triggers are only a little more cumbersome: You need a second > FPGA-pin and a single resistor. Or no additional pin and a driver in > sc70-package. Have ever you measured the Icc/Vin on this kludge, or done noise immunity tests ? -jgArticle: 98753
Scott M. Kroll wrote:
> Believe it or not, just taking jumper M0 off let me program the .bit
> file and it worked. But the USB cable is always hot, even when not
> programming (it's plugged into my laptop right now, without the
> Spartan-3 Board, and it's very warm/near hot.
I set up the Digilent USB JTAG cable (Export 1.3) and tried
a few bitfile downloads of my S3 memory test code; the results
match yours, but I can also get the bitfile download to work
with the mode jumpers all on just by doing an extra JTAG
operation as I mentioned earlier.
test notes:
- my cable also stays warm
- after changing mode jumpers, .bit file downloads & runs OK
- with JP1 completely off, M0/M1/M2 jumpers all on, after
the .bit file is downloaded (PROM in bypass), the FPGA
fails to operate ( DONE LED off, user LEDs weakly lit
during/after download ).
However, another JTAG operation will wake up the design,
(DONE LED on) and it functions correctly after a manual reset.
"Another JTAG operation" = either an initialize chain, or just
do a device ID on the FPGA or PROM
- changing the startup clock (user/JTAG) and DCM reset options in
bitgen had no effect on the problem with the mode jumpers all on.
Brian
Article: 98754There is no question that such FPGAs or CPLDs can be designed and manufactured. And you can be assured that there are smart people at Xilinx and Altera (and elsewhere) who have analyzed this scenario. The challenging question is: How large is the potential market, and is this a meaningful area to invest our design, manufacturing, marketing and sales resources in ? And there is the "opportunity cost: "What other area do we have to neglect, in order to jump onto this allegedly juicy opportunity?" People, talent and money are not unlimited, neither is the focus of management and of the sales force. If the market is -just to pick a number- $ 50 M per year, that does not look tempting for the two big guys who each have between 1 and 2 billion dollar revenue per year. 2 to 5 percent of potential but not guaranteed extra revenue will not create great excitement. It might look more tempting to a smaller (or shrinking) manufacturer. I have personally suggested several interesting product ideas (along the lines of this thread) and several times had to admit defeat... Peter Alfke, from homeArticle: 98755
Hi Steve-
Thanks for reading and responding!
Re: binary files... Binary files have their advantages. However, the
rest of the software industry has recognized their distinct
disadvantages in many cases and have moved in droves to XML. It's
really quite beautiful in its simplicity. May I suggest that the ISE
tools store XML for SCM purposes, but (if they want to), create a binary
during operation for cross-app integration.
The ISE file should really only contain those parameters necessary to
describe a project and its components. It should not contain temp
results and should not even contain results of a project build (like
statistics). Place those in another file (pref. text/HTML) and let the
user decide if she wants to add them to SCM or not. They definitely
don't need to be added if a minor update has been made.
Please consider the separate build directory. I've suggested it through
different channels over the past few years. Deaf ears, I suppose.
Visual Studio does this (as do many other tools) and also stores project
info in XML. Temp files are binary (like precompiled headers and
Intellisense info)
Jake
Steve Lass wrote:
> First, let me try to address the reason why the ISE file is binary. A
> binary file
> allows us to manage concurrent reads/writes which is critical in making all
> the GUI applications work together. Binary files are faster and more
> efficient.
> Right now, there is a bug that is making the ISE file much larger than
> it needs
> to be. Also, a binary file can be more robust and requires less error
> checking.
>
> Access to the data in the ISE file is often important, so providing the
> capability
> to import and export is key. Check answer record 21067 for info on how to
> do this. Other than the GUI, the standard way to add info into the ISE
> file is
> Tcl, however, 8.2i will be required for this capability.
>
> Regarding keeping intermediate files in a separate directory, that is a
> great
> idea. We are planning on allowing you to specify the directory
> structure in
> the future.
>
> Regarding creating a batch file from the GUI, you can just cut and paste
> the
> commands from the command_log file.
>
> We do not hate version control and have plans to allow for integration with
> your source control systems.
>
> We are listening and taking your input seriously.
>
> Regards,
>
> Steve
>
> Jake Janovetz wrote:
>> Is there some internal Xilinx conspiracy against source code
>> management like SVN (subversion) and CVS? Or is it that the Xilinx
>> guys don't use version control to understand the goals?
>>
>> ISE 6.x used ".npl" files to contain the project information. These
>> were text-based making them at least somewhat SCM-friendly, but they
>> changed each and every time you saved the project even if nothing
>> changed. Some date code changed. Thus requiring an update...
>>
>> ISE 7.x came along and, even when the rest of the world was switching
>> to XML because of all the problems with binary config files, Xilinx
>> decided to move to a binary format ".ise" from it's .npl files. Now,
>> each SCM checkin required the whole binary file to be checked in each
>> time rather than just diffs (like the ISE 6.x days).
>>
>> ISE 8.x came along and the conspiracy became clearer. Xilinx held on
>> to its binary format but has apparently added a LOT more to the file.
>> Now, it's almost 1 MB!!! This means that my SCM repository grows by 1
>> MB EACH TIME I do a checkin if I include the ISE file. That's
>> ridiculous!
>>
>>
>> PLEASE Xilinx, be learn about CVS, SVN, and others, and how to design
>> file formats for SCM. Also, place all temporary files in a temp
>> directory and stop spamming my project directory. Oh, and one more
>> thing -- it would be nice to know which files from a CORE are
>> necessary to the project. Each CORE generates almost a dozen files
>> and I'd rather not add all of them to SCM.
>>
>> Jake
>
Article: 98756I want to know if the X2c family (coolrunner II) have a non-volatile program memory inside its package: I would like a non-volatile memory (eeprom...) that contains the "programs" also when it's extinguished (and with a number of macrocells comparable with a small/medium fpga). However I would know the name of a low-power, non-volatile program memory family (CPLD). Another question: can I use the XC9500 programmer (seen here: http://www.xilinx.com/support/programr/files/0380507.pdf) to program the X2c family (or where I can find some programers for the CPLD package)? Thanks DuccioArticle: 98757
Hi, You can get a look at Zilog Z-87200 which is a new version of the original Stanford STEL-2000... At Harris or Intersil : PRISM 2.5 chipset At COMBLOCK : COM-1018 And so I'm very interested if you buy a DSSS chip to cross correlate your results : sensitivity, SNR, BER... with our chip companie (we don't sell it), we have developped with a Stratix FPGA a DSSS transceiver DQPSK/DBPSK 4Mbps/2Mbps.Article: 98758
The schematic that you link points to is the Parallel Cable III and is used as a basis of many 3rd party programming cables like ourselves. It will usually program Coolrunner2 parts as well as XC9500 parts. I am not quite sure what your CPLD question refers to but both Lattice and Altera also have CPLD offerings. Even the biggest CPLDs are generally smaller than smallest FPGAs in effective logic size. John Adair Enterpoint Ltd. - Home of Hollybush1. The PC104+ Spartan-3 Development Board. http://www.enterpoint.co.uk "Duccio" <picinotti.duccio@tin.it> wrote in message news:1142497117.216446.269970@p10g2000cwp.googlegroups.com... >I want to know if the X2c family (coolrunner II) have a non-volatile > program memory inside its package: I would like a non-volatile memory > (eeprom...) that contains the "programs" also > when it's extinguished (and with a number of macrocells comparable with > a small/medium fpga). > However I would know the name of a low-power, non-volatile program > memory family (CPLD). > Another question: can I use the XC9500 programmer (seen > here: http://www.xilinx.com/support/programr/files/0380507.pdf) to > program the X2c family (or where I can find some programers for the > CPLD package)? > > Thanks > Duccio >Article: 98759
Duccio wrote: > I want to know if the X2c family (coolrunner II) have a non-volatile > program memory inside its package: I would like a non-volatile memory > (eeprom...) that contains the "programs" also > when it's extinguished (and with a number of macrocells comparable with > a small/medium fpga). > However I would know the name of a low-power, non-volatile program > memory family (CPLD). There are a number of players in the On-Chip memory PLD devices In the CPLD arena Xilinx X2Cxx you mention Lattice ispMACH4000z family Atmel ATF15xASL/BE family, In the FPGA fabric, but promoted as CPLD or Crossover devices These make more sense as the macrocell count climbs. These are not quite as low power as the 'Z' style CPLDs above, but are less than the hungry FPGAs. lattice ispMACH_XO Altera MAX II and NV FPGAs are also from Actel - various families Lattice ..but you will have already looked at the vendors web sites ? > Another question: can I use the XC9500 programmer (seen > here: http://www.xilinx.com/support/programr/files/0380507.pdf) to > program the X2c family (or where I can find some programers for the > CPLD package)? Check on the ISP software, for the cables supported. -jgArticle: 98760
Hi, I'm looking for a way to purchase V-4 (more specifically V4FX20 and V4FX40) at very low quantities (4-5 devices). It is for research and educational reasons, still the XUP(Xilinx University Program) does not offer devices. Does anyone know where I could buy from in such quantities? Thank you, GeorgeArticle: 98761
I am considering trying to interleave two 250MS/s ADCs. Would this be a good idea? possible? or too much trouble? Cheers JonArticle: 98762
Hard to get hold of these FX parts in any quantities at present. You should talk to your local distributor as a starting point for what is available in what timescale. Do check as this is a rapidly changing situation so advice that I have received may have changed since I last asked. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "George" <gpouikli@ee.duth.gr> wrote in message news:ee99044.-1@webx.sUN8CHnE... > Hi, I'm looking for a way to purchase V-4 (more specifically V4FX20 and > V4FX40) at very low quantities (4-5 devices). It is for research and > educational reasons, still the XUP(Xilinx University Program) does not > offer devices. Does anyone know where I could buy from in such quantities? > > Thank you, GeorgeArticle: 98763
Hi all, I've installed ISE 8.1 for linux (32 bit) on a Debian machine with no pain at all, it works fine. Now I'm trying to install the same release on a dual core AMD64 machine, with debian 64 bit, and all works fine until I need to insert the serial code of the product, wich is ever refused. Note that I'm using the _same_ serial I used for the 32bit machine, and our Xilinx man said that's right. I would like toknow if anyone experienced the same problem, and if with rhle 64 bit it works correctly with the same key, or if I need a special key for 64bit release... Thank you. -- MarcoArticle: 98764
> > Testing IS expensive, but so also is running a custom test - thus the >fairly high NRE prices on EasyPath - it also serves as a 'go away' flag >to those with insufficent volumes :) > My guess is that Xilinx does not prepare custome tests. Instead they select a handful from their pool of test vectors used to test the whole device. So the issue is how to decide which test vectors to use against a customer design: pretty simple really..... One issue which I feel has been overlooked in the cost analysis is that yields are higher for easypath than they would be for the equivalent FPGA part..... So I'd say that the cost savings come from both testing and yield improvements.... No?Article: 98765
I mean you want to reach 500MS/s sampling? It could be possible, you must be careful in designing PCB, Jerzy GburArticle: 98766
Reading the LSI Strucutred ASIC fiasco thread has made me think. People are saying the FPGA revenues are going to grow, so.... Which markets are FPGA heading into? I mean, at the moment there's Comms, Medical, Military, Consumer. Where are they going next? Automotive I guess is coming, as is aerospace. You could put the two together, as control electronics. How about seeing them in a PC? What are your views on the matter?Article: 98767
In general, you will find that this is a lot of trouble. That said, it is done. See the AD12401 at www.analog.com for an example of a module that interleaves two ADC. If you want to interleave multiple ADCs there are three main parameters that must be matched or corrected for on the ADCs. To the extent that they are not matched, the quality will degrade. 1. DC offset. Easy to track and remove if it is not matched. 2. Gain. Needs to be matched or equalized across your frequency range of interest. 3. Sampling phase offset. This is the one that will cause you big problems. If the ADCs have any phase error in when they sample, it will cause spurs in the data. The hight of the spurs depends on the sampling phase error. The data sheet for the AD9481 gives an error budget of < 2 ps for interleaving two 8 bit 250 MS/s ADCs with a 100MHz analog input. That error budget will go down if your analog input is higher frequency, or if you want more bits of resolution. I think that there are some graphs of sampling phase error budgets vs other parameters some where on the Analog web site, but I do not remember where. Regards, John McCaskillArticle: 98768
>I mean you want to reach 500MS/s sampling? > >It could be possible, you must be careful in designing PCB, > >Jerzy Gbur > > Yes I would like to reach that sampling, but I guess there are a lot of other things to take into consideration apart from the pcb like the ADC errors etc. Cheers JonArticle: 98769
John C <brakepiston@yahoo.co.uk> wrote: >Reading the LSI Strucutred ASIC fiasco thread has made me think. >People are saying the FPGA revenues are going to grow, so.... >Which markets are FPGA heading into? >I mean, at the moment there's Comms, Medical, Military, Consumer. >Where are they going next? >Automotive I guess is coming, as is aerospace. You could put the two >together, as control electronics. Aerospace posses issues with ionizing radiation. >How about seeing them in a PC? When there's an advantage of reconfiguration ability over static asic massproduced at low price. A possible app could be builtin reciever for television, modem etc.. that can be adapted fast to new codecs post manufacture.Article: 98770
Just found this: http://direct.xilinx.com/bvdocs/userguides/ug230.pdf HenkArticle: 98771
Yes,The fpga can't handle 5v , so I must use the 74lv245 to convert the voltage.Now I have made the fpga work successfully,the problem is that levels of the signals (low effective) are all recognized high effective.I make the assert by high level,so the device don't work.Article: 98772
Are the jitter/phase specs RMS? If so, this probably tries to account for the crest factor (ratio of peak to RMS).Article: 98773
Ralf, I mean how can I connect the sensor to the FPGA board, how to connect the pin on FPGA board? Thanks. Laura Ralf Hildebrandt =E5=AF=AB=E9=81=93=EF=BC=9A > laura_pretty05@yahoo.com.hk wrote: > > > My Altera FPGA boards is UP2 development kit-programmable logic for > > education, with MAX EPM7128S &FLEX 10K EPF10K70 devices. > > Look at the board: there all pins of the FLEX_EXPAN_X pin rows are > numbered. (Only the numbers for pin 1,2 and 59,60 are printed. This is > the one row on the FLEX_EXPAN_X tables. The other row gives the internal > pin number of the FDGA. If you make pin assignments, this internal pin > number has to be used. >=20 > RalfArticle: 98774
NickC wrote: > So I'd say that the cost savings come from both testing and yield > improvements.... > > No? With the very high margins as they as they are, and I suspect the majority of the other direct and indirect costs for all purposes fixed, I suspect that testing costs are a redherring as far as any significant cost variable which would signficantly impact end user price. IE for every dollar of revenue, testing costs are maybe a penny (or two). If you asked for untested unpackaged die or full wafers prorated by statistical yield, I suspect there isn't much of a savings to be offered given that the real price setters are margins, other direct costs, and indirect costs which remain unchanged.
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z