Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
You need a 48-bit accumulator, clocked at 200 MHz. Maybe you have to split it. Check the timing alculator for the ripple-carry delay. And remember that you will generate 5 ns of jitter, which widely overshadows your superb frequency resolution. Peter Alfke, Xilinx Applications.Article: 99101
John_H wrote: > Isaac Bosompem wrote: > > Hi Ray and Peter, > > > > I am sorry for hijacking your thread Roger , but I think my question is > > relevant. > > > > I was thinking of using about 8 FIR (bandpass) filters in parallel to > > create a graphic equalizer. Now I know there are some phase problems > > with this method but it seems to me like a very logical way to go about > > this problem. I was wondering if you guys know of any better methods? > > > > I also was thinking of using 16 taps each. > > > > 320 FF's is not a lot actually. My XC3S200 (which is probably dirt > > cheap) has almost 4000 FF's. Enough for your filter network and much > > more. > > > > -Isaac > > Another great advantage to FPGA FIRs: most of the time the FIRs are > symmetric which allows half the taps (half the multipliers) to implement > the full FIR by adding t-d to t+d before multiplying by the common > coefficient, the implementation is more elegant. Hi John, I cannot see what you mean? Can you offer a quick example? -IsaacArticle: 99102
On Mon, 20 Mar 2006 08:46:29 -0600, "maxascent" <maxascent@yahoo.co.uk> wrote: >I would like to implement a DDS on a Spartan device. Here are is my spec. >Clocked at 200MHz. Max Output of 80MHz. 1uHz increments. Is this possible >on a Spatan? A more recent Spartan family, yes. How accurate do those 1uHz increments have to be? You can't get exactly 1uHz with a regular DDS. If your spec is <= 1uHz increments (rather than exactly 1uHz), then a 48 bit phase accumulator would do, as this gives 0.71uHz steps. A 48 bit accumulator will require pipelining to run at 200MHz, but that's not a big problem. The next question is what output waveform do you require? Will you have to produce a sine wave? Or will you simply be using the MSB of the phase accumulator as a crude approximation to a square wave? Regards, AllanArticle: 99103
Georgios Pouiklis wrote: > Hi, > > I'm looking for a V4FX devel. board, with both optical (e.g. SFP)MGTs and ddr2 memory (especially one with DIMM modules, if two ddr2 busses are available even better). > > Can someone suggest something, I haven't found one incorporating both features. > > Thanks, George Hello George, Take a look at this: http://www.fastertechnology.com/ http://www.fastertechnology.com/extras/pics/p6a/ The P6 is a V4FX based PCI card with four SFP connectors connected to the MGTs. It has one DDR2 SODIMM connector, and four SATA/SAS connectors (we have not yet created any SATA/SAS IP for them, but plan to in the future). The V4FX is configured by a Spartan 3E from a MiniSD card, and has access to the card after configuration to load software from it. We built our first run of cards with the V4FX60. The same PCB will also support the V4FX40 and the V4FX100, and we will support those some time in the future. We support customers creating FPGA designs for this card via EDK. We supply an EDK repository that has the board definition file and IO cores for this card. We also have a growing library of DSP cores. I am about to leave on a trip, so I will only be in sporadic contact for several weeks, but you can contact Charles Camp for more information. His email is cjcamp @ our domain name. My email is jhmccaskill @ ... I will only be able to check it on occasion. Our phone number is also on the web site. Regards, John McCaskillArticle: 99104
"Allan Herriman" <allanherriman@hotmail.com> wrote in message news:l0jt12hp0l0a31smf9nkr0ie0j0of70b25@4ax.com... > > How accurate do those 1uHz increments have to be? You can't get > exactly 1uHz with a regular DDS. > Well, from a 200MHz clock, you can get exactly 1uHz if you make the accummulator overflow at 200,000,000,000,000. i.e. accum <= (accum + freq) mod 2E14; The accummulator doesn't have to saturate at a power of two. HTH, Syms.Article: 99105
John_H wrote: > SO, are you trying to agitate again this late in the thread? Are you > trying to be the devils' advocate to help out the mentors on this board > or are you becoming an ass again? I do love to start my morning being > pissed; if that's your goal, you succeed rather well. Just being a devils advocate here, partly because I have a terrible time with my dyslexia when I'm tired or stressed and frequently get flamed for it, and just so you can be a bigot again. Tech speak, is part of this segment of the electronic world ... as I say ... get used to it. Feel free not to answer posters in tech speak ... they will appreciate the increased civility with the lack of your bitching.Article: 99106
Bitching about tech speak I find pretty lame. There are enough other forms of tech speak frequently used by posters in CAF. ROTF, IANAL, LOL, :), :^) .... how many people wish to have a few ass's bitching everytime they use part of this technical chat room language style? Not many I suspect ....Article: 99107
Hi, I bowsed through some threads about using the various Xilinx programming cables. It seems like with my Linux notebook without a parallel port I am doomend and not able to use any of them. At the moment I have a parallel cable IV and from what I read there is no way that I will be able to use that with the notebook, even when booting it with Windows, as no USB-to-Parallel adapter will work with it. The notebook does not have a PCMCIA port, so such a parallel adapter will not be an option either. Concerning the new Xilinx Platform USB cable I read that it does not work under Linux, so here the only option would be to boot the notebook with Windows to get that going. Is there really no way to get the parallel cable going with a USB-to-Parallel adapter? TIA GuenterArticle: 99108
On 20 Mar 2006 07:41:37 -0800, "Isaac Bosompem" <x86asm@gmail.com> wrote: > >John_H wrote: >> Isaac Bosompem wrote: >> > Hi Ray and Peter, >> > >> > I am sorry for hijacking your thread Roger , but I think my question is >> > relevant. >> > >> > I was thinking of using about 8 FIR (bandpass) filters in parallel to >> > create a graphic equalizer. Now I know there are some phase problems >> > with this method but it seems to me like a very logical way to go about >> > this problem. I was wondering if you guys know of any better methods? >> > >> > I also was thinking of using 16 taps each. >> > >> > 320 FF's is not a lot actually. My XC3S200 (which is probably dirt >> > cheap) has almost 4000 FF's. Enough for your filter network and much >> > more. >> > >> > -Isaac >> >> Another great advantage to FPGA FIRs: most of the time the FIRs are >> symmetric which allows half the taps (half the multipliers) to implement >> the full FIR by adding t-d to t+d before multiplying by the common >> coefficient, the implementation is more elegant. > >Hi John, > >I cannot see what you mean? Can you offer a quick example? An FIR filter is implemented as a dot product of a constant vector and a vector made up of the input samples delayed, y[n] = c[0].x[n] + c[1].x[n-1] + ... c[m-1].x[n-m+1] for an m tap filter. The c[n] are the coefficients. If the filter has a linear phase response, the coefficients are symmetric, so c[0] = c[m-1], c[1] = c[m-2], etc. We can group the expression for y[n] as follows: y[n] = c[0].(x[n] + x[n-m+1) + c[1].(x[n-1] + x[n-m+2]) + ... This has (roughly) halved the number of multipliers. I say roughly, because m is often odd. Regards, AllanArticle: 99109
On Mon, 20 Mar 2006 15:52:41 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >"Allan Herriman" <allanherriman@hotmail.com> wrote in message >news:l0jt12hp0l0a31smf9nkr0ie0j0of70b25@4ax.com... >> >> How accurate do those 1uHz increments have to be? You can't get >> exactly 1uHz with a regular DDS. >> >Well, from a 200MHz clock, you can get exactly 1uHz if you make the >accummulator overflow at 200,000,000,000,000. i.e. > >accum <= (accum + freq) mod 2E14; > >The accummulator doesn't have to saturate at a power of two. Depends on your definition of "regular" DDS I suppose... The logic to implement the pipelined mod 2e14 operation will probably be a lot harder than simply making a regular binary phase accumulator a few bits wider. Still, if the requirement is for a step size of *exactly* 1uHz, then the mod operation is needed. Regards, AllanArticle: 99110
<fpga_toys@yahoo.com> wrote in message news:1142870547.165588.256280@g10g2000cwb.googlegroups.com... > > John_H wrote: >> SO, are you trying to agitate again this late in the thread? Are you >> trying to be the devils' advocate to help out the mentors on this board >> or are you becoming an ass again? I do love to start my morning being >> pissed; if that's your goal, you succeed rather well. > > Just being a devils advocate here, partly because I have a terrible > time with my dyslexia when I'm tired or stressed and frequently get > flamed for it, and just so you can be a bigot again. > > Tech speak, is part of this segment of the electronic world ... as I > say ... get used to it. Feel free not to answer posters in tech speak > ... they will appreciate the increased civility with the lack of your > bitching. Congrats on being the first to push me into figuring out how to work the kill file. If all you do is rant, you have no place in my readings. I have not seen you ask for help on this forum. I have not seen you provide answers on this forum. You may have done both but my recollection is only ranting. If you choose to still think of me as a bigot because I think you and deliberately bad english have no place on this forum, feel free. - John Handwork fed up with John BassArticle: 99111
no way. the parallel cable will NOT work with usb-2-parallel AnttiArticle: 99112
I am not too concerened about getting exactly 1uHz. I plan to use sine, ramp, arb wave etc. I will use a external circuit with a comparator to gen a square wave. cheers JonArticle: 99113
"Allan Herriman" <allanherriman@hotmail.com> wrote in message news:tumt12l1jq2cnppqn4e9ki3iiceni5d5bb@4ax.com... > On Mon, 20 Mar 2006 15:52:41 -0000, "Symon" <symon_brewer@hotmail.com> > wrote: > <snip> >>Well, from a 200MHz clock, you can get exactly 1uHz if you make the >>accummulator overflow at 200,000,000,000,000. i.e. >> >>accum <= (accum + freq) mod 2E14; >> >>The accummulator doesn't have to saturate at a power of two. > > Depends on your definition of "regular" DDS I suppose... > > The logic to implement the pipelined mod 2e14 operation will probably > be a lot harder than simply making a regular binary phase accumulator > a few bits wider. Still, if the requirement is for a step size of > *exactly* 1uHz, then the mod operation is needed. <snip> The logic is extremely simple: When the MSbit changes, rather than adding PhaseInc add ((2^48)-(2e+14))/2+PhaseInc. The dual-increment value is very easy to support. I added the /2 in there for "whenever" the MSbit changes rather than just tracking the high-to-low transition.Article: 99114
Is the accuracy of your time base 1e-14? Calculate to 9 digits. Measure with a micrometer. Mark with chalk. Cut with an axe. Are your specs really necessary? "maxascent" <maxascent@yahoo.co.uk> wrote in message news:54CdncX_96TYXYPZRVn_vA@giganews.com... >I would like to implement a DDS on a Spartan device. Here are is my spec. > Clocked at 200MHz. Max Output of 80MHz. 1uHz increments. Is this possible > on a Spatan? > > Cheers > > JonArticle: 99115
"leaf" <adventleaf@gmail.com> wrote in message news:1142818282.728042.84490@i40g2000cwc.googlegroups.com... > John_H, its not that i'm saying the "after the single-cycle FRAME# > signal > is an idle state", what i mean is how can we follow state machine > design (as described in Appendix B of PCI Spec 3.0) to accomodate a > Configuration Read/Write.... > > > --- > young_leaf Just as a little guidance, the Xilinx core I use has separate signals for configuration control - CFG_HIT, C_READY, and C_TERM - rather than the target control - BASE_HIT[7:0], S_READY, S_TERM, S_ABORT. Perhaps your attempts to use the "hit" in your state machine is confused between configuration and target cycles?Article: 99116
All, I found that mozilla email supports a really useful feature: it is "ignore thread." I know, everyone else probably knows how to use this but me.... Anyway, for those who do not, go to Message, pull down, and you find "Ignore Thread." Do this while pointing to any message in a thread to be ignored, and poof! Does Exploder/Outhaus also have this feature? I don't know. Can you do this with Google? Again, I just don't know. For when the 'ranting' never seems to stop, or when you see a thread with posts you just wish to ignore. AustinArticle: 99117
"Leow Yuan Yeow" <nordicelf@msn.com> wrote in message news:441ed4e8$1@news.starhub.net.sg... > Hi, for a program such as > case state is > when S0=> > A <= B + C; > when S1=> > Z <= X + Y; > does it mean that 2 adders are generated, or will the synthesis recognize > the adder can be shared? > Or to I have to specifically write a multiplexor for the adder? Thanks! Adders are cheap in FPGAs. Two adders will be instantiated because 1) A and Z are different targets and 2) two muxes on the inputs require two levels of logic - the same amount needed to implement two adders. Usually the syntesis does a great job of optimizing where it makes sense. Using one adder for multiple results with a wide input mux will probably not benefit anyone. If you feel that this resource sharing is critical to your design, you will have to manually implement the multiplexers and thereby increase the total resources needed in your design.Article: 99118
"Austin Lesea" <austin@xilinx.com> wrote in message news:dvmoch$as412@xco-news.xilinx.com... > All, > > I found that mozilla email supports a really useful feature: it is > "ignore thread." > > I know, everyone else probably knows how to use this but me.... > Austin, With you on the newsgroup, we all learnt this long ago! H&Ks, Syms. p.s. Just kidding! :-)Article: 99119
Symon wrote: > Austin, > With you on the newsgroup, we all learnt this long ago! > H&Ks, Syms. > > p.s. Just kidding! :-) Without Austin, this list just wouldn't be the same :(Article: 99120
Leow Yuan Yeow wrote: > Hi, for a program such as > case state is > when S0=> > A <= B + C; > when S1=> > Z <= X + Y; > does it mean that 2 adders are generated, or will the synthesis recognize > the adder can be shared? > Or to I have to specifically write a multiplexor for the adder? Thanks! Are you optimizing for speed or area? -aArticle: 99121
Does it mean that Configuration cycles are not part of the state
machine (IDLE, B_BUSY ect.. )?
i guess i was not able to recognized it.
Anyway, if that's the case that solves it partially if not i don't
know...
my Hit is ORed bar_hits (i have BAR0 and BAR1) ( assynchronous of pci
clock )
-- Hit Detection --------------------------
match <= ( (Pci_Ad_Reg(31 downto 2) = BAR_0)
OR
(Pci_Ad_Reg(31 downto 4) = BAR_1) );
bar_hit_reg(0) <= '1' when ( match and ( cmdReg(1) = '1' ) ) else '0';
bar_hit_reg(1) <= '1' when ( match and ( cmdReg(0) = '1' ) ) else '0';
Hit <= ( bar_hit_reg(0) OR bar_hit_reg(1) ) ;
--------------------------------------------------
Pci_Ad_Reg is a registered Pci_Ad at rising edge of Pci_Clk...
is this advisable, also to register IRDY# and/or FRAME#?
---
Leaf
Article: 99122Outlook Express (which my Outlook uses as its newsreader) has "Ignore Conversations" and "Block Sender..." available from the Message menu. First time I've used it. "Austin Lesea" <austin@xilinx.com> wrote in message news:dvmoch$as412@xco-news.xilinx.com... > All, > > I found that mozilla email supports a really useful feature: it is > "ignore thread." > > I know, everyone else probably knows how to use this but me.... > > Anyway, for those who do not, go to Message, pull down, and you find > "Ignore Thread." Do this while pointing to any message in a thread to be > ignored, and poof! > > Does Exploder/Outhaus also have this feature? I don't know. Can you do > this with Google? Again, I just don't know. > > For when the 'ranting' never seems to stop, or when you see a thread with > posts you just wish to ignore. > > AustinArticle: 99123
I have seen PCMCIA/Cardbus plug in parallel ports that could solve your issue. Maplin in the UK have one http://www.maplin.co.uk/Module.aspx?ModuleNo=47119&criteria=parallel%20port&doy=20m3 .and some others on Ebay. Longer term we will be doing a fairly cheap S3E PCMCIA card that will have a programming solution integrated with it. It is on roadmap now as the result of some customer feedback and awaiting a free engineeriing slot. The integrated programmer can also be used to program other boards and will look like Parallel Cable III. John Adair Enterpoint Ltd. - Soon to be Home of Tarfessock1. The PCMCIA Spartan3E Development Board. http://www.enterpoint.co.uk <GHEDWHCVEAIS@spammotel.com> wrote in message news:1142871917.392979.167810@i40g2000cwc.googlegroups.com... > Hi, > > I bowsed through some threads about using the various Xilinx > programming cables. It seems like with my Linux notebook without a > parallel port I am doomend and not able to use any of them. > > At the moment I have a parallel cable IV and from what I read there is > no way that I will be able to use that with the notebook, even when > booting it with Windows, as no USB-to-Parallel adapter will work with > it. The notebook does not have a PCMCIA port, so such a parallel > adapter will not be an option either. > > Concerning the new Xilinx Platform USB cable I read that it does not > work under Linux, so here the only option would be to boot the notebook > with Windows to get that going. > > Is there really no way to get the parallel cable going with a > USB-to-Parallel adapter? > > TIA > > Guenter >Article: 99124
"leaf" <adventleaf@gmail.com> wrote in message news:1142877107.853006.74990@t31g2000cwb.googlegroups.com... > Does it mean that Configuration cycles are not part of the state > machine (IDLE, B_BUSY ect.. )? > i guess i was not able to recognized it. > > Anyway, if that's the case that solves it partially if not i don't > know... > > my Hit is ORed bar_hits (i have BAR0 and BAR1) ( assynchronous of pci > clock ) > > -- Hit Detection -------------------------- > match <= ( (Pci_Ad_Reg(31 downto 2) = BAR_0) > OR > (Pci_Ad_Reg(31 downto 4) = BAR_1) ); > > bar_hit_reg(0) <= '1' when ( match and ( cmdReg(1) = '1' ) ) else '0'; > bar_hit_reg(1) <= '1' when ( match and ( cmdReg(0) = '1' ) ) else '0'; > Hit <= ( bar_hit_reg(0) OR bar_hit_reg(1) ) ; > -------------------------------------------------- > > > Pci_Ad_Reg is a registered Pci_Ad at rising edge of Pci_Clk... > is this advisable, also to register IRDY# and/or FRAME#? > > > --- > Leaf Whether to use registered or unregistered values is dependent on when the values are valid versus when you use them. I was able to do what I needed done by looking at timing diagrams and signal descriptions. I have a local version of the PCI spec, v2.3. The state machine diagrams cover target and master. *If* the configuration cycle were part of the target state machine, then the "hit" would include a configuration hit, not a BAR hit since your BAR is typically configured through configuration cycles. *If* the target state machine covers configuration, you need to work in the config cycle qualifications (IDSEL asserted for the slot or device during the first cycle of FRAME#). Happy travels.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z