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Messages from 94825

Article: 94825
Subject: Re: [RANT] Webpack 8.1 editor totally messed up ?
From: Zara <yozara@terra.es>
Date: Wed, 18 Jan 2006 10:34:45 +0100
Links: << >>  << T >>  << A >>
On Wed, 18 Jan 2006 09:08:43 +0100, "Antti Lukats"
<antti@openchip.org> wrote:

>"Zara" <yozara@terra.es> schrieb im Newsbeitrag 
>news:39srs1pib0md5de88dnea8uds2gun9ba5i@4ax.com...
>> On Tue, 17 Jan 2006 23:00:54 +0100, "Antti Lukats"
>> <antti@openchip.org> wrote:
>>
>>>"Antonio Pasini" <removethis_pasini.a@tin.it> schrieb im Newsbeitrag
>>>news:43cd66bc$0$1087$4fafbaef@reader1.news.tin.it...
>> <snip>
>>>
>>>Hi
>>>
>>>after verifying the hot keys in 'flaot mode' I was a bit 'breathing' as it
>>>is a workaround, until I tried the
>>>
>>>|
>>>
>>>in float mode - and that doesnt work in float mode either - so we can say 
>>>it
>>>is confirmed the ISE 8.1 built in editor is useless for non US keyboard
>>>users :(
>>>
>>>well I still use my notepad.exe trick to copy the | into clipboard when I
>>>need it, but I guess others are defenetly not willing to use this kind of
>>>workarounds
>>>
>>>Antti
>>>
>>
>> I am using WebPack 8.1 with an Spanish keyboard, and have not found
>> yet any such problem (other problems, yes, but I have not rechecked
>> against SP1, so I will  not disclose them).
>>
>> Zara
>
>lucky you!
>
>the issues with the editor are the same SP1 or not, on my machine
>the 'alternate ALT' key labelled
>"Alt Gr"
>does not work in ISE editor and as this key is used to make
>|
>then it makes difficulties

Ok, yes you are right. Control combinations work, but Alt Gr don't, as
you say. The problem is I don't use | much, so I didn't notice it.

And I have just discovered a real nuisance/error: I have a "repository
project" (somewhre I have all cores designed for EDK, together with
thier test benches"): From the momet I added 15th VHDL module and 7th
VHDL Test bench, Check Syntax fails with nes Module without giving and
error identifying the lien of the error, and ModelSim is executed with
another different testbench from the last one added.

That much for new ISE's! Keeping up with Xilnx is a reall PITA.

Best regards,

Zara

Article: 94826
Subject: Re: [RANT] Webpack 8.1 editor totally messed up ?
From: Zara <yozara@terra.es>
Date: Wed, 18 Jan 2006 10:36:03 +0100
Links: << >>  << T >>  << A >>
On Wed, 18 Jan 2006 09:03:50 +0100, Johan Bernspång <xjohbex@xfoix.se>
wrote:

>Antti Lukats wrote:
>> "Antonio Pasini" <removethis_pasini.a@tin.it> schrieb im Newsbeitrag 
>> news:43cd66bc$0$1087$4fafbaef@reader1.news.tin.it...
>> 
<snip>
>
>Isn't it still possible to define your own external (favorite) editor in 
>ISE as it was before? In 7.1 it was done in Edit/Preferences dialog. 
>That is, when double clicking on a file in the 'Sources in 
>Project:'-view the code was opened in your predefined editor. I've been 
>doing this for quite a long time since I never really liked the ISE 
>editor...
>
>Another workaround could be to install the american keyboard layout 
>(which I'm using in my external editor since some common characters are 
>more accessable than on the swedish keyboard). A simple alt+left shift 
>in windows swaps the layout from your native one to the american one..
>
>As for me I havn't installed ISE 8.1i yet since I'm waiting for EDK...

It is possible to define an external text editor...but it will not
work!. problems with file paths, I think.

Zara

Article: 94827
Subject: Selling Microblaze based Machines
From: "Marco T." <marc@blabla.com>
Date: Wed, 18 Jan 2006 11:09:23 +0100
Links: << >>  << T >>  << A >>
Hallo,
I'm developing a system based on microblaze, some EDK cores and some custom 
cores.

If I plan to sell it, I must pay a fee to Xilinx for every core?

Many Thanks
Marco 



Article: 94828
Subject: Re: [RANT] Webpack 8.1 editor totally messed up ?
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Wed, 18 Jan 2006 11:12:45 +0100
Links: << >>  << T >>  << A >>
Zara wrote:
>>Isn't it still possible to define your own external (favorite) editor in 
>>ISE as it was before? In 7.1 it was done in Edit/Preferences dialog. 
>>That is, when double clicking on a file in the 'Sources in 
>>Project:'-view the code was opened in your predefined editor. I've been 
>>doing this for quite a long time since I never really liked the ISE 
>>editor...
>>
>>Another workaround could be to install the american keyboard layout 
>>(which I'm using in my external editor since some common characters are 
>>more accessable than on the swedish keyboard). A simple alt+left shift 
>>in windows swaps the layout from your native one to the american one..
>>
>>As for me I havn't installed ISE 8.1i yet since I'm waiting for EDK...
> 
> 
> It is possible to define an external text editor...but it will not
> work!. problems with file paths, I think.
> 
> Zara

Well, it works for me. I use, for instance, Crimson Editor. Thus I've 
set the Editors preferences to Custom and the command line syntax to 
cedt.exe $1. That opens any code file in my projects in that editor.



-- 
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Article: 94829
Subject: Re: Selling Microblaze based Machines
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 18 Jan 2006 10:14:52 -0000
Links: << >>  << T >>  << A >>
"Marco T." <marc@blabla.com> wrote in message 
news:dql44k$cg2$1@nnrp.ngi.it...
> Hallo,
> I'm developing a system based on microblaze, some EDK cores and some 
> custom cores.
>
> If I plan to sell it, I must pay a fee to Xilinx for every core?
>
> Many Thanks
> Marco
Are you using the cores in an Altera part? ;-)
Cheers, Syms. 



Article: 94830
Subject: Re: [RANT] Webpack 8.1 editor totally messed up ?
From: Zara <yozara@terra.es>
Date: Wed, 18 Jan 2006 12:09:41 +0100
Links: << >>  << T >>  << A >>
On Wed, 18 Jan 2006 11:12:45 +0100, Johan Bernspång <xjohbex@xfoix.se>
wrote:

>Zara wrote:
>>>Isn't it still possible to define your own external (favorite) editor in 
>>>ISE as it was before? In 7.1 it was done in Edit/Preferences dialog. 
>>>That is, when double clicking on a file in the 'Sources in 
>>>Project:'-view the code was opened in your predefined editor. I've been 
>>>doing this for quite a long time since I never really liked the ISE 
>>>editor...
>>>
>>>Another workaround could be to install the american keyboard layout 
>>>(which I'm using in my external editor since some common characters are 
>>>more accessable than on the swedish keyboard). A simple alt+left shift 
>>>in windows swaps the layout from your native one to the american one..
>>>
>>>As for me I havn't installed ISE 8.1i yet since I'm waiting for EDK...
>> 
>> 
>> It is possible to define an external text editor...but it will not
>> work!. problems with file paths, I think.
>> 
>> Zara
>
>Well, it works for me. I use, for instance, Crimson Editor. Thus I've 
>set the Editors preferences to Custom and the command line syntax to 
>cedt.exe $1. That opens any code file in my projects in that editor.

I use (in 7.1) crimson editor, cedt $1 -l:$2.

But when I use it in 8.1, with files *outside* the main project path,
it fails, because the file name passed to editor is "project
path"\"file path"\"filename". File path is OK with a file in the same
folder as the project, because it is empty. On all other cases, file
path is an absolutte path,and the result is invalid, of the sort:

"c:\myproject\c:\myotherproject\musource.vhdl"

And I do like to use folders to classify information, I hate flat
"all-in-one-folder" projects.

Bets regards

Zara

PS: As soon as I have alittel time to do it, I intend to file a bug to
Xilinx. But time is scarce.

Article: 94831
Subject: Xilinx 8.1i: Testbench waveform from VHDL netlist does not work ??
From: "Mahmoud" <mahmoud.kassem@gmail.com>
Date: 18 Jan 2006 03:13:38 -0800
Links: << >>  << T >>  << A >>
In ISE 8.1i creating a Testbench waveform does not work for a Schematic
TOP Level project with VHDL set as the language for HDL Functional
Language Model (Verilog is the default, in 8.1i the Simulation
generated language option was removed from the project properties)

Testbench waveform works for Verilog netlist and it works in 7.1i for
VHDL too. I tried 8.1i SP1 but it did not help.

Does anyone have the same problem?

Thanks


Article: 94832
Subject: Re: [RANT] Webpack 8.1 editor totally messed up ?
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Wed, 18 Jan 2006 12:39:33 +0100
Links: << >>  << T >>  << A >>
Zara wrote:
> I use (in 7.1) crimson editor, cedt $1 -l:$2.
> 
> But when I use it in 8.1, with files *outside* the main project path,
> it fails, because the file name passed to editor is "project
> path"\"file path"\"filename". File path is OK with a file in the same
> folder as the project, because it is empty. On all other cases, file
> path is an absolutte path,and the result is invalid, of the sort:
> 
> "c:\myproject\c:\myotherproject\musource.vhdl"
> 
> And I do like to use folders to classify information, I hate flat
> "all-in-one-folder" projects.
> 
> Bets regards
> 
> Zara
> 
> PS: As soon as I have alittel time to do it, I intend to file a bug to
> Xilinx. But time is scarce.

ah, I see... hopefully Xilinx has fixed that by the time EDK sees the 
daylight.

-- 
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Article: 94833
Subject: Re: [RANT] Webpack 8.1 editor totally messed up ?
From: Zara <yozara@terra.es>
Date: Wed, 18 Jan 2006 12:43:51 +0100
Links: << >>  << T >>  << A >>
On Wed, 18 Jan 2006 10:34:45 +0100, Zara <yozara@terra.es> wrote:

<snip>

>>
>>lucky you!
>>
>>the issues with the editor are the same SP1 or not, on my machine
>>the 'alternate ALT' key labelled
>>"Alt Gr"
>>does not work in ISE editor and as this key is used to make
>>|
>>then it makes difficulties
>
>Ok, yes you are right. Control combinations work, but Alt Gr don't, as
>you say. The problem is I don't use | much, so I didn't notice it.
>
>And I have just discovered a real nuisance/error: I have a "repository
>project" (somewhre I have all cores designed for EDK, together with
>thier test benches"): From the momet I added 15th VHDL module and 7th
>VHDL Test bench, Check Syntax fails with nes Module without giving and
>error identifying the lien of the error, and ModelSim is executed with
>another different testbench from the last one added.
>
>That much for new ISE's! Keeping up with Xilnx is a reall PITA.
>
>Best regards,
>
>Zara

Murphy: As soon as I have coded a new FSM, I have needed | character.
Now I hate ISE 8.l1, too!

Zara

Article: 94834
Subject: Re: [RANT] Webpack 8.1 editor totally messed up ?
From: "A.D." <stevenson@xxxxxxxx.it>
Date: Wed, 18 Jan 2006 13:13:36 +0100
Links: << >>  << T >>  << A >>
"Antonio Pasini" <removethis_pasini.a@tin.it> ha scritto nel messaggio 
news:43cd66bc$0$1087$4fafbaef@reader1.news.tin.it...
>I already saw the message from Antti about '|' char on German keyboard. So 
>I installed WebPack 8.1 with some trepidation...
>
> Sadly, *seems* that on XP SP2 with Italian keyboards almost NO control key 
> works.
>
> Can some other guy verify this ?

You're right! It is impossible to directly write symbols like {,},[,],@,#, 
etc,
using an Italian keyboard... I succeded only hitting Alt  + ASCII code
on the numerical pad! That's quite umbelivable... :-)
It's a pity, since from the other side, it seems that synthesis and 
implementation
in ISE8.1 achieve better results than previous releases (I've only made some
preliminary trials).

Regards,
A.D.



Article: 94835
Subject: Re: xilinx free Sample Pack info now also on Xilinx own webpages
From: "Brian Davis" <brimdavis@aol.com>
Date: 18 Jan 2006 04:38:07 -0800
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
>
> we are actually also able to support impact CableServer in remote mode so
> that will bring full support of all Xilinx supported cables instantly. I know how
> todo it, but  its not included yet in our current release.
>
 I haven't tried your programming S/W yet, maybe this weekend.

 BTW, my hope in ordering that cheap Digilent USB cable was to someday
accomplish the following:

 NSLU2 ($90 USD) + Digilent USB JTAG ($38 USD) = Network Download Cable

 But I haven't looked at the Digilent USB driver situation yet.

Brian


Article: 94836
Subject: xilmfs on flash
From: rajashekar_798@yahoo.com
Date: 18 Jan 2006 05:48:18 -0800
Links: << >>  << T >>  << A >>
Hello all,

I am using Xilinx fpga in my project. The board is ML403 and it
contains an 8MB flash.
I need to store few data files onto the flash and read these files
during the execution of my program on powerpc.
i have to use xilmfs as the filesystem on the flash and therefore i
created a mfs image of the files by using mfsgen utility according to
the xilinx reference manuals (oslib_rm, ps_ug).

for downloading this mfs image, the manual says
"Load this image file into memory at a suitable address, such as
0x10000000. You can
use XMD to download data, or you can use another tool to copy this data
to memory."

i tried to download using XMD command: dow -data image.mfs 0x22000000
where
   dow : command
   -data : option to indicate data file and not executable
  image.mfs : mfs filesystem image
  0x22000000 : flash memory starting address in my design where the mfs
image has to be downloaded.

in the design, i have included the flash drive on the hardware side and
enabled the xilmfs libary with the parameters set appropriately. i.e.,
baseaddress = 0x22000000, init_type = rom_image and size = 15960 bytes

in the code
#include "mfs_config.h"

main()
{
....
	mfs_init_fs(MFS_NUMBYTES, MFS_BASE_ADDRESS, MFSINIT_ROM_IMAGE);

	mnt1 = mfs_file_open("1_1_0.mnt", MFS_MODE_READ);
	xil_printf("\n%d\n",mnt1); // receiving -1 for mnt1 : the file opening
was unsuccessful.

...
}

and still not able to open the file and read from it.

i have crosschecked all the steps suggested in the manual many times
but found that i have done everything according to the manuals.

(i also tried to load the flash with the image.mfs using "Program Flash
Memory" option in the Menu but with no change in the result)

Any help in resolving the problem is deeply appreciated.

Thanks in advance,
Rajashekar


Article: 94837
Subject: ISE8.1 on Linux, first impressions
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Wed, 18 Jan 2006 13:55:58 +0000 (UTC)
Links: << >>  << T >>  << A >>
I just installed ISE 8.1 on Linux and these are my first
impressions:

* Project Navigator finally feels like a native Linux
  program. Previous versions often felt unresponsive and
  slow. With this version I no longer feel an immediate
  urge to build everything with Makefiles. This is great!

* Impact does not work out of the box with kernel
  version 2.6.15.1. I had to download linuxdrivers2.6.tar.gz
  and compile it. Furthermore, I had to edit the configure
  script in windrvr and make sure that UDEV was not used.
  (The udev interface seems to have changed in later 2.6.x
  series. The relevant symbols are also GPL-only now, so I don't
  think a binary only module can be distributed using UDEV in later
  2.6.x kernels.)
  I also had to install fxload to download the firmware to the
  programming cable and make sure /proc/bus/usb was mounted.

  All in all, I got it to work, but I really wish that Xilinx
  could remove the dependence on windriver. It is a real nuisance
  if you have to upgrade your kernel for whatever reason since you
  will need to recompile the kernel module in that case. If you
  happen to use parallel cable III or IV you can use XC3Sprog instead.
  You have to modify the program somewhat if you want to use it with
  Virtex-II FPGA:s. (You have to make sure that it recognizes the FPGA.)
  I haven't tested V2P or V4 FPGA:s with it though.


* Test benches seem to be handled much more sanely in Project
  Navigator. You can now for each source file decide if it should
  be used for simulation, synthesis or both.


/Andreas

Article: 94838
Subject: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
From: newsmailcomp5@gustad.com
Date: 18 Jan 2006 16:08:30 +0100
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> writes:

> you can connect Cable III to the JTAG and use impact, or I could

Can you play SVF files with impact? How? 


Thank you for your help.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 94839
Subject: clock generation with DOPPLER shift
From: "Ben Marpe" <Ben.Marpe@gmx.de>
Date: 18 Jan 2006 07:12:58 -0800
Links: << >>  << T >>  << A >>
Dear experts in this newsgroup,

in my diploma thesis i'm using a FPGA for baseband signal generation.
I'm interested in generating and varying a clock of 1Mhz which is
DOPPLER shifted +/- 5Hz due to movements between receiver and
transmitter.

The +/- 5Hz Doppler must be applied in a very "smooth" way, the step
resolution should be as fine as possible.

Any ideas how to do this on a (Xilinx) FPGA ?
The sine output of Xilinx LogiCore DDS isn't necessary and the step
resolution might be even a little bit finer for my application.

Thanks a lot for every single hint you can give to me !

Greetings, BEN


Article: 94840
Subject: Re: clock generation with DOPPLER shift
From: "John McCaskill" <junkmail@fastertechnology.com>
Date: 18 Jan 2006 07:23:05 -0800
Links: << >>  << T >>  << A >>

Ben Marpe wrote:
> Dear experts in this newsgroup,
>
> in my diploma thesis i'm using a FPGA for baseband signal generation.
> I'm interested in generating and varying a clock of 1Mhz which is
> DOPPLER shifted +/- 5Hz due to movements between receiver and
> transmitter.
>
> The +/- 5Hz Doppler must be applied in a very "smooth" way, the step
> resolution should be as fine as possible.
>
> Any ideas how to do this on a (Xilinx) FPGA ?
> The sine output of Xilinx LogiCore DDS isn't necessary and the step
> resolution might be even a little bit finer for my application.
>
> Thanks a lot for every single hint you can give to me !
>
> Greetings, BEN


Build a phase accumulator, and use the MSB as your clock.  This is an
accumulator that runs at a much faster rate than the clock you are
generating, you control the frequency of its output by setting the
input phase increment.  In you case, create the doppler by varying the
phase input value.

Regards,

John McCaskill


Article: 94841
Subject: Re: Spartan3 initialization with DSP
From: "Marco" <marco@marylon.com>
Date: 18 Jan 2006 07:36:09 -0800
Links: << >>  << T >>  << A >>
Thanks Antti, I'll go with option 2 as long as I have to use Spartan3,
do you think there's something I should take particular care about
working this way? I'll need to do the same for the DONE signal, in
order not to waste the DSP input.
Thanks, Marco


Article: 94842
Subject: Re: Migrating Project from Xilinx ISE 4.1 to 8.1?
From: "Drily Lit Raga" <midicad2001@yahoo.com>
Date: 18 Jan 2006 07:45:21 -0800
Links: << >>  << T >>  << A >>
Thanks Uwe!


Article: 94843
Subject: FPGA interface to FLASH
From: "GMM50" <gfm5050@gmail.com>
Date: 18 Jan 2006 07:45:50 -0800
Links: << >>  << T >>  << A >>
Helo all:

I'm uning an FPGA with a IP processor and it has an interface to INTEL
and AMD FLASH devices.  Both these devices offer burst operations for
read.  Namely the first read is at max access times (110 ns) but reads
to the next few (3 or 15) address are much faster (25 nsec) in acesss
times.

My question, has anyone developed logic to take advantage of this burst
transfer?
Or can anyone offer suggestions as to how to inplement this design?

There are a few more details in the rules for burst transfers but they
are specific to each device.

Thanks
George


Article: 94844
Subject: where to find the bfm files?
From: "bjzhangwn" <bjzhangwn@126.com>
Date: 18 Jan 2006 07:50:36 -0800
Links: << >>  << T >>  << A >>
I am designing an ata interface then I need a bfm files of ata device
to simulate,and the device must support the ultra dma
mode(UltraDMA/66).Thanks.


Article: 94845
Subject: EDK 8.1
From: Eli Hughes <emh203@psu.edu>
Date: Wed, 18 Jan 2006 11:13:43 -0500
Links: << >>  << T >>  << A >>
When can we expect an EDK that corresponds to the newest ISE release?

Article: 94846
Subject: data2bram and coregen
From: langwadt@ieee.org
Date: 18 Jan 2006 08:52:53 -0800
Links: << >>  << T >>  << A >>
Hi,

Does  anyone have a hint on how to get data2bram and coregen memory to
work together?

I have an SoC with some 32bit memory made up of four 8bit memories
generated with coregen, I've made a bmm file that defines the memory.
I can run data2bram with the bmm file and an .elf file and if I set the
output to verilog the init strings look resonable.
If I run the same bmm and .elf file on my bit file and use the updated
bit file to configure an FPGA DONE doesn't go high so I assume the bit
file is corrupt.

Is there a trick I should know about ?

data2bram does give me a warning the the memory is not LOC'ed, is there
a simple way to
get that info when the memory is generated with coregen?

(xc2v3000 and ISE5.1)

-Lasse


Article: 94847
Subject: Re: Data2Mem with CRC for Virtex FPGAs
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 18 Jan 2006 18:13:28 +0100
Links: << >>  << T >>  << A >>

"John D. Davis" <johnd@stanford.edu> schrieb im Newsbeitrag 
news:Pine.GSO.4.44.0601172313190.29583-100000@elaine15.Stanford.EDU...
>
> I have configured an XCV1000 as a data and instruction cache. It is
> connected to a external hard core. I would like to be able to update the
> contents of the caches without recompiling the file. I have been using
> Data2mem, but it appears that the CRC bits for the bitstream are not
> recalculated. They are always set to:  0xDEFC
>
> When data2mem modifies a bit file, it apparently turns off CRC checking
> by replacing the calculated CRC value with a constant 0xDEFC (which
> apparently spells DEFault Crc value).  0xDEFC is apparently supposed to
> tell the FPGA not to bother doing a CRC check on load because we were
> apparently TOO LAZY to calculate a correct value to check against.
>
> I found one (non-xilinx) web site that indicated that Virtex-II etc. will
> work just fine without a valid CRC value, but not so for Virtex.
>
> ngdbuild, or one of those tools near it, explicitly states that "-g
> CRC:DISABLE" is a valid command line option for Virtex-II but not Virtex,
> and indeed project navigator complains when I attempt "-g CRC:DISABLE" for
> our part.
>
> It seems clear at the moment that data2mem is not calculating CRC values
> but is calculating a bypass value instead; and it's less clear, but all
> signs seem to indicate, that that would work for Virtex-II and later parts
> but won't work for Virtex.
>
> I think there must be a way to get the CRC in the bitfile, hopefully using
> data2mem, but I haven't found it yet.
>
> Has anyone run into this problem and solved it? Here is a diff of the two
> bit files.

hi John,

we are using internally libraries that read bitstreams and recalculate the 
CRC,
it is currently being used to fix the oscillator optons for Spartan3e, but 
with
no big mods it should be able to process virtex bitstreams as well.

so as one option is to have a simple command line tool that post-process
the bitstream and injects the proper CRC.

and you are right DEFC is DEFault Crc that is needed to be written
in place of real CRC and also in place of autoCRC, also the CRC
bypass bit in COR must be set.

and as noted not all familes support the CRC bypass

Antti













Article: 94848
Subject: Re: How to set Xilinx compiling parameters to get PCI setup time right
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 18 Jan 2006 17:19:52 GMT
Links: << >>  << T >>  << A >>
You're looking at poorer setup times.  Have your clock-to-out times skewed 
as well?

The routing of the clock can give you large differences in some Xilinx 
devices.  A clock input pin doesn't HAVE to route to the BUFG(MUX) closest 
to it and encounters a larger delay moving to the other side of the chip. 
Similarly, the DCM/DLL can use buffers and input pins not along the same 
side.

If clock routing is responsible for some or all of the differences, the 
input setup and clock-to-out times will shift the same direction; if setup 
time is worse, clock-to-out will be better.  Sometimes the clock resources 
have to be LOCed to get 100% repeatability.


<wtxwtx@gmail.com> wrote in message 
news:1137516323.958631.67290@g43g2000cwa.googlegroups.com...
> Hi,
> I recently switched from Xilinx 6.3 to Xilinx 7.1.i4.
>
> After the first compilation, I was surprised to find that PCI input
> setup time is about 1.5 ns, excellent configuration! 66MHz PCI input
> setup time is 3.0 ns. Usually I got 2.9xxns from 6.3 version.
>
> But recently my compilation parameters changed and the PCI input setup
> time is returned back to around 3.0 ns, and most of time, it is beyond
> 3.0 ns that leads to an unsuccessful compilation result.
>
> Can you give some tips on which parameter setting caused the dramatic
> change for the PCI input setup time?
>
> Thank you.
>
> Weng
> 



Article: 94849
Subject: Re: FPGA interface to FLASH
From: "PeteS" <ps@fleetwoodmobile.com>
Date: 18 Jan 2006 09:23:44 -0800
Links: << >>  << T >>  << A >>
GMM50 wrote:
> Helo all:
>
> I'm uning an FPGA with a IP processor and it has an interface to INTEL
> and AMD FLASH devices.  Both these devices offer burst operations for
> read.  Namely the first read is at max access times (110 ns) but reads
> to the next few (3 or 15) address are much faster (25 nsec) in acesss
> times.
>
> My question, has anyone developed logic to take advantage of this burst
> transfer?
> Or can anyone offer suggestions as to how to inplement this design?
>
> There are a few more details in the rules for burst transfers but they
> are specific to each device.
>
> Thanks
> George

I assume you mean something like Intel Strataflash which offers a page
read mode using the ADV line?

It's pretty simple to implement. See how it's done with a processor
(try the Intel PXA270) - get the development manual and look at the
timing.

The basic trick in the state machine is to hold off after starting the
burst read for some number of clock cycles, then treating all reads the
same, so something like

// state BURSTSTART
always @(posedge clk)
begin
holdoffcount <= holdoffcount+1;
if(holdoffcount == requiredwait)
begin
     state <= NormalReadCycle; // moves us to the next state.
end
end

// remember to zap the counter before starting a bus transaction

that holds you off in the start phase (before any data transfer) until
some number of clocks - so figure out the difference in clocks between
first read and subsequent reads (and round that value UP !), then fall
through and just use the normal timing beyond that.


As all the devices are different, you'll need to tune accordingly (or
do as we do in processors and have a writeable register for the number
of clocks to wait between certain events).

Cheers

PeteS




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