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Please let me know any Xilinx distributor from any European Union country in order to by the HW-SPAR3_CPLD-DK kit. Xilinx price is $99 but if Imported from USA including Shipping and Taxes the final price is near $200Article: 94701
Have a look here http://www.xilinx.com/company/sales/ww_disti.htm for Xilinx distributors. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk "Apostol" <castel-electronics@ath.forthnet.gr> wrote in message news:1137437619.910594@athnrd02... > Please let me know any Xilinx distributor from any European Union country > in order to by the > HW-SPAR3_CPLD-DK kit. Xilinx price is $99 but if Imported from USA > including Shipping and Taxes the final price is near $200 > >Article: 94702
I have a V2P chip and am using both PPCs. Each has its own PLB bus and each PLB bus is connected to a small dual-ported BRAM (amongst other things). The idea is for them to pass messages to each other through this BRAM, but I was noticing mangled data. The shared BRAM is dedicated to this message-passing (no code or other data lives there). Trying to reduce the problem, I started using XMD to debug. The two programs initiallizng the respective programming BRAMs are just a few lines each now and don't even reference the shared BRAM, so there is no code accessing the shared area. Now when I use XMD (on either processor), I can read/write the shared BRAM. The wierdness is that consecutive reads can give different results. I am assuming this is the behavior I was initially seeing with my message-passing program and isn't a problem with XMD. The read results are ususally not wildly different... it is as if a value from one location sort of jumps to an adjacent location or lives in a couple locations at once, then on the next read, something variant of this. Clearly not the behavior I'd hope for. When using XMD to fiddle with the off-chip RAM on the board, it holds values just fine. I can provide more details if helpful, but I was just wondering if anyone has any idea what is going on here. Any advice on how to debug further would be appreciated. Unfortunately can't use ModelSim because of the license requirements on the IBM stuff (PLB bus, etc). Just hoping it is something simple I have neglected... Thanks in advance, JoeyArticle: 94703
<wtxwtx@gmail.com> wrote > Hi, > The following is the part of my code to drive 4 output ports with one > combinational signal: > LatchA : process(CLK66M) > begin > if(CLK66M'event and CLK66M = '1') then > A0_O <= RowPtr; > A1_O <= RowPtr; > A2_O <= RowPtr; > A3_O <= RowPtr; > ... > endif; > end process; > > 1. RowPtr is a combinational signal; > 2. A0_O, ... are 4 separate output pins; > 3. I thought that Xilinx compiler 7.1 should create 4 registers for > each output pin and the output pins should be located in the I/O > blocks. But they are not. Only one middle register is created and is > located in the geometric center of 4 output pins, then 4 wires are > connected to the 4 output pins, leading to clock-to-output time > violations. > > My question is: > How do I direct Xilinx compilter to generate 4 individual registers for > the above equations? If you are using XST, disable "Equivalent Register Removal" in the Xilinx Specific Synthesis Options. MichaelArticle: 94704
My next step would be to simulate the design. What license requirements are holding you up? Everything for simulation with Modelsim is available from Xilinx in EDK/ISE. Paul Joseph wrote: > > I have a V2P chip and am using both PPCs. Each has its own PLB bus and > each PLB bus is connected to a small dual-ported BRAM (amongst other > things). The idea is for them to pass messages to each other through > this BRAM, but I was noticing mangled data. The shared BRAM is > dedicated to this message-passing (no code or other data lives there). > Trying to reduce the problem, I started using XMD to debug. The two > programs initiallizng the respective programming BRAMs are just a few > lines each now and don't even reference the shared BRAM, so there is no > code accessing the shared area. Now when I use XMD (on either > processor), I can read/write the shared BRAM. The wierdness is that > consecutive reads can give different results. I am assuming this is > the behavior I was initially seeing with my message-passing program and > isn't a problem with XMD. The read results are ususally not wildly > different... it is as if a value from one location sort of jumps to an > adjacent location or lives in a couple locations at once, then on the > next read, something variant of this. Clearly not the behavior I'd > hope for. When using XMD to fiddle with the off-chip RAM on the board, > it holds values just fine. > > I can provide more details if helpful, but I was just wondering if > anyone has any idea what is going on here. Any advice on how to debug > further would be appreciated. Unfortunately can't use ModelSim because > of the license requirements on the IBM stuff (PLB bus, etc). Just > hoping it is something simple I have neglected... > > Thanks in advance, > JoeyArticle: 94705
I'm also one of those rebirth hobbyists. I was a hobbyist up until the mid to late 80's. Probably the most ambitious stuff I tried was a 68020 board with dynamic ram, running at 16Mhz, all on a big wire-wrap board. Back then, the board was stuffed with LSTTL chips. The board was none too reliable -- flex it the wrong way, and something broke. But on a good day, it worked. I tried to make some improvements for reliability. I played with bipolar PALs. Expensive, and I really hated throwing them away when I made a mistake in programming them. I also tried making my own double sided printed circuit boards. Lithographic film, developed in a close bathroom in my apartment. Needless to say, making and drilling these boards was a fiasco. So I just stored all my parts away for 15 years or so. What's changed to get me back into this hobby? Three things. 1) Flash programmable microcontrollers, i.e. PICs and AVRs. None of this burning EPROM business anymore. No wiring up SRAM or DRAM. Just program and go. 2) Low cost schematic/PCB design software and PCB boardhouses. I wouldn't even attempt to make my own boards anymore. And I can get 6 and 8 layer boards, something I'd never attempt as a hobbyist. Woohoo! Soldering those SMD components is a bit of a challenge, especially the PQFP208 packages. Of course there are some interesting things in BGA packages, but I haven't reached the level of craziness to try the toaster over reflow method. 3) FPGA's! I last looked at programmable logic in the bipolar PAL days. I happened to be looking through a Digikey catalog one day and noticed stuff from a company called Xilinx. Hmm, checked their website. Hey, this is pretty neat stuff! And since Digikey (and Xilinx to a limited extent, hint, hint) allow small orders, I can actually get parts. In the 80's, I often had to try going though a rep or Big Distributor, and most wouldn't deal with me at all. So nowdays, I typically design a board with a microcontroller on it, slap a Spartan chip of some sort on it as well, and worry about how to make it work later. Aside from a few early gotchas, like trying to use an input only pin on an FPGA as an output, this has worked very well. I've weaned myself away from schematics for CPLD/FPGA design and taught myself VHDL. To me at least, it's a very different mindset to think in, but it's getting easier as I do more designs. I still struggle with VHDL which looks legal but isn't quite right for synthesis, trying to interpret some obscure message from WebPack. Now I'm looking to do even more. I keep checking to see when the Spartan 3E board is available. I've worked with the Spartan 3 eval board from Digilent, so I'm anxious to see what's next. And then there's the little matter of the ML403 kit Xilinx offers with the Virtex 4 FX and the EDK. As a hobbyist, I'm cringing at the thought of putting $895 into this. At the same time, I'm going, hmm, what could I do with the PowerPC chip or the MicroBlaze? Hmm, no it's too much money.... But I keep thinking about it :-) I know Xilinx doesn't really target people like me, but I keep hoping for a half-price sale or a hobby bundle on the ML403 (no support, no commercial use or you give up your first born, etc). Cheers, Scott slburris@earthlink.net In article <1137338637.940229.315040@g49g2000cwa.googlegroups.com>, coreyhahn@gmail.com says... > Well, I guess I would be one of those "rebirth" hobbyists. I am > younger and just "discovered" the fpga. I was under the impression > that things like this were very expensive, but when I see starter kits > for $150, I had to snatch one up and try it out. For the last 5 months > I have been feverishly programming and learning with Webpack 7.1 > implimenting different ideas on codecs, processor cores, and so on. > Now I that I have a handle on whats available and possible on most > platforms I bought my first dev board a couple of days ago. I can't > wait for sun to open up there sparc cores. So many ideas so little > time!! > > I can't believe I went through my undergraduate education without > trying fpga's out, and my focus on RF and optics was not very close to > VLSI or control. After 5 months though there are a ton of optics > processing problems that can be sped up with fpgas. Like I said, can't > wait to start debugging!! > > So much to do, so little time... > new Hobbyist > >Article: 94706
wtxwtx@gmail.com wrote: > Hi Sylvain, > signal A0_O : std_logic_vector(12 downto 0); > signal A1_O : std_logic_vector(12 downto 0); > signal A2_O : std_logic_vector(12 downto 0); > signal A3_O : std_logic_vector(12 downto 0); > attribute MAX_FANOUT: string; > attribute MAX_FANOUT of A0_O: net is "1"; > attribute MAX_FANOUT of A1_O: net is "1"; > attribute MAX_FANOUT of A2_O: net is "1"; > attribute MAX_FANOUT of A3_O: net is "1"; > > Still error: > parse error, unexpected OPENPAR, expecting COLON > > signal A0_O: std_logic_vector(12 downto 0); > signal A1_O: std_logic_vector(12 downto 0); > signal A2_O: std_logic_vector(12 downto 0); > signal A3_O: std_logic_vector(12 downto 0); > attribute KEEP: string; > attribute KEEP of A0_O: signal is "true"; > attribute KEEP of A1_O: signal is "true"; > attribute KEEP of A2_O: signal is "true"; > attribute KEEP of A3_O: signal is "true"; > > Still error: > parse error, unexpected OPENPAR, expecting COLON > > All attribute statements are below the definitions of those signals. > > Thank you for further help. > > Weng > cut & paste from some of my code that works : --- cut --- signal rnd_ctrl : std_logic; attribute keep : string; attribute keep of rnd_ctrl : signal is "true"; --- /cut --- so it's signal instead of net your right but it should work ... note that I'm not sure if the "keep" will be useful for you ... the max_fanout looks a better option. SylvainArticle: 94707
does anybody use opwenwince jtag for this pourpose? Gabor ha scritto: > For PROMs I generally make Intel Hex files (.mcs) although the > programmer > we use from BP can take many different file formats. I only use this > for > programming parts off-board. For in-system programming you generally > need a file format that works with your embedded software. For Xilinx > bitstreams > I generally prepare a "Hex" format file which is just a stream of hex > characters > with no header or other information (just the bits, ma'am). This I > usually convert > to a binary file for use by the embedded system (to reduce file size. > > > Antti Lukats wrote: > >>"antonio bergnoli" <bergnoli@pd.infn.it> schrieb im Newsbeitrag >>news:43cb5fd1$2_2@x-privat.org... >> >>>Hi, >>>I want to know if anybody has never programmed fpga or proms not using >>>Impact or Quartus programmer but other (third party) tools. If yes, how ? >>>which are the file formats to use? >>>Thanks in advance. >> >>lots of people do that. >> >>most of the info is available, sometimes it needed to reverse engineer SVF >>or BSDL files to complement the public information >> >>there are different formats that can be used depending on device targetted >> >> >>-- >>Antti Lukats >>http://www.xilant.com > >Article: 94708
Tobias Weingartner wrote: > > I happen to disagree. We are all entitled to our opinions of course. > If the vendors would have a well defined format to "compile" to, and > a good library/port for a program to be able to take this format and > then generate a bitstream, that would be a start. Note, I'd want to > have the source available to be so that I could port this last bit of > "technology" to my favourite OS (by choice or necessity). > > I can't believe that these things are anything but simple portable ANSI > C (or some derivative)... > The problem is the bitstream is very tightly tied to the architecture of the FPGA cell. Having a well defined format tightly constrains the FPGA architecture to the one the bitstream format is published for. What that means is that either the format has to change for every fpga variant out there, now and in the future, or the FPGA has to be frozen in order to comply with the bitstream format. There is far more coupling between the bitstream in an FPGA and its hardware than there is between an instruction set and a processor architecture because of the fine granularity of the configuration of the FPGA. In other words, an instruction set in a microprocessor controls relatively few connections between some very complex blocks. The FPGA bit stream controls many many connections between lots of small simple blocks, so if the bitstream format is predefined by a standard there is very little lattitude for evolving the FPGA's structure. I'm not sure I see what the big push for having bitstream access is. I've yet to see a compelling need for it that is not addressed by the existing tools (there is always XDL if you really want to bit bang). The only reason that seems to surface is to allow outside parties to develop their own place and route tools. Frankly, I don't think the complexity of modern FPGAs is such that this type of undertaking can improve on or even compete with the free place and route tools already offered by the FPGA vendors in the timeframe between device introduction and obsolescence. Anyway, for those hadry enough to try, as I said, the XDL tools do give you enough access to every step of the design flow to allow you to play with any step you feel compelled to play with.Article: 94709
On 2006-01-16, tony.p.lee@gmail.com <tony.p.lee@gmail.com> wrote:
> John,
>
> Is it true that uCLinux does not have protected kernel memory?
> A simple programming loop index comparision error can wipe out the
> system memory including kernel.
Yes, that's the point of uCLinux, to support machines
that have a flat address space.
> I had to deal with this kind of problems in vxWorks days, it was
> a nightmare.
Me too, man.
> I am using PPC with Linux and it has been a joy to use. There
> were one bugs shows up in test group that crash one program - first
> crash in 6 months. It is solved in 5 mintues after looking a the
> core dump.
So choose a processor supported by (non-uC) Linux.
There are a dozen architectures to choose from.
Leon Sparc can target an FPGA, I'm pretty sure it
has virtual memory. Presumably slower and bigger
than microBlaze for FPGA work, but it should be more
reliable from your perspective.
- Larry
Article: 94710Thanks for the quick reply Paul, I went through trying to get the necessary tools to simulate the PLB bus using the BFM (bus functional model?) stuff a while ago. Turned out I need a more advanced version of ModelSim than we had... got a trial version of the PE(?) version which was necessary for the BFM stuff I think. That trial ended in 30 days, and since then I haven't even considered simulating anything. We are a little behind the times I guess, just upgraded to EDK 7.1 a couple weeks ago, maybe not so hard now to get the necessary BFM stuff? Guess I need to look into it, the Xilinx modelsim stuff is all a little confusing/frustrating... Any other advice appreciated... JoeyArticle: 94711
Just an update: Still using XMD, poking other on-chip memory locations, I can see that they behave normally. The only obvious difference I see right now is the fact that I am using both ports in the shared BRAM and not the others. Any advice still appreciated! JoeyArticle: 94712
Joseph wrote:
> Thanks for the quick reply Paul,
>
> I went through trying to get the necessary tools to simulate the PLB
> bus using the BFM (bus functional model?) stuff a while ago. Turned
> out I need a more advanced version of ModelSim than we had... got a
> trial version of the PE(?) version which was necessary for the BFM
> stuff I think. That trial ended in 30 days, and since then I haven't
> even considered simulating anything. We are a little behind the times
> I guess, just upgraded to EDK 7.1 a couple weeks ago, maybe not so hard
> now to get the necessary BFM stuff? Guess I need to look into it, the
> Xilinx modelsim stuff is all a little confusing/frustrating...
>
> Any other advice appreciated...
You really want to be able to simulate this. The bus functional model is
not strictly necessary. If all you care about is basic read/write
accesses, you can create your own model of the PPC that works reasonably
enough to tell you what is going on. I created one, largely by trial and
error.
For example, here are a couple of (VHDL) procedures I use. I stick them
within a test file that is embedded within a wrapper that simply hard
sets all the unused signals. It looks like I set the "Reset Interface"
and "Instruction Cache Unit" signals to all '0', and all the rest of the
unused signals to '1'. The procedures below implement the "Data Cache
Unit" interface.
procedure sread(addr : in std_logic_vector(0 to C_PLB_AWIDTH-1)) is
begin
wait until rising_edge(PLB_Clk);
M_request <= '1';
M_RNW <= '1';
if addr(29) = '1' then
M_BE <= X"0F";
else
M_BE <= X"F0";
end if;
M_size <= (others => '0');
M_type <= (others => '0');
M_ABus <= addr;
if PLB_MAddrAck = '0' then
wait until PLB_MAddrAck = '1';
end if;
wait until rising_edge(PLB_Clk);
M_request <= '0';
M_RNW <= '0';
M_BE <= X"00";
M_ABus <= (others => '0');
if PLB_MRdDAck = '0' then
wait until PLB_MRdDAck = '1';
end if;
if addr(29) = '1' then
RD_DATA <= PLB_MRdDBus(32 to 63);
else
RD_DATA <= PLB_MRdDBus(0 to 31);
end if;
wait until rising_edge(PLB_Clk);
end procedure sread;
procedure swrite(addr : in std_logic_vector(0 to 31);
data : in std_logic_vector(0 to 31)) is
begin
wait until rising_edge(PLB_Clk);
M_request <= '1';
M_RNW <= '0';
M_size <= (others => '0');
M_type <= (others => '0');
M_ABus <= addr;
if addr(29) = '1' then
M_BE <= X"0F";
-- M_wrDBus(0 to 31) <= (others => '0');
M_wrDBus(0 to 31) <= data;
M_wrDBus(32 to 63) <= data;
else
M_BE <= X"F0";
M_wrDBus(0 to 31) <= data;
-- M_wrDBus(32 to 63) <= (others => '0');
M_wrDBus(32 to 63) <= data;
end if;
if PLB_MAddrAck = '0' then
wait until PLB_MAddrAck = '1';
end if;
wait until rising_edge(PLB_Clk);
M_request <= '0';
M_RNW <= '0';
M_BE <= X"00";
M_ABus <= (others => '0');
if PLB_MWrDAck = '0' then
wait until PLB_MWrDAck = '1';
end if;
wait until rising_edge(PLB_Clk);
M_wrDBus <= (others => '0');
end procedure swrite;
Article: 94713Hi Tony, tony.p.lee@gmail.com wrote: > Is it true that uCLinux does not have protected kernel memory? > A simple programming loop index comparision error can wipe out the > system memory including kernel. Yes, that's true. The "uC" in uClinux implies no MMU, so no memory mapping or protection. > If this is the case, have you seen this kind of problem with > uCLinux.? > Do you think this is a real issues for uCLinux + microbraze > environment? It is no more of an issue for uClinux + MicroBlaze than for any of the other uClinux targets out there. You could argue that the millions of deployed uClinux devices out there say it's not a major issue. More helpfully, however, because it's all Linux, you can debug your app code on a desktop machine, where coredumps etc will be able to help find these kinds of errors. You might need stub device drivers for embedded peripherals, but this is not a major task. Bugs in kernel drivers are always going to hurt. Even with MMU a driver bug can bring down the kernel. > I had to deal with this kind of problems in vxWorks days, it was > a nightmare. A few bugs that is trivial (gdb the core dump) for the > protected kernel environment took a team of sw engineers 2 months > to reproduce and solved. The use of a desktop linux environment as a prototyping / development / simulation environment can really help here. > I am using PPC with Linux and it has been a joy to use. There > were one bugs shows up in test group that crash one program - first > crash in 6 months. It is solved in 5 mintues after looking a the > core dump. No doubt. There are many factors to consider when choosing a CPU, and operating system. If board costs are tight, PPC simply may not be an option. You can put a MicroBlaze Linux system + app-specific logic in a Spartan3-400 + DRAM - that can be pretty compelling. Regards, JohnArticle: 94714
Hi Sylvain, Thank you for your help. The grammar now is working. signal A0_O : std_logic_vector(12 downto 0); signal A1_O : std_logic_vector(12 downto 0); signal A2_O : std_logic_vector(12 downto 0); signal A3_O : std_logic_vector(12 downto 0); attribute MAX_FANOUT: string; attribute MAX_FANOUT of A0_O: signal is "1"; attribute MAX_FANOUT of A1_O: signal is "1"; attribute MAX_FANOUT of A2_O: signal is "1"; attribute MAX_FANOUT of A3_O: signal is "1"; Now the second problem seems to be more serious than the first compilation. When I don't use MAX_FANOUT, the combinational goes to a register that is allocated in the geometric center of 4 output ports. TS_clk66m = PERIOD TIMEGRP "clk66m" 15 ns | 15.000ns | 14.886ns | 8 *TIMEGRP "SDRAM" OFFSET = OUT 8.1 ns AFTER | 8.100ns | 9.184ns | 1 Now with introduction of MAX_FANOUT * TS_clk66m = PERIOD TIMEGRP "clk66m" 15 ns | 15.000ns | 15.468ns | 9 * TIMEGRP "PCI" OFFSET = IN 3 ns BEFORE COM | 3.000ns | 3.791ns | 1 * TIMEGRP "SDRAM" OFFSET = OUT 8.1 ns AFTER | 8.100ns | 9.042ns | 1 That is what I was expecting when I was writing the first post: For example, in my case, My running timing requirement is met, but clock-to-output timing is violated. If all registers are located in I/O blocks, clock-to-output timing may be met, but the running frequency may be violated. In that situation, all 4 registers should be located near I/O blocks to meet both timing requiments. Not like current case that either one register is located in the geometri center or in I/O blocks. It seems now I need a Xilinx Field Engieer to help for the new attribute. Weng Michael Rhotert wrote: > <wtxwtx@gmail.com> wrote > > Hi, > > The following is the part of my code to drive 4 output ports with one > > combinational signal: > > LatchA : process(CLK66M) > > begin > > if(CLK66M'event and CLK66M = '1') then > > A0_O <= RowPtr; > > A1_O <= RowPtr; > > A2_O <= RowPtr; > > A3_O <= RowPtr; > > ... > > endif; > > end process; > > > > 1. RowPtr is a combinational signal; > > 2. A0_O, ... are 4 separate output pins; > > 3. I thought that Xilinx compiler 7.1 should create 4 registers for > > each output pin and the output pins should be located in the I/O > > blocks. But they are not. Only one middle register is created and is > > located in the geometric center of 4 output pins, then 4 wires are > > connected to the 4 output pins, leading to clock-to-output time > > violations. > > > > My question is: > > How do I direct Xilinx compilter to generate 4 individual registers for > > the above equations? > > If you are using XST, disable "Equivalent Register Removal" in the > Xilinx Specific Synthesis Options. > > MichaelArticle: 94715
Symon wrote: > > Aha, now I see what you're saying, there's a new feature! Cool, I'll try it, > even though it goes against my principle of waiting for SP3! > Any wagers whether they've changed the #@%$&!! pan & zoom functions (again) in FPGA editor 8.x ? Also, for other 7.1i FPGA Editor "features", see Answer Records 22469, 21667, and 22217 ( loss of config info on manual comp edits ) BrianArticle: 94716
Brannon wrote: > "one cycle" is the whole issue. I don't have any spare cycles. This has > to be done asynchronously. Whatever you do, don't ever feed async inputs into a Virtex-II BRAM. And never clock BRAMs, while enabled, from an unlocked DCM. See Answer Record 21870 aka "How do I randomly clobber bits in my read only BRAM function" or the recent thread starting here: http://groups.google.com/group/comp.arch.fpga/msg/458bb7a6301318d9 BrianArticle: 94717
Hobbyists. Now there's a term you don't often hear amongst the next generation. If the hobbyist is going to make a comeback in this country (US) it is going to take more than a low-cost, high capability FPGA. With the watered down public education serving up a non-challenging, push them through curriculum, what hope is there for technologists in this country over the next few decades? Do you know how many times I've walked into a gas station and encountered a teen who can't carry through on a simple transaction? The youth today aren't--for the most part--go getters: they lack direction, motivation, and personal responsibilty. They are not problem-solvers, they're problem-makers who go though life thinking that somebody is always going to wipe their backside. Give them a kit of parts and ask them to make it work-ha! They might have to read a book! It has been reported that high school graduates are increasingly choosing non-technical fields to major in. The technical fields are too challenging, require too much work, and interfere with the 50hrs/week of playing video games. Where are the Heathkitter's of the next generation? I've ranted long enough........................... "Kevin Morris" <kevin@techfocusmedia.com> wrote in message news:1137096913.255199.239090@o13g2000cwo.googlegroups.com... > I'm writing a feature article for FPGA Journal (www.fpgajournal.com) > about FPGAs and the re-birth of the electronics hobbyist. My theory is > that electronics as a hobby went through a "dark age" period, maybe > from the early/mid 1970s until recently becuase of the inaccessibility > and cost of designing with state-of-the-art technology. Radio Shack > shifted their focus from 50-in-1 project kits and hobbyist parts to > selling toys, cell-phones, and stereo equipment. > > Now, with the emergence of low-cost, high-capability FPGAs, development > boards, and design software, I see a new age of hobbyist activity > beginning (as often evidenced in this group). > > I'm looking for a few people that would be willing to express views on > this topic for the article. > > I know, Austin will probably post a strong technical argument that > Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from > Altera will send me a Cubic Cyclonium prototyping paperweight (they're > very cool), and Actel and Lattice people will post just to remind us > that they have low-cost kits too, but I'm primarily interested in some > info from real, live, "working" hobbyists. > > Any takers? >Article: 94718
Rob, the first adult who is known to have complained about the youth of his time being lazy do-no-gooders, was Socrates, more than 2400 years ago. And each generation after him has repeated the complaint, while benefitting from the progress brought about by those youths, once they had matured. Look at the kids coming out of Stanford, starting SUN, Yahoo, and Google. Most of the detailed work in my company is done by engineers in their late twenties and thirties, obviously with necessary guidance from us more experienced folks... If kids are not interested in science, that is mainly the fault of educators, industry and management, creating a a bad learning and career environment. I prefer the original posting of this thread: How can FPGAs envigorate individual or personal design activity? Let's pool ideas, and not complain about our kids and grandkids. Many of them are smarter than we are. Peter Alfke, from home =================== Rob wrote: > Hobbyists. Now there's a term you don't often hear amongst the next > generation. If the hobbyist is going to make a comeback in this country > (US) it is going to take more than a low-cost, high capability FPGA. With > the watered down public education serving up a non-challenging, push them > through curriculum, what hope is there for technologists in this country > over the next few decades? > > Do you know how many times I've walked into a gas station and encountered a > teen who can't carry through on a simple transaction? The youth today > aren't--for the most part--go getters: they lack direction, motivation, and > personal responsibilty. They are not problem-solvers, they're > problem-makers who go though life thinking that somebody is always going to > wipe their backside. Give them a kit of parts and ask them to make it > work-ha! They might have to read a book! > > It has been reported that high school graduates are increasingly choosing > non-technical fields to major in. The technical fields are too challenging, > require too much work, and interfere with the 50hrs/week of playing video > games. Where are the Heathkitter's of the next generation? > > I've ranted long enough........................... > > > > "Kevin Morris" <kevin@techfocusmedia.com> wrote in message > news:1137096913.255199.239090@o13g2000cwo.googlegroups.com... > > I'm writing a feature article for FPGA Journal (www.fpgajournal.com) > > about FPGAs and the re-birth of the electronics hobbyist. My theory is > > that electronics as a hobby went through a "dark age" period, maybe > > from the early/mid 1970s until recently becuase of the inaccessibility > > and cost of designing with state-of-the-art technology. Radio Shack > > shifted their focus from 50-in-1 project kits and hobbyist parts to > > selling toys, cell-phones, and stereo equipment. > > > > Now, with the emergence of low-cost, high-capability FPGAs, development > > boards, and design software, I see a new age of hobbyist activity > > beginning (as often evidenced in this group). > > > > I'm looking for a few people that would be willing to express views on > > this topic for the article. > > > > I know, Austin will probably post a strong technical argument that > > Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from > > Altera will send me a Cubic Cyclonium prototyping paperweight (they're > > very cool), and Actel and Lattice people will post just to remind us > > that they have low-cost kits too, but I'm primarily interested in some > > info from real, live, "working" hobbyists. > > > > Any takers? > >Article: 94719
Peter: I appreciate your comments. But do you know how many great civilizations have come and gone since Socrates, including his [Socrates] own? I'm an old patriot and my response was mainly driven by my frustration of what I see as a possible future for this great country. I work for a fortune 500 company and I don't see many young Americans coming in for internships. I have also worked with one of our local well-renonowed colleges and I see a majority of students with visas filling the class rooms, not young Americans. Yes, there are many great engineers in this country ,and doubtless there will be many more, but I fear that those numbers will fall. And don't mis-interpret my message: I'm not against anyone coming to this country to get an education. To re-state, I'm just frustrated with our primary education system. My apologies for deviating from the topic--it just hit a nerve. Take care, Rob "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1137467887.797205.284330@o13g2000cwo.googlegroups.com... > Rob, the first adult who is known to have complained about the youth of > his time being lazy do-no-gooders, was Socrates, more than 2400 years > ago. And each generation after him has repeated the complaint, while > benefitting from the progress brought about by those youths, once they > had matured. > Look at the kids coming out of Stanford, starting SUN, Yahoo, and > Google. Most of the detailed work in my company is done by engineers in > their late twenties and thirties, obviously with necessary guidance > from us more experienced folks... > If kids are not interested in science, that is mainly the fault of > educators, industry and management, creating a a bad learning and > career environment. > I prefer the original posting of this thread: > How can FPGAs envigorate individual or personal design activity? > Let's pool ideas, and not complain about our kids and grandkids. > Many of them are smarter than we are. > Peter Alfke, from home > =================== > Rob wrote: >> Hobbyists. Now there's a term you don't often hear amongst the next >> generation. If the hobbyist is going to make a comeback in this country >> (US) it is going to take more than a low-cost, high capability FPGA. >> With >> the watered down public education serving up a non-challenging, push them >> through curriculum, what hope is there for technologists in this country >> over the next few decades? >> >> Do you know how many times I've walked into a gas station and encountered >> a >> teen who can't carry through on a simple transaction? The youth today >> aren't--for the most part--go getters: they lack direction, motivation, >> and >> personal responsibilty. They are not problem-solvers, they're >> problem-makers who go though life thinking that somebody is always going >> to >> wipe their backside. Give them a kit of parts and ask them to make it >> work-ha! They might have to read a book! >> >> It has been reported that high school graduates are increasingly choosing >> non-technical fields to major in. The technical fields are too >> challenging, >> require too much work, and interfere with the 50hrs/week of playing video >> games. Where are the Heathkitter's of the next generation? >> >> I've ranted long enough........................... >> >> >> >> "Kevin Morris" <kevin@techfocusmedia.com> wrote in message >> news:1137096913.255199.239090@o13g2000cwo.googlegroups.com... >> > I'm writing a feature article for FPGA Journal (www.fpgajournal.com) >> > about FPGAs and the re-birth of the electronics hobbyist. My theory is >> > that electronics as a hobby went through a "dark age" period, maybe >> > from the early/mid 1970s until recently becuase of the inaccessibility >> > and cost of designing with state-of-the-art technology. Radio Shack >> > shifted their focus from 50-in-1 project kits and hobbyist parts to >> > selling toys, cell-phones, and stereo equipment. >> > >> > Now, with the emergence of low-cost, high-capability FPGAs, development >> > boards, and design software, I see a new age of hobbyist activity >> > beginning (as often evidenced in this group). >> > >> > I'm looking for a few people that would be willing to express views on >> > this topic for the article. >> > >> > I know, Austin will probably post a strong technical argument that >> > Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from >> > Altera will send me a Cubic Cyclonium prototyping paperweight (they're >> > very cool), and Actel and Lattice people will post just to remind us >> > that they have low-cost kits too, but I'm primarily interested in some >> > info from real, live, "working" hobbyists. >> > >> > Any takers? >> > >Article: 94720
I've had some interesting conversations with Tutors, and one point they make for the lack of inflows, is the 'appliance' nature of much of the electronics. No one enters tertiary education expecting to design a stereo, or TV, plus much of what potential students see is disposable, or close to disposable. Then the Dot-bomb tended to tar all technology companies with the same brush, and the industry is still clawing back from that. That's why I believe such 'early/wide student' demos, need to have at least one block that has a wide audience. ie something they can show their parents, or apply to a club, or sport. GPS-option Stopwatch is one such item : Give them time displays to the low ns, just to remind potential students of the reach of the time-domain. - and make it simple enough for even schools to run as 'canned examples'. -jg Peter Alfke wrote: > Rob, the first adult who is known to have complained about the youth of > his time being lazy do-no-gooders, was Socrates, more than 2400 years > ago. And each generation after him has repeated the complaint, while > benefitting from the progress brought about by those youths, once they > had matured. > Look at the kids coming out of Stanford, starting SUN, Yahoo, and > Google. Most of the detailed work in my company is done by engineers in > their late twenties and thirties, obviously with necessary guidance > from us more experienced folks... > If kids are not interested in science, that is mainly the fault of > educators, industry and management, creating a a bad learning and > career environment. > I prefer the original posting of this thread: > How can FPGAs envigorate individual or personal design activity? > Let's pool ideas, and not complain about our kids and grandkids. > Many of them are smarter than we are. > Peter Alfke, from home > =================== > Rob wrote: > >>Hobbyists. Now there's a term you don't often hear amongst the next >>generation. If the hobbyist is going to make a comeback in this country >>(US) it is going to take more than a low-cost, high capability FPGA. With >>the watered down public education serving up a non-challenging, push them >>through curriculum, what hope is there for technologists in this country >>over the next few decades? >> >>Do you know how many times I've walked into a gas station and encountered a >>teen who can't carry through on a simple transaction? The youth today >>aren't--for the most part--go getters: they lack direction, motivation, and >>personal responsibilty. They are not problem-solvers, they're >>problem-makers who go though life thinking that somebody is always going to >>wipe their backside. Give them a kit of parts and ask them to make it >>work-ha! They might have to read a book! >> >>It has been reported that high school graduates are increasingly choosing >>non-technical fields to major in. The technical fields are too challenging, >>require too much work, and interfere with the 50hrs/week of playing video >>games. Where are the Heathkitter's of the next generation? >> >>I've ranted long enough...........................Article: 94721
Hi I didn't see a long pci cards for a long time (may be some evaluation board still uses long size). You can still use additional riser (as you mention) But, this PCI extender is really good for the mid/low size. I'm using hot swap software from Amfeltec (it comes with PCI Extender) under Linux and it very simple to install/use. Linux: 1. Load the small driver (you can load it on startup). 2. Run utility to read pci configuration and store it into a file. 3. Now, you can switch off PCI Extender and replace your test card. 4. Switch on PCI Extender and update pci configuration using the same utility 5. you ready to go. Under Windows platform, it has almost the same procedure. StevArticle: 94722
Got a project from a consultant using ISE 4.1 but of course the latest download is 8.1. If it matters, target device is XC95144-XL. There is no obvious way to open this older project. Oddly, ISE doesn't seem to create ANY file associations in Windows. I do have all of the original pieces from 4.1, but it's not clear to me which of these are critical input and which are output, log, or intermediate files. Any clues? Thx, DLRArticle: 94723
As I mentioned in another thread, I received a project from a consultant who supplied the design files, in fact everything. I'm thinking there MUST be a way to simply program the device (XC95144XL) from the JEDEC file, but after rummaging around for an hour I could NOT figure this out! Am I missing something besides my brain? Thanks, DLRArticle: 94724
Is there any way to get gate counts for a Quartus implemented design? I know Xilinx will give gate counts out of place and route but I can't seem to figure out anything other than LUT counts and logic element usage from Quartus. Adam
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