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On 4 Aug 2005 13:17:10 -0700, "Brandon" <killerhertz@gmail.com> wrote:
>Actually, this syntax was ok:
>port map (... P => unsigned(S) ...)
>
>While this was not:
>port map (... unsigned(A) => B ...)
ok - both versions should be absolutely fine, assuming
A is an output port of course. Both forms were made
legal in VHDL-93 (in VHDL-87 it would have been necessary
to write your own function, something like "my_unsigned",
so that the conversion is a function call rather than an
array type conversion)
>I don't understand why they haven't fixed this...
Not enough people shouting about it, I guess.
> Is there any sort of
>option to toggle VHDL-93 syntax?
You must have VHDL-93 enabled already, otherwise the input-port
conversion would also have been illegal.
>If you don't mind, could you explain the wrapper workaround? I made the
>changes manually myself, but that involved creating a duplicate signal
>to perform the type conversion on. This is quite sloppy imo, and I
>dislike having to tailor my code to a specific tool.
Well... the code you end up with will work in any tool OK, it's
just that it is tiresome to do. I wasn't suggesting anything
different - just another layer of module instantiation so that
the conversion is not visible in the top-level module:
entity Original is
port (P: in unsigned(...); Q: out std_logic_vector(...));
end;
entity Wrapper is
port (P: in std_logic_vector(...); Q: out unsigned(...));
end;
architecture Hack of Wrapper is
signal QU: unsigned(...);
begin
Original_Instance: entity work.Original(arch)
port map (P => unsigned(P), Q => QU);
Q <= std_logic_vector(QU);
end;
Now, when you instantiate Wrapper in your top-level module,
no type conversion is needed. I'm sure this is exactly
what you have already done - I'm merely suggesting the
wrapper module as a way of localising the type conversion
so that it doesn't pollute the architecture of the
enclosing module.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 88001HI, I have studied ST M24P40 serial flash memory, but i have some confuse some confuse about the HOLD signal. The situation as I want to send Page-program instruction to Flash memory, and followed by its data bit. If my data bit is coming so slow from my front-end module. can i now need to generate the Hold signal to Flash memory until my data-bit is already a multiple of 8? (clk cycle still remain in Hold state) I mean if it can work ? thanks a lot kelvinArticle: 88002
Hi,
does QuartusII version 5.0 SP1 implement
a holding function in output registers ?
If it does not, how can I solve
the following example if I want to place "ls_data_out"
in output registers ?
...
ARCHITECTURE example OF XY IS
BEGIN
Data_out <= ls_data_out;
PROCESS(Rst, Clk)
BEGIN
IF Rst='1' THEN
ls_data_out <= (OTHERS => '0');
ELSIF rising_edge(Clk) THEN
ls_data_out <= ls_data_out; -- If no condition keep the value
IF condition='1' THEN
ls_data_out <= ...;
END IF;
END IF;
END PROCESS;
END example;
Article: 88003
Hi,
does QuartusII version 5.0 SP1 implement
a holding function in output registers ?
If it does not, how can I solve
the following example if I want to place "ls_data_out"
in output registers ?
...
ARCHITECTURE example OF XY IS
BEGIN
Data_out <= ls_data_out;
PROCESS(Rst, Clk)
BEGIN
IF Rst='1' THEN
ls_data_out <= (OTHERS => '0');
ELSIF rising_edge(Clk) THEN
ls_data_out <= ls_data_out; -- If no condition keep the value
IF condition='1' THEN
ls_data_out <= ...;
END IF;
END IF;
END PROCESS;
END example;
Article: 88004"kelvins" <kelvins.huang@gmail.com> schrieb im Newsbeitrag news:1123230769.478488.51380@g47g2000cwa.googlegroups.com... > HI, > I have studied ST M24P40 serial flash memory, but i have some > confuse some confuse about the HOLD signal. The situation as I want to > send Page-program instruction to Flash memory, and followed by its data > bit. If my data bit is coming so slow from my front-end module. can i > now need to generate the Hold signal to Flash memory until my data-bit > is already a multiple of 8? (clk cycle still remain in Hold state) > I mean if it can work ? > > > thanks a lot > > kelvin > Hi Kelvin just think of the 'hold' signal as 'Clock enable' - while in hold it doesnt matter what the other signals do, you can re-use the same pins for different purpose or secondary protocol if you wish, 25P will not change it state and you can proceed with command-data that was interrupted. Antti Spartan-3 On-Chip Oscillator: http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=7536462111Article: 88005
"Marc Randolph" <mrand@my-deja.com> wrote in message news:1123159113.543734.166940@g43g2000cwa.googlegroups.com... > > I think that tight vs. loose coupling discussions come up every year > or so on the SI-list. > Hi Marc, This is lazy I know, but could you post a link to point me at the SI-list so I can hunt down the stuff you mention? I have to say that with the devices and PCB technologies I use, edge-coupled pairs are the only ones that make sense and the coupling between the traces is << than the coupling to the reference plane. This gives you inherent protection against aggressor traces as those traces can only edge-couple too. With broadside-coupled stripline, the traces are much more tightly coupled, but it's hard to make the traces thin enough and the layers far enough apart to get 100 ohms differentially. It also requires vias to traces within the layer stack which provides SI problems of its own. I think that on properly laid out PCBs the diff pairs mostly protect you against power supply noise at the transceivers rather than from aggressor nets. That said, you make a good point, and one I'll bear in mind. Thanks, Syms.Article: 88006
Maybe stick with more std DSP texts that include a decent section on OFDM, but I don't know of one OTOH.Article: 88007
Hello all, I am now trying to code a bough wooley multiplier in verilog. The following link gives good animation and VHDL code for that. http://tima-cmp.imag.fr/~guyot/Cours/Oparithm/english/Multip.htm Is it possible to get a verilog code as simple as the VHDL code shown in the site. i tried to model it but have some doubt. Is it possible to instantiate two dimensional components in verilog. There is options for 1 dimensional instantiations But when i tried for two dimension it gave an error. I tried the following syntax.. FA fa[7:0][6:0](in1[7:0][6:0],out[7:0][6:0]); etc.... but FA fa[7:0](in1[7:0],out[7:0]); worked just fine. Also i felt like books and related topics on this type advanced design is very less. Requesting evry bodies comment on this. regards SumeshArticle: 88008
Symon wrote on 05.08.2005 11:45: > This is lazy I know, but could you post a link to point me at the SI-list so > I can hunt down the stuff you mention? http://www.si-list.org :) cu, SeanArticle: 88009
Ta! "Sean Durkin" <smd@despammed.com> wrote in message news:42f34d3a$1@news.fhg.de... > http://www.si-list.org :) >Article: 88010
ALuPin@web.de wrote: > Hi, > > does QuartusII version 5.0 SP1 implement > a holding function in output registers ? > > If it does not, how can I solve > the following example if I want to place "ls_data_out" > in output registers ? > > ... > ARCHITECTURE example OF XY IS > > BEGIN > > Data_out <= ls_data_out; > > PROCESS(Rst, Clk) > BEGIN > IF Rst='1' THEN > ls_data_out <= (OTHERS => '0'); > > ELSIF rising_edge(Clk) THEN > ls_data_out <= ls_data_out; -- If no condition keep the value > > IF condition='1' THEN > ls_data_out <= ...; > END IF; > END IF; > END PROCESS; > > END example; There's no need for the "if no condition keep the value" assignment. The semantics of the clocked process that creates a flip-flop means that it's redundant. "condition='1'" synthesizes to a clock enable whose effect is to gate the rising edge of the clock. (Of course on an FPGA, the clock enable is really a mux select -- look up "recirculating mux"). -aArticle: 88011
Yup, parallel IV cables on the computers here work refuse to work as Parallel IV , they run as a III... I haven't found a way to fix it either. Ben "Sean Durkin" <smd@despammed.com> wrote in message news:3lfaibF12bb33U1@individual.net... > Hi Austin, > > austin wrote on 04/08/05 21:11: >> 'DONE does not go high' is the #1 complaint we get > What's #2? :) > > For me the biggest complaint is the drivers for the Parallel Cable IV. > The same cable works fine on one PC, but is detected as a Parallel Cable > III on another, no matter what settings you use for the parallel port, > and no matter what kind of board you hook it up to. Most of the time > it's slow as hell, taking a minute or so to program a bigger V2P, which > makes rapid prototyping not so rapid anymore... After spending a few > days trying out different cables with different PCs and all ISE-releases > and Service Packs I could get a hand on, and doing a *LOT* of research, > I found that the problem is definitely that Jungo > windriver-parallel-port-thingie you ship with ISE. On their website it > just says that with "some parallel port chips" it simply doesn't work > well, mostly "Intel based chips" (and these are so rare to come by these > days...), and that's that... > > We're starting to switch to USB platform cables, but there's still a > whole bunch of parallel cables in use which would be okay if only that > driver worked on more machines... > > cu, > SeanArticle: 88012
Austin, I will take you up on that offer and send you schematics. That is great customer service. The problem seems to be more intermittent than what I just described. Maybe I only need a pullup somewhere. The board is six layer and well capped. It should be relatively quiet. Thank you. BradArticle: 88013
> In a way yes and it's safe to do. You don't register the reset signal > though. Assume you have an active low reset. You connect input of a > flop to 1 and connect its async reset input to the reset io pin, a > second flop takes the output of the first as input and it's also async > reset by the io pin. These are clock by your local clock (of course > you have to make sure that for every clock domain in your design, you > repeat this process). OK. Are you doing this with Unisim components? Or can the XST infer all this through VHDL? And then does the synched reset from the second flop then connect to some global reset? And then how do you check that the synthesizer is correctly inferring to use the synched reset signal? BradArticle: 88014
has anyone had a chance to work with any of the new v4 dev boards? I am looking for one with PCI (or pci express) support, and some good (clear) reference designs drivers would be helpful as well... thanks -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 88015
"Brad Smallridge" wrote:
>> In a way yes and it's safe to do. You don't register the reset signal
>> though. Assume you have an active low reset. You connect input of a
>> flop to 1 and connect its async reset input to the reset io pin, a
>> second flop takes the output of the first as input and it's also async
>> reset by the io pin. These are clock by your local clock (of course
>> you have to make sure that for every clock domain in your design, you
>> repeat this process).
>
>OK. Are you doing this with Unisim components? Or can the
>XST infer all this through VHDL? And then does the synched
>reset from the second flop then connect to some global reset?
Try something like this:
Process(clk,resetin)
begin
if resetin = '1' then
reset1 <= '1';
reset2 <= '1';
elsif rising_edge(clk)
reset1 <= not dll_lock;
reset2 <= reset1;
end if;
end process;
-- one of many processes
Rest_of_logic: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
-- set reset conditions where needed
else
-- normal operation
end if;
end if;
end process;
Output_needing_forced_off_during_reset: process(regular_oe, reset, d)
begin
if regular_oe = '0' or reset = '1' then
OUTPIN <= 'Z';
else
OUTPIN <= d;
end if;
end process;
>And then how do you check that the synthesizer is correctly
>inferring to use the synched reset signal?
FPGA_editor.
--
Phil Hays
Phil-hays at comcast.moc (remove moc and add net) should work for
email
Article: 88016Hello Paul and Ben, In Quartus II 4.2 you will need a license for your encrypted core so that you can compile it successfully with Incremental Compilation. This restriction will be removed in Quartus II 6.0. Alternatively in Quartus II 5.0 if you do not have a license one can use Incremental Compilation and set all PARTITION_SOURCE settings to POST_SYNTHESIS for the core. Hope this helps, Subroto Datta Altera Corp. Ben Twijnstra wrote: > Hi Paul, > > > I am currently using the evaluation open-core FIR compiler and NCO > > compiler in the design and when I use these I am not able to perform > > incremental synthesis. Does anyone know if you can perform incremental > > synthesis with these cores once the cores are licensed? as synthesis steps > > are taking upwards of 20-30 minutes at the moment and it is becoming quite > > painful not having incremental systhesis. > > You _should_ be OK with the licensed cores as well. The only difference > between the licensed and the unlicensed version is the Big Counter that > will shut the core down after an hour. > > Better yet, in Quartus II 5.0 (out since June - why are you still on 4.2?) > you should also be able to do incremental P&R of your design. > > This last bit may or may not cost you a bit of performance as the design > optimization is hindered by the fitting boundaries, but it should save you > loads of time between iterations. > > Best regards, > > > > BenArticle: 88017
Actually I did use functions to perform the conversion. For some reason it only complained when the function call was on the left hand side of the port map. Thanks for the help.Article: 88018
When the Virtex-4 XC4VFX140 with 24 RocketIOs is expected to be available, for normal customers ? -- Tullio Grassi ====================================== Univ. of Maryland-Dept. of Physics | College Park, MD 20742 - US | Tel +1 301 405 5970 | Fax +1 301 699 9195 | ======================================Article: 88019
I sucess fully created a two dimensional structure for unsigned multiplier, using multiple "one dimensional instantiations". it synthesized correctly but simulator gave error values. All code seems ok i also verified it in the output of the synthesizer but in simulator its not working. What is the standard procedure to describe a circuit which is repeatation of small units(like the multiplier). I think we can use the "for" loop for that (i used the same in my design). But it can be included only in the always blocks ?? is there any other way for that? IS there any other way in which we can simply specify the connections as is done in schematic editor ?? regards sumeshArticle: 88020
Tulio, I would suggest that you contact your Xilinx FAE, but I see that you are a university or school, so I suggest you contact your university support person here at Xilinx. http://www.xilinx.com/univ/ Get a login, and then request product pricing and availability. AustinArticle: 88021
Arrays of instances can only be 1-dimensional in Verilog. You can always map a multi-dimensional array into a 1-dimensional array anyway. Alternately, you could instantiate an array of instances, each of which handles an entire row by instantiating an array of instances to handle the individual elements. Verilog-1995 only supported 1-dimensional arrays of data words also. Multi-dimensional arrays were only added in Verilog-2001. Multi-dimensional arrays of instances were probably not added because attention was focused on adding the more general generate constructs to do the same kind of things, rather than extending arrays of instances.Article: 88022
Hello Everyone Thanks Eric for the suggestions.Since you have been working in the area of evolutionary algorithms, can you suggest where I could find some examples of code that use evolutionary algorithms for electronic or logic circuit.This would give me an idea to start with my own code.I haven't actually seen an evolutionary algorithm being implemented in a code.So I have absolutely no idea how it looks like.Its like learning programming for the first time.You need to look at some programs to get started with your own code. Ankit Eric wrote: > Evolutionary Algorithms do have their place. > > During my Masters program a friend and I wrote a piece of software that > would take a logic circuit and generate a set of test vectors that > would give you the best fault coverage. > > The program did this using a "Genetic Algorithm" approach. > First a random set of test vectors were created. Then the set of > vectors were repopulated based on a fitness function. (Basically if the > test vector had a high % of fault coverage it was more likely to be > selected back in the set of vectors) After that there is a > mutation/cross over phase which adds more variants to the population. > These 3 steps are repeated until a certain % of fault coverage is > completed by a set of the vectors. > > The upside to this approach is it can be a lot faster than an > exhaustive approach, especially if the circuit is large. The downside > is every time you run the program you get a different answer. The > whole value of this and other evolutionary methods are how good is the > fitness function. > > I'm not sure how you would use evolutionary methods in an FPGA. > Unless you wanted a hardware version of what my program does... create > a set of test vectors to test your ASIC every time it boots up. But I > probably need to read Adrian's paper aswell. > > It is an interesting topic even if it might only academic merit at the > present. > > Here are the references for the paper I wrote on this program. > > 1) Rudnick, E. , "Application of Simple Genetic Algorithms to > Sequential Circuit Test > Generation", Center for Reliable and High-Performance Computing, > University of > Illinois, Urbana, Il 61801 > 2) Rudnick, E., "Sequential Circuit Test Generation in a Genetic > Algorithm Framework", > Center for Reliable and High-Performance Computing, University of > > Illinois, Urbana, Il 61801 > 3) Corno, F., "A Parallel Genetic Algorithm for Automatic Generation > of Test Sequences > for Digital Circuits", Dip. Automatica e Informatica - > Politecnico di Torino, Torino > Italy > 4) Prinetto, P., "An Automatic Test Pattern Generator for Large > Sequential Circuits > based on Genetic Algorithms", Dip. Automatica e Informatica - > Politecnico di Torino, > Torino Italy > > Eric HollandArticle: 88023
Genetic Algorithm pseudo code:
Problem: Solve 2x+1 = 7 (we know the answer is 3, but work with me)
Step #1 Generate a Random population of numbers:
Population = 1, 6, 8, 4
Step #2 Chose a fitness function. Ours will be Error = ABS(1-(2x +
1)/7)
Error(1) = ABS(1-(2x1+1/7)) = 0.57
Error(6) = ABS(1-(2x6+1/7)) = 0.86
Error(8) = ABS(1-(2x8+1/7)) = 1.43
Error(4) = ABS(1-(2x4+1/7)) = 0.29
The number with the smallest Error is closest to the answer. (Still
with me?)
Step #3 Repopulate your population based on your fitness function
results. This is the tough part to grasp. We need to normalize all of
the errors so we can get a repopulation percentage. This will help us
get the new population of numbers.
Take the total of the error 0.57 + 0.86 + 1.43 + 0.29 = 3.15
3.15/0.57 = 5.53
3.15/0.86 = 3.66
3.15/1.43 = 2.20
3.15/0.29 = 10.86
Take the total of the normalized error = 5.53 + 3.66 + 2.20 + 10.86
=22.25
Repopulation percentage for 1 = 5.53/22.25 = 25%
Repopulation percentage for 6 = 3.66/22.25 = 16%
Repopulation percentage for 8 = 2.20/22.25 = 10%
Repopulation percentage for 4 = 10.86/22.25 = 49 %
So now you repopulation your population, this means if you were
generating a random number from 0-100,
if the number was 0-24 the answer would be 1.
if the number was 25-41(25+16) the answer would be 6
if the number was 42-52(42+10) the answer would be 8
if the number was 53-100 the answer would be 4
So you can see the smaller the Error the greater chance the new
population will include that number
New Repopulation = 4, 4, 4, 1
So if you kept on repeating step 2 eventually you would have a
population of all 4's, but 4 is not the answer. So how do we get the
answer in our population if we don't have 3 in the initial
population?
The answer is step #4.
Step #4 mutation / crossover. In this example we'll just do mutation.
Just generate a random number and replace it in the population.
New population after mutation 4, 4, 4, 9
Step #5 repeat steps 2 - 4 until total Error is acceptable. In this
case until you get an Error of 0.
Kind of make sense???
I can give you sample code but it won't make sense unless you
understand the concept of evolutionary codes.
Eric
Article: 88024
Thanks for the suggestion. I am experimenting with the generate key
word.
But while doing that some problem observed. the following code gave
error.
"index out of range".
for(i = 0; i<= 7;i=i+1)
begin
assign A[i] = (i!=0)?B[i]&C[i-1]:1;
end
because of this error i am forced to split the loop. Is there any way
to do this in a single loop???
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Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z