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On Jan 18, 8:02=A0pm, "Marty Ryba" <martin.ryba.nos...@verizon.net> wrote: > "Peter Alfke" <pe...@xilinx.com> wrote in message > > news:76bcd2dd-330e-47c8-9813-00fea9a4d6d1@v67g2000hse.googlegroups.com... > > > Decades ago, the major TV stations kept the color subcarrier very > > accurate (much better than 0.01 ppm), but that service has ben > > abandoned. WWV needs a short-wave receiver, or at least a good > > selective amplifier. > > I am asking this smart group for some creative ideas. GPS ? > > I indicate the frequency on a 9-digit display, so it would be > > desirable to be able to guarantee better than 1 ppm (after calibration > > for at least a few days. Temperature drift is not a big issue in a lab > > instrument...) > > Other posters have mentioned the excellent GPS-based solutions available, > and/or WWV(B) options. Here are two others: > 1) The TV carriers are still often dead-on in frequency, as they are now > locked to GPS. > 2) The Loran-C system (100 kHz pulses) is being recapitalized with precise= > (GPS-locked) references as a backup to GPS against potential jamming. > > I've been very happy with my Symmetricom frequency references; for a > small/cheap solution, SigNav is now selling a GPS receiver based on the ol= d > Motorola Oncore series (interface compatible) that provides a precise 10MH= z > output. Trimble also sells something called the Micro-T with similar > capability. Both I believe are in the ~$200 range for an OEM, but prices > have been dropping. When locked to GPS, these jobbies can give you better > than 10 ppb accuracy. > > Marty Thank you, guys, for all the advice arriving in just a few hours. I remember Droitwitch 200 kHz from my parents' (highly illegal) listening to the BBC during WW2. It covered most of Germany (!) very well, but is obviously silent here in the US. The 60 kHz timing transmissions in Europe and here from Fort Collins, Colorado are rather slow, and burdened with their data modulation. I like the GPS-based solutions from SigNav and Trimble best. I have no intentions of burdening the box with a >>$10 precision oscillator, I rather provide a separate calibration capability, for manufacturing and for ultra-demanding users, where a few hundred dollars do not matter. The nicest solution would be over the internet, but I have not heard about anything like that (yet). I will keep you informed about our progress. Peter AlfkeArticle: 128251
In article <478fd923$0$25480$ba620dc5@text.nova.planet.nl>, burrynulnulfour@ppllaanneett.nnlll says... > linnix wrote: > > On Jan 17, 12:03 am, recoder <kurtulmeh...@gmail.com> wrote: > >> Dear All, > >> As an assignment I have to design a CCD Sensor based FPGA digital > >> Camera. However, the Camera will be exposed to XRAY (It will be placed > >> behind an Imaging Intensifier). Does anybody know how XRAY affects the > >> electronic circuits (The CCD Sensor and the FPGA ). What type of noise > >> should I expect and what should I do to prevent it. > >> Thanks in advance > > > > Is it internal flash or external flash? If anything, flash would be > > the weakest link. > I would think an old fashioned tube camera with tube amplifiers > would be the most radiation resistant. > Vidicon tubes! I haven't seen one of those in a whole lot of years but I'm so happy everythign is CCD now.Article: 128252
On Jan 18, 4:49 pm, Peter Alfke <pe...@xilinx.com> wrote: > This is slightly off-topic: > I have mentioned before that I am in the process of designing (and > manufacturing in limited volume) a clock-generator box (1 Hz to 1.5 > GHz in 1 Hz increments). We debated some jitter issues... > It's tough to get a very accurate reference xtal (2 ppm should be > possible, 20 ppm is easy) > I might include a simple calibration mechanism (any reasonable amount > of logic is free in the Virtex-5 FPGA), but from where do I get a very > accurate reference frequency input of any value ? > > Decades ago, the major TV stations kept the color subcarrier very > accurate (much better than 0.01 ppm), but that service has ben > abandoned. WWV needs a short-wave receiver, or at least a good > selective amplifier. > I am asking this smart group for some creative ideas. GPS ? > I indicate the frequency on a 9-digit display, so it would be > desirable to be able to guarantee better than 1 ppm (after calibration > for at least a few days. Temperature drift is not a big issue in a lab > instrument...) > Peter Alfke Here is one more interesting link: http://www.leapsecond.com/ Regards, John McCaskill www.FasterTechnology.comArticle: 128253
>Here is one more interesting link: >http://www.leapsecond.com/ Beware. That's much more than just an "interesting link". It's a gigantic time sink. :) -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128254
In article <76bcd2dd-330e-47c8-9813-00fea9a4d6d1@v67g2000hse.googlegroups.com>,
Peter Alfke <peter@xilinx.com> writes:
>This is slightly off-topic:
>I have mentioned before that I am in the process of designing (and
>manufacturing in limited volume) a clock-generator box (1 Hz to 1.5
>GHz in 1 Hz increments). We debated some jitter issues...
>It's tough to get a very accurate reference xtal (2 ppm should be
>possible, 20 ppm is easy)
>I might include a simple calibration mechanism (any reasonable amount
>of logic is free in the Virtex-5 FPGA), but from where do I get a very
>accurate reference frequency input of any value ?
My two cents worth...
I assume your target market is pretty broad, some combination
of professionals/geeks with serious cash, hackers with time but no cach,
and professors/students and whatever in between.
A connector for an external clock is the obvious first step.
That lets you use whatever is available at the local environment.
Serious labs will have 10 MHz available from the wall next to the
110 V AC and ethernet.
Lots of lab equipment (for example counters) have a BNC jack
on the back for input of a reference clock andor output of
their internal oscillator. That sort of lab gear has good to
very good internal oscillators.
That's all pretty fancy/expensive. But it lets the geeks go
for the bleeding edge.
Most low cost digital crystal oscillator packages have 2
interesting error components. One is manufacturering offset.
The other is temperature. (Supply voltage is probably third,
but I'm not calibrated on that.)
The ballpark for tempertaure is 1 ppm per C. The ballpark for
manufacturing (at room temp) is 1/2 of the spec.
I'd expect you could get pretty close to a few ppm if you did
a calibration run at a known temperature on your final checkout
line and recorded the fudge factor.
You could do even better if you included a temperature sensor
near the local oscillator package and made a few test runs to get
a simple linear correction. (Maybe non-linear via table lookup
would be better. Mumble, TBD.)
I don't think you will get much from WWVB or WWV and friends
without a stable local clock to use as a refernce. They are
great for the long term, but you need a place to stand.
As others have suggested, ask Austin for high end ideas.
DDS type approaches are notorious for close-in spurs.
I think they are not interesting for longer term measurements.
(But lots of people are interestedin short term measurements.)
GPS is a good (low cost) straw man.
You can get GPS receivers with a PPS (pulse per second) output
for under $100. They are basically low cost commerical units
with an extra output pin.
You can get various boxes with a good crystal, a GPS input,
a pile of software, and ... They tend to be expensive
on the hobbyist scale.
An example:
http://jackson-labs.com/products_fury.html
Symmetricom (by way of Agilent) has Borged HP's old Cesium
clock business area and friends and lots of others.
http://www.symmetricom.com/Products
(I didn't run into their Flash crap until I got there.)
GPSDO is a good magic word: GPS Disciplined Oscillator.
GPS provides the long term stability. The local (good
crystal) provides the short and medium stability. Usually
there is a lot of software filtering involved.
HP pioneered that technology many years ago.
For more than you wanted to know:
http://www.hpl.hp.com/hpjournal/96dec/dec96a9.pdf
The Global Positioning System and HP SmartClock
December 1996 Hewlett-Packard Journal
http://www.realhamradio.com/GPS_Frequency_Standard.htm
(Z3801As were available cheap for a while as cell towers upgraded.)
HP app notes:
HP SmartClock Technology Application Note 1279
The Science of Timekeeping Application Note 1289
GPS and Precision Timing Applications Application Note 1272
(Ask me if google can't find them for you.)
Just for fun, and this needs a serious time-sink warning,
here is my all time favorite paper about time:
http://www.physicstoday.org/vol-59/iss-3/p10.html
Daniel Kleppner
Physics Today, March 2006, page 10
[Don't say I didn't warn you.]
--
These are my opinions, not necessarily my employer's. I hate spam.
Article: 128255"Peter Alfke" <peter@xilinx.com> wrote in message news:76bcd2dd-330e-47c8-9813-00fea9a4d6d1@v67g2000hse.googlegroups.com... > I am asking this smart group for some creative ideas. GPS ? > I indicate the frequency on a 9-digit display, so it would be > desirable to be able to guarantee better than 1 ppm (after calibration > for at least a few days. Temperature drift is not a big issue in a lab > instrument...) > Peter Alfke Hi Peter, I don't claim to be smart or creative, but some TCXOs are good for 1ppm and not too expensive. If you can calibrate them after manufacture, which I guess you can easily do with your small batch, and store the offset error in your device, I bet you can easily keep a TCXO at the same frequency to a few 100ppb, if you don't change the temperature too much. I guess you could even use a IC thermometer (Maxim make some cheap'n'cheerful ones, maybe with nvrom to store offsets?) and adjust the cal accordingly. My experience with TCXOs is just that; the initial accuracy is somewhere within the spec., say +/-2ppm, but the frequency stays at that initial frequency from then on (> a few days!). (A whack with a hammer can sometimes 'adjust' the initial frequency!) Of course, OCXOs are good for a few ppb. http://foxonline.com/pdfs/fts301ah.pdf GPS is great, if you're outdoors. How many lab instruments meet this requirement? ;-) Cabling an aerial can be a PITA. HTH., Syms.Article: 128256
Actually, forget all that, use this:- http://www.nist.gov/public_affairs/releases/miniclock.htmArticle: 128257
comp.arch.fpga <ksulimma@googlemail.com> wrote: > On 18 Jan., 23:49, Peter Alfke <pe...@xilinx.com> wrote: > > This is slightly off-topic: > > I have mentioned before that I am in the process of designing (and > > manufacturing in limited volume) a clock-generator box (1 Hz to 1.5 > > GHz in 1 Hz increments). We debated some jitter issues... > > It's tough to get a very accurate reference xtal (2 ppm should be > > possible, 20 ppm is easy) > Peter, > for our time to digital converters we use temperature compensated > oscillators (TCXOs) with 1 ppm. > We pay a premium because we have custom frequencies cut for us, but > for standard frequencies > in higher quantities the price should be below 10$. > These devices are available from many manucatures in 7mm x 5mm SMD. > I recently saw a new TCXO that only has 100ppb temperature drift. > Below that you need OCXOs. The packages of these are a bit larger, > they are more expensive > and draw quite a lot of current (500mW to 5W). But you can get them > down to 5ppb. While the OCXO have drifts down to 20 ppb, the default accurracy is only in the ppm range... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128258
On Fri, 18 Jan 2008 16:22:59 -0000, "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >Pah, I'll beat that for elegance and simplicity.... > > >process(clk,rst) >begin > one_bit_fifo <= '0'; >elsif(rising_edge(clk)) then > if(load_fifo = '1') then > one_bit_fifo <= one_bit_fifo_input; > end if; >end if; >end process; > >fifo_output <= one_bit_fifo; Where are the empty and full flags? - BrianArticle: 128259
Peter Alfke wrote:
> I might include a simple calibration mechanism (any reasonable amount
> of logic is free in the Virtex-5 FPGA), but from where do I get a very
> accurate reference frequency input of any value ?
IMHO you should simply provide an external clock input
(perhaps of any configurable value, you have some spare
cells in your FPGA...) and let the user supply his own
reference clock. Which could be, for instance, a rubidium
atomic oscillator:
http://cgi.ebay.com/RUBIDIUM-SYMMETRICOM-EFRATOM-LPRO-101-10Mhz-Oscillator_W0QQitemZ300191164028QQihZ020QQcategoryZ25399QQssPageNameZWDVWQQrdZ1QQcmdZViewItem
for 260 USD (dollar is cheap now...). AFAIK there
are smaller models on the market.
Best regards
Piotr Wyderski
Article: 128260On Jan 19, 3:02 am, Ben Jackson <b...@ben.com> wrote: > On 2008-01-18, winsc...@googlemail.com <winsc...@googlemail.com> wrote: > > > > > Does anyone know how to create them in one slice? > > It might happen automatically when your design gets larger and packing > is needed for space. I tried it, but even if I use so many SRLs that packing two of them into one LUT would be required in order to fit into the fpga and set the optimization goal in XST to "area", it doesn't work. winscattArticle: 128261
>While the OCXO have drifts down to 20 ppb, the default accurracy is only in >the ppm range... But many/most of them that are that stable have a voltage adjust input pin. A good regulator and a pot lets you manually adjust it. A DAC lets you servo it to something else, for example GPS. That's a good first step down a very long steep slippery slope. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128262
It Depends!! Yes the SVA constructs are a standard just like the SVD constructs. But that does not mean the tools fully understand the SystemVerilog language. Your tool vendor should have a list that breaks down thier SystemVerilog support by LRM section. I know that the tools I work with are only partially literate in System Verilog. Some of the tools don't support the entire SVD constructs yet, let alone the SVA constructs. Even if this means just to ignore them as unsynthesizable. "aka" <aka@nospam.net> wrote in message news:PdYjj.1832$Rg1.849@nlpi068.nbdc.sbc.com... >I tried synthesizing a Systemverilog-RTL file in Quartus-II 7.2sp1. > The synthesis-engine doesn't seem to understand SVA (systemverilog > assertion) > syntax. > > property prop_x; > @ ( posedge clk ) // disable iff (rstn) > (!$stable( comb_sm )) |-> ##1 (comb_sm !== BADSTATE); > endproperty : prop_x > > ap_x: assert property( prop_x ); > > For now, I've simply put some `ifdef/`endif blocks around the SVA, > to conditionally remove it from Quartus-II compile. > > Now, I assumed SVA was standardized along with the rest of Systemverilog, > and synthesis-tools are supposed to ignore the SVA-constructs -- i.e. > ugly `ifdef should not be needed. > > Is this understanding correct? > For example, does Synopsys Design Compiler and Cadence RTL Compiler > require `ifdef blocks around SVA? >Article: 128263
Peter Alfke wrote: <snip> > I have no intentions of burdening the box with a >>$10 precision > oscillator, I rather provide a separate calibration capability, for > manufacturing and for ultra-demanding users, where a few hundred > dollars do not matter. <snip> How about a 2ppm accuracy reference for $2.55 as a first step? The DS3231 is one of several 32.768kHz Maxim oscillator modules. http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4627Article: 128264
Not a problem. If the Synopsis library exists, I sould have no problem either using it directly with Cadence Encounter RTL Compiler or getting a Cadence contact to convert it. "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:fmp04i$j0b3@cnn.xsj.xilinx.com... > Dwayne Dilbeck wrote: >> That is good to hear. I tend to be pestimistic about getting things for >> free. When NuHorizons finally ships my Spartan 3e kit to me I will look >> for the files. >> >> I will see how well RC can handle the mapping. I will probably have to >> file some bugs with Cadence. >> > > I think by RC you mean the Cadence Encounter RTL Compiler. If this is > correct > then I do not know of any libraries that were ever developed for this tool > for > FPGA synthesis. My previous comments were with respect to the Synopsys > Design > Compiler (DC) tool. > > I did check the Synopsys DC libraries and there is one for Spartan-3E, but > there > isn't anything for the newer Spartan-3A families. At one time (early > 1990s) there > was a very active set of Synopsys DC users and it had good FPGA support, > but now > the focus is on Synplicity Synplify, Mentor Precision RTL and vendor owned > tools. > Ed McGettigan > -- > Xilinx Inc.Article: 128265
winscatt@googlemail.com wrote: > Hello, > > I have a design where I need a couple of 16-bit shift registers, two > bits wide. According to the "Virtex-5 FPGA User Guide", it should be > possible to implement one of these in just one LUT6 in a SLICEM (as > long as one doesn't need the extra flip-flop in that slice). XST does > recognise them as 16-bit shift registers, but always uses two LUTs for > them, instantiating two SRLC32Es. > > Does anyone know how to create them in one slice? > > Thanks, > winscatt Isn't the SRL16x2 a macro? Two SRLC32Es may pack the way you expect in your V5 if they're properly constrained *and* have the same controls. Are you familiar with RPMs? While I usually include my critical RPMs in the .ucf file there are ways to introduce them into the code itself, particularly if you're using VHDL. How many of these SRL pairs do you have? Can you implement each pair with its own level of hierarchy? Are you using XST with Verilog or VHDL? - John_HArticle: 128266
Peter Alfke wrote: > This is slightly off-topic: > I have mentioned before that I am in the process of designing (and > manufacturing in limited volume) a clock-generator box (1 Hz to 1.5 > GHz in 1 Hz increments). We debated some jitter issues... > It's tough to get a very accurate reference xtal (2 ppm should be > possible, 20 ppm is easy) > I might include a simple calibration mechanism (any reasonable amount > of logic is free in the Virtex-5 FPGA), but from where do I get a very > accurate reference frequency input of any value ? > > Decades ago, the major TV stations kept the color subcarrier very > accurate (much better than 0.01 ppm), but that service has ben > abandoned. WWV needs a short-wave receiver, or at least a good > selective amplifier. > I am asking this smart group for some creative ideas. GPS ? > I indicate the frequency on a 9-digit display, so it would be > desirable to be able to guarantee better than 1 ppm (after calibration > for at least a few days. Temperature drift is not a big issue in a lab > instrument...) Hi Peter, The Carrier precisions vary around the world, so I'd allow a flexible calibration scheme. If you implement a reciprocal counter, then users can choose what they like, as reciprocal counters give appx constant precision-per-second Most globaly common these days, is the 1pps on GPS, which gives appx 100ns, or one part in 10^7 per pulse, so you'd need 1000 pulses to get 10^10 A tougher question is how does the user correct the result?. If you use just a vanilla crystal/module, they are not easy to trim. A VCXO would allow a lock system with a simple DAC. Even nicer would be a dual-input system, (would need Dual reciprocal counters, but hey, this is a big FPGA! ) so a user could ratio-lock/check almost any two reference sources (as well as the local crystal). 9 Digits sounds ok for a per-second readout, but users might want to run to 100s or 1000s timebases, for highest precision, and 9 digits is light then :) Or, you could look for one of these!! :) http://www.eurekalert.org/pub_releases/2003-09/oonr-oon090203.php "The Ultra-miniature Rubidium (Rb) Atomic Clock, 40 cubic centimeters in volume and using a minuscule one watt of power, doesn't weigh much more than a matchbox either. And... it will lose only about one second every 10,000 years." -jgArticle: 128267
Hi
I am very new to VHDL and in partuclar ModelSim, so of course I have a
simple starting exercise to learn from.
I want to simulate this RAM model: (thankyou John Aynsley from Doulos)
using the testbench that I have pasted under this model. Everything
works fine until I assert the OE signal, i.e. OE <= '1', '0' after 55
ns;
At this point I would expect to data signal to read what I originally
wrote into "0000". But what is happening is that the wave turns red,
and the 8 bit signal is a mixture of what I expect and x's. i.e.
0X010X0X,.
What am I doing wrong? I don't think it has anything to do with the
model.
Regards
Buce
********************************************************************************************************************************
-- Simple RAM Model
--
-- +-----------------------------+
-- | Copyright 1997 DOULOS |
-- | Library: Memory |
-- | designer : John Aynsley |
-- +-----------------------------+
-- Architectures:
-- 03.02.97 Behaviour
library IEEE;
library vfp;
use IEEE.std_logic_1164.all;
use vfp.generic_conversions.all;
entity RamChip is
port (Address: in Std_logic_vector(3 downto 0);
Data: inout Std_logic_vector(7 downto 0);
CS, WE, OE: in Std_logic);
end;
architecture Behaviour of RamChip is
begin
process(Address, CS, WE, OE)
subtype Byte is Std_logic_vector(7 downto 0);
type Mem is array (0 to 15) of Byte;
variable Memory: Mem := (others => Byte'(others=>'U'));
begin
Data <= (others => 'Z');
if CS = '0' then
if OE = '0' then -- Read operation
Data <= Memory(To_Integer(Address));
elsif WE = '0' then -- Write operation
Memory(To_Integer(Address)) := Data;
end if;
end if;
end process;
end;
********************************************************************************************************************************
-- Test bench for simple RAM model
library ieee;
library parts_lib;
use parts_lib.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TEST_RAM is
end;
architecture BENCH of TEST_RAM is
component RamChip
port(address: in std_logic_vector(3 downto 0);
data: inout std_logic_vector(7 downto 0);
CS, WE, OE: in std_logic);
end component;
signal address: std_logic_vector(3 downto 0);
signal data: std_logic_vector(7 downto 0);
signal CS, WE, OE: std_logic;
begin
address <= "0000", "0001" after 15 ns, "0000" after 45 ns;
CS <= '1', '0' after 3 ns;
WE <= '1', '0' after 5 ns, '1' after 15 ns, '0' after 20 ns,
'1' after 40 ns;
OE <= '1', '0' after 55 ns;
data <= "00010000", "01010101" after 15 ns;
ram: RamChip port map(address, data, CS, WE, OE);
end BENCH;
Article: 128268On Jan 19, 2:25=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > Peter Alfke wrote: > > This is slightly off-topic: > > I have mentioned before that I am in the process of designing (and > > manufacturing in limited volume) a clock-generator box (1 Hz to 1.5 > > GHz in 1 Hz increments). We debated some jitter issues... > > It's tough to get a very accurate reference xtal (2 ppm should be > > possible, 20 ppm is easy) > > I might include a simple calibration mechanism (any reasonable amount > > of logic is free in the Virtex-5 FPGA), but from where do I get a very > > accurate reference frequency input of any value ? > > > Decades ago, the major TV stations kept the color subcarrier very > > accurate (much better than 0.01 ppm), but that service has ben > > abandoned. WWV needs a short-wave receiver, or at least a good > > selective amplifier. > > I am asking this smart group for some creative ideas. GPS ? > > I indicate the frequency on a 9-digit display, so it would be > > desirable to be able to guarantee better than 1 ppm (after calibration > > for at least a few days. Temperature drift is not a big issue in a lab > > instrument...) > > Hi Peter, > The Carrier precisions vary around the world, so I'd allow a flexible > calibration > scheme. > > If you implement a reciprocal counter, then users can choose what they > like, > as reciprocal counters give appx constant precision-per-second > > Most globaly common these days, is the 1pps on GPS, which gives appx > 100ns, > or one part in 10^7 per pulse, so you'd need =A01000 pulses to get 10^10 > > A tougher question is how does the user correct the result?. If you > use just a > vanilla crystal/module, they are not easy to trim. A VCXO would allow > a lock system > with a simple DAC. > > Even nicer would be a dual-input system, (would need Dual reciprocal > counters, but > hey, this is a big FPGA! ) so a user could ratio-lock/check almost any > two > reference sources (as well as the local crystal). > > 9 Digits sounds ok for a per-second readout, but users might want to > run to 100s > or 1000s timebases, for highest precision, and 9 digits is light > then :) > > Or, you could look for one of these!! :) > > http://www.eurekalert.org/pub_releases/2003-09/oonr-oon090203.php > "The Ultra-miniature Rubidium (Rb) Atomic Clock, 40 cubic centimeters > in volume and using a minuscule one watt of power, doesn't weigh much > more than a matchbox either. And... it will lose only about one second > every 10,000 years." > > -jg I really appreciate all the inputs. Here is where I stand today. We have not yet finished the prototype (got delayed by OLED interface issues, and also explored more creative ways to reduce jitter and wander), but that's now behind us. We generate 2 output channels (since it is almost for free) and have a dual-16 character (really: 128 x 64 pixel) display. We will use a 312.5 MHz xtal oscillator that promises single-digit ppm accuracy. For the first dozen prototypes I will ignore the accuracy question, since the average user seems to be content with 20 ppm. But we do not want to remain "average"... We will provide for a calibration input, and also for the non-volatile storage of calibration factors (We already store hundreds of frequencies for recall, again because it is almost for free). Calibration will be by arithmetic number crunching, nothing analog here. We don't change the internal clock frequency, we just change the DDS/PLL interpretation. For the later calibration strategy, we use the fact that we can adjust our signal output to any frequency with 1 Hz granularity. So we can match any comparison frequency "anywhere in the world". We need a Virtex-5 LXT50 chip, due to the way we (ab)use the GTPs, but that gives us an enormous amount of spare logic, RAMs and multipliers. There is also a chip thermometer with digital read-out on every Virtex-5 die. It really is an embarrassment of riches. And we can fine- tune the design as often as we have time and patience. Aren't FPGAs fun ! Thanks again. I have a few things to read and study. Peter AlfkeArticle: 128269
"Bucephalus" <davidsullivan1974@gmail.com> wrote in message news:cdbbf015-c61f-49cc-9347-89c4dd36633a@i3g2000hsf.googlegroups.com... > Hi > At this point I would expect to data signal to read what I originally > wrote into "0000". But what is happening is that the wave turns red, > and the 8 bit signal is a mixture of what I expect and x's. i.e. > 0X010X0X,. > > What am I doing wrong? I don't think it has anything to do with the > model. <snip> Your testbench is also driving the signal data at the same time that 'RamChip' is. At the time when you assert 'OE' into the RAM, you also need to drive 'data' to all 'Z'. Something like the following... > OE <= '1', '0' after 55 ns; > data <= "00010000", "01010101" after 15 ns, "ZZZZZZZZ" after 55 ns; > ram: RamChip port map(address, data, CS, WE, OE); > Kevin JenningsArticle: 128270
On Jan 19, 3:31 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Bucephalus" <davidsullivan1...@gmail.com> wrote in message > > news:cdbbf015-c61f-49cc-9347-89c4dd36633a@i3g2000hsf.googlegroups.com...> Hi > > At this point I would expect to data signal to read what I originally > > wrote into "0000". But what is happening is that the wave turns red, > > and the 8 bit signal is a mixture of what I expect and x's. i.e. > > 0X010X0X,. > > > What am I doing wrong? I don't think it has anything to do with the > > model. > > <snip> > > Your testbench is also driving the signal data at the same time that > 'RamChip' is. At the time when you assert 'OE' into the RAM, you also need > to drive 'data' to all 'Z'. Something like the following... > > > OE <= '1', '0' after 55 ns; > > data <= "00010000", "01010101" after 15 ns, "ZZZZZZZZ" after 55 ns; > > ram: RamChip port map(address, data, CS, WE, OE); > > Kevin Jennings Thanks for that kevin. That's awesome. DavidArticle: 128271
>The nicest solution would be over the internet, but I have not heard >about anything like that (yet). If you have a stable local clock, you can calibrate it over the net. Use NTP - Network Time Protocol. If you have a T1/T3 link, the bit rate on that is usually very accurate. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128272
I have the Spartan 3e starter kit. it has this model RAM on it (MT46V32M16). I have generated the memory controller for it, but I would like to play with it on ModelSim first to help me understand DDR SDRAM operation. I am reading the spec sheet, but I would like to see it work in ModelSim also. I looked on the Micron site and they said that they don't do VHDL memory models any more. Has anyone got any clues as to where I could find a memory model for the DDR SDRAM that is on the Sparten 3e kit? DavidArticle: 128273
On Jan 19, 9:05 pm, Bucephalus <davidsullivan1...@gmail.com> wrote: > I have the Spartan 3e starter kit. > it has this model RAM on it (MT46V32M16). I have generated the memory > controller for it, but I would like to play with it on ModelSim first > to help me understand DDR SDRAM operation. I am reading the spec > sheet, but I would like to see it work in ModelSim also. > > I looked on the Micron site and they said that they don't do VHDL > memory models any more. > Has anyone got any clues as to where I could find a memory model for > the DDR SDRAM that is on the Sparten 3e kit? > > David I don't suppose you could live with the Verilog model? If your project is in VHDL you'd need a mixed language simulator. Otherwise I'd suggest finding another DDR SDRAM vendor who supplies VHDL models, but my first attempt at finding one (Samsung K4H511638D) revealed another company that provides only Verilog models. Maybe a European memory maker? Is there one? Here in the US Verilog is more popular for system-level simulation ;)Article: 128274
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message news:zcudnR4BM_5KOw_anZ2dnUVZ_j-dnZ2d@megapath.net... > > > If you have a T1/T3 link, the bit rate on that is usually > very accurate. > I wouldn't rely on that. T1 is only required to be Stratum 4 compliant, which is 32 ppm accuracy.
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