Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Op Wed, 05 Dec 2007 10:46:03 +0100 schreef comp.arch.fpga <ksulimma@googlemail.com>: > On 5 Dez., 09:57, "Boudewijn Dijkstra" <boudew...@indes.com> wrote: >> Your description below only applies to certain compression >> algorithms, so any conclusion derived from it may or may not apply to >> the >> general case. > ROTFL. > Did you even read it? Yes. Multiple times. > He outlined the formal prove that I was referencing to in a little > more detail. > > This proof shows, that for ANY lossless algorithm there is an input > that can't be > compressed. I find it rather funny that you counter that proof by the > assertion that it only applies to certain algorithms. I didn't mean to counter the proof itself, only claims to the relation between compression ratio and the bandwidth needed to split a stream. > For the fun of it: Would you be so kind and present a single example > of a compression > algorithm that the proof does not apply to? Could be worth a PhD if > you manage. Nah. I'd rather waste my time on something else. :) -- Gemaakt met Opera's revolutionaire e-mailprogramma: http://www.opera.com/mail/Article: 126876
Hi All, The Virtex-5 user guide lists RAM32X1D as a distributed RAM primitive, however this primitive is not listed in the libraries guide. Does anyone know whether this primitive is supported or not? Is this a Xilinx error? cheers, RobArticle: 126877
Im new to FPGA, so id like to ask what is "simultaneously switching output ? Is it connected with noise problem which comes from switching ? How to prevent it ? thx for all answers MWJArticle: 126878
Hello! I have made a serial firmware downloader for the EPC4 device, and have a couple of questions. After looking at different .pof files, it looks like the file is made up of (on the epc4): *******start-of-file**************************************** * header (50-100 bytes) * data (about 400 bytes with 0xFF as blank space) * signature (40-50 bytes) *******end-of-file **************************************** I can open a .pof file and program this to the EPC4 device IF i know the length of the header so i can remove it first. The header includes info about Quartus build date/version/device/comment e.t.c The .pof file also includes a signature, but since the useful data only exists until about 1/3 into the file, this signature is also removed when programming.. Does anyone know the .pof file format? I really need to know this: 1. Where is the header-length is specified? 2. What does the different "unknown" bytes in the header (except for the obvious ascii coded strings) specify? My application can also read the contens of the flash and save it to a file. It would be really useful if this could be saved in a .pof valid format, and written back using the quartus programming tool, so: 3. What does the Quartus programming tool look for to determine if the .pof is valid? (checksum? probably some of the info requested in 1, 2?) 4. What does the signature/footer describe? Thanks so much in advance, LTArticle: 126879
<wojjed@gmail.com> wrote in message news:07c44187-be07-4076-af0d-0a0bdd493ee7@s12g2000prg.googlegroups.com... > Im new to FPGA, so id like to ask what is "simultaneously switching > output ? Is it connected with noise problem which comes from > switching ? How to prevent it ? > > thx for all answers > > MWJ Dear MWJ, What annoys me is that you know how to use Google to post to usenet, and yet seem unable to carry out a basic search of the WWW for information. It's like going to the pub, and then shouting out of the window to ask people in the street to come in, go to the bar, and buy you a free beer. Sheesh. Hope this helps, Syms.Article: 126880
On Dec 4, 1:35 am, Mike Treseler <mike_trese...@comcast.net> wrote: > rickman wrote: > > Yes, you are right that this is not a "global" variable. But the > > point is that the one way you have it coded does not work with XST. > > So why is that a real problem? > > The fact that XST does not throw an error. > > Instead, it silently creates hardware that doesn't sim > anything like the code. > > > There are at least two way to code it > > correctly. This sort of thing (not supporting all valid code styles) > > has plagued HDLs since they were invented. > > Not supporting every odd version is fine. > Producing a bad netlist is not. > > > If you had > > procedures that were being shared I could see the point of it. But > > this is just breaking the code into modules for the sake of having > > modules, in my opinion. > > This is a simplified example with one purpose: > to demonstrate the bug to xilinx. > > When I write production > code, I use use procedures for duplicated blocks of code. > I do sometimes like to share a variable between > two procedures. > For example, I might want to share an > input register variable between a collect_data > procedure and a readback procedure > that packs in a status bit. It works fine. > If I make a mistake, it shows up in the sim, > just like any other mistake. > > -- Mike Treseler I agree wholeheartedly, Xilinx should not produce incorrect results, without an error message. Either do it right, or don't do it (stop with error). AndyArticle: 126881
On Dec 4, 11:03 am, rickman <gnu...@gmail.com> wrote:
> On Dec 4, 7:51 am, "KJ" <kkjenni...@sbcglobal.net> wrote:
>
>
>
> > "rickman" <gnu...@gmail.com> wrote in message
>
> >news:58740cd5-a79f-4306-bff9-c274852f2a01@e6g2000prf.googlegroups.com...
>
> > > On Nov 30, 5:15 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
> > >> "rickman" <gnu...@gmail.com> wrote in message
>
> > >> > The examples are far too numerous to list, but here is one.
> > >> <snip>
> > >> > To make this unsynthesizable in a way that is sometimes attempted by
> > >> > newbies...
>
> > >> > Example2: process (SysClk, Reset) begin
> > >> > if (Reset = '1') then
> > >> > DataOutReg <= (others => '0');
> > >> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
> > >> > if (SCFG_CMD = '1') THEN
> > >> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > >> > RTS;
> > >> > end if;
> > >> > end if;
> > >> > end process Example2;
>
> > >> > You can imagine a register that clocks on both the rising and falling
> > >> > edge, but you can't build it in an FPGA.
>
> > >> But that does not imply that it couldn't be synthesized using two sets of
> > >> flip flops whose results get combined. You might not find a synthesis
> > >> tool
> > >> in 2007 that accepts the above code, but that doesn't mean that there
> > >> won't
> > >> be one in 2008 that will. Whether there is such a tool or not depends on
> > >> how many users scream to brand A and X that they really need this. It
> > >> can
> > >> be synthesized, just not how you are focusing on how you think it must be
> > >> synthesized.
>
> > > If you can build the second description, I would like to see that. Do
> > > you know this is possible or are you just speculating? I have never
> > > seen a good example of a register clocked on both edges done in an
> > > FPGA.
>
> > Like I said, your description does not imply that it couldn't be synthesized
> > using two sets of flops suitably combined. See code below for functionally
> > equivalent code that implements your example 2 but does so in a way that I'm
> > sure you can see that it can be synthesized. Note, I'm not suggesting that
> > writing dual edge flop code is good practice or anything, I'm simply saying
> > that the code that you presented is synthesizable, since it is functionally
> > equivalent to the code that I list below which clearly is synthesizable.
> > That implies that your Example 2 code is just not supported by today's
> > tools, quite possibly due to the lack of any real demand for support for
> > such coding....but, like I said in the earlier post, 'not supported' is not
> > the same as 'not synthesizable'.
>
> > KJ
>
> > Example2a: process (SysClk, Reset) begin
> > if (Reset = '1') then
> > DataOutReg_re <= (others => '0');
> > elsif rising_edge(SysClk) then
> > if (SCFG_CMD = '1') THEN
> > DataOutReg_re <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > RTS;
> > end if;
> > end if;
> > end process Example2a;
>
> > Example2b: process (SysClk, Reset) begin
> > if (Reset = '1') then
> > DataOutReg_fe <= (others => '0');
> > elsif falling_edge(SysClk) then
> > if (SCFG_CMD = '1') THEN
> > DataOutReg_fe <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > RTS;
> > end if;
> > end if;
> > end process Example2b;
>
> > DataOutReg <= DataOutReg_re when (SysClk = '1') else DataOutReg_fe;
>
> I am not sure you are correct in that the two circuits are
> equivalent. I was thinking about how such a circuit would not work in
> a practical sense, although logically it is the same as the one I
> wrote. So from a synthesis standpoint, this circuit could be
> synthesized. However, it would likely not work as intended since it
> depends too much on controlling delays. So I see your point, but I
> disagree that the two circuits are the same.
>
> I don't argue that "not supported" is the same as "not
> synthesizable". But I think there is a very small set of useful
> designs that are synthesizable but not supported by most vendors.
The following double edge flop implementation avoids potential
glitches on the output (after all, it is supposed to act like a
register). Not all synthesis tools support the single process style,
but it can easily be split into two clocked processes and a concurrent
assignment.
process (clk, rst) is
variable qr,qf : std_logic;
begin
if rst = '1' then
qr := '0';
qf := '0';
elsif rising_edge(clk) then
qr := d xor qf;
elsif falling_edge(clk) then
qf := d xor qr;
end if;
q <= qr xor qf; -- combinatorial xor of registered qr,qf
end process;
This description also illustrates a way to have combinatorial logic on
the output of registers, within a clocked process. That is a very
useful feature that is not supported by all tools. It also allows for
the exportation via signals (or output ports) from local variables
(registered values thereof), without creating a duplicate register
that is then (usually) optimized out.
Andy
Article: 126882u_stadler@yahoo.de wrote: > HI > > I have a question about the use of an BUFGCE in a xilinx design. > (currently using a virtex 4). > when i enable the buffer it seems to loose one clock cycle. > > 1 2 3 4 > ___ ___ ___ ___ ___ > CLK_IN __| |___| |___| |___| |___| | > _________________________ > ENABLE _______| > ___ ___ ___ > CLK_OUT _______________| |___| |___| | > > (hope the drawing dosen't get messed up) > > can anyone tell my why i don't see clock cycle number 2 on the output? > i read in the virtex4 datasheet (if i understood that right) that the > second > clock cycle should be on the output. any ideas what i'm doing wrong? > > thanks > urban It was my impression that this glitchless device was very well documented. Have you read up on the BUFCE or did you just come straight here when it didn't look like the AND gate you expected? The BUFCE will guarantee the output doesn't produce a runt pulse by using some elegant asynchronous handshaking. Thanks, Peter! While my mind tends to settle back on the BUFGMUX which has stronger needs, the control for the BUFCE *may* simply register the enable control on the falling edge of CLK_IN so the CLK_OUT is guaranteed to be a full high pulse.Article: 126883
well no i didn't come stright here. i looked it up in the virtex datasheet but as far as i understood (and read) it doesn't register the enable on the falling edge. although it appears to be like that when i look at the simulation... but if i compare it with the timing diagramm from the datasheet it looks different.. in that timing diagramm the clock output is working immediately after the enable (even if there is no falling edge) thanksArticle: 126884
On Dec 5, 1:57 pm, "Symon" <symon_bre...@hotmail.com> wrote: > <woj...@gmail.com> wrote in message > > news:07c44187-be07-4076-af0d-0a0bdd493ee7@s12g2000prg.googlegroups.com...> Im new to FPGA, so id like to ask what is "simultaneously switching > > output ? Is it connected with noise problem which comes from > > switching ? How to prevent it ? > > > thx for all answers > > > MWJ > > Dear MWJ, > What annoys me is that you know how to use Google to post to usenet, and yet > seem unable to carry out a basic search of the WWW for information. It's > like going to the pub, and then shouting out of the window to ask people in > the street to come in, go to the bar, and buy you a free beer. > Sheesh. > Hope this helps, Syms. Simultanious Switching Outputs (SSO) is (as you'd expect) to do with what happens then mutliple output pins of a device change simultaniously. Since each IO will consume power to change state (due to driving external capacitance), when lots of IOs change state simultaniously the transient power requirements can be quite demanding and cause Vcc sag/ ground bounce. The effects of SSO can be mitigated with a good decoupling network, good PSU design, turning down drive strengths, reducing simultaniously switching ouputs, and probably other things I've forgotten. As already pointed out there is alot of information on this available online, and Xilinx cover the issue in detail. RobArticle: 126885
Thanks for the input. I've gained a little more direction (for anyone who is interested), I've settled on a transport triggered architecture (http://en.wikipedia.org/wiki/Transport_Triggered_Architectures) with a number reconfigurable elements. On Dec 4, 5:33 pm, Jecel <je...@merlintec.com> wrote: > Though not what you were asking for, you might find this bibliography > page interesting: > > http://splish.ee.byu.edu/bib/bibpage.html > > You might want to look at some of the projects being done on the > "RAMP": > > http://ramp.eecs.berkeley.edu/ > > -- JecelArticle: 126886
"John_H" <newsgroup@johnhandwork.com> wrote in message news:5Ey5j.6002$6k1.2736@trndny02... > While my mind tends to settle back on the BUFGMUX which has stronger > needs, the control for the BUFCE *may* simply register the enable control > on the falling edge of CLK_IN so the CLK_OUT is guaranteed to be a full > high pulse. The BUFGCE and BUFGMUX are the same element: http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0069_53.htmlArticle: 126887
I recently upgraded from a Centos 4.5 x86_64 (Red Hat Enterprise 4 Update 5) installation to Centos 5.1. I reinstalled the O/S from scratch. When I try to install Xilinx ISE 9.2 Foundation (Evaluation) on my Centos 5.1 x86_64 machine, the './setup' script in the DVD's root-directory doesn't work. When I run it from the shell, it says 'Permission denied.' I did not have this problem with Centos 4.5. I tried the 'Webpack 9.2' web-download, and that setup script has no problem running under Centos 5.1. Did I miss something? When I installed Centos 5.1, I selected all the packages (compat libraries, etc.).Article: 126888
On Wed, 2007-12-05 at 15:09 +0000, Helpme wrote: > I recently upgraded from a Centos 4.5 x86_64 (Red Hat Enterprise 4 Update 5) > installation to Centos 5.1. > > I reinstalled the O/S from scratch. When I try to install Xilinx ISE 9.2 > Foundation (Evaluation) on my Centos 5.1 x86_64 machine, the './setup' > script in the DVD's root-directory doesn't work. > > When I run it from the shell, it says 'Permission denied.' I did not have > this problem with Centos 4.5. > Did you even tried to remount your DVD with the 'exec' option? First of all you should read 'man mount'. JanArticle: 126889
On Dec 5, 3:57 am, "Boudewijn Dijkstra" <boudew...@indes.com> wrote: > Op Tue, 04 Dec 2007 17:50:46 +0100 schreef rickman <gnu...@gmail.com>: > > > But noise and signal that "resembles noise" are two different things. > > You can characterize noise and send a description of it. But it is > > *isn't* noise you have just turned part of your signal into noise. So > > to take advantage of the fact that noise can be compressed by saying > > "this is noise" requires that you separate the noise from the signal. > > If you could do that, why would you even transmit the noise? You > > wouldn't, you would remove it. > > If you could, yes. Costs put limits on the available processing power. That is irrelevant to the conversation. No one has mentioned data rates, processing power or time requirements. So there is no point is raising issues that we have no information on. But my point remains. If your algorithm can remove the true noise separated from signal that looks like noise, then you would just toss the real noise and improve the signal while compressing at the same time. That is my point and from what you have said, it requires no extra processing, but is part of your compression. > > How can you flag the "easy" (compressible) part vs. the "hard" part > > without sending more bits? > > In the context of the OP's hardware implementation, you may be able to > distribute these two streams over the available output pins without > sending extra bits. If the OP has two streams, one for compressible signal and one for uncompressible signal, then he could just send the original message over the uncompressible channel and avoid the issue of compression altogether. > > As I describe below, compression only saves bits if your *average* > > content has sufficient redundancy. So what does "possibly" mean? > > If compression saves 'a lot of' bits ands flagging needs 'a few' bits, > then it will not "add as much, if not more to the message than [I am] > removing..." Your description below only applies to certain compression > algorithms, so any conclusion derived from it may or may not apply to the > general case. Compression can only save bits in the subset of signals that actually are reducible. If you do the math you will find that if the signal is randomly distributed, any coding scheme can not reduce the total number of bits sent. It is only when some signal patterns are more frequent than others that you can exploit the non-randomness of the signal to compress it into fewer bits. I haven't said anything about algorithms, so everything I have said on this applies to *all* compression algorithms. My discussion below is intended to apply to the general case. That is why I reduce the discussion to one of compressing a large number to a smaller number. > >> > If you are trying to compress data without loss, you can only compress > >> > the redundant information. If the message has no redundancy, then it > >> > is not compressible and, with *any* coding scheme, will require some > >> > additional bandwidth than if it were not coded at all. > > >> > Think of your message as a binary number of n bits. If you want to > >> > compress it to m bits, you can identify the 2**m most often > >> > transmitted numbers and represent them with m bits. But the remaining > >> > numbers can not be transmitted in m bits at all. If you want to send > >> > those you have to have a flag that says, "do not decode this number". > >> > Now you have to transmit all n or m bits, plus the flag bit. Since > >> > there are 2**n-2**m messages with n+1 bits and 2**m messages with m+1 > >> > bits, I think you will find the total number of bits is not less then > >> > just sending all messages with n bits. But if the messages in the m > >> > bit group are much more frequent, then you can reduce your *average* > >> > number of bits sent. If you can say you will *never* send the numbers > >> > that aren't in the m bit group, then you can compress the message > >> > losslessly in m bits. > > -- > Gemaakt met Opera's revolutionaire e-mailprogramma: http://www.opera.com/mail/Article: 126890
On Wed, 05 Dec 2007 15:09:55 +0000, Helpme wrote: > I recently upgraded from a Centos 4.5 x86_64 (Red Hat Enterprise 4 > Update 5) installation to Centos 5.1. > > I reinstalled the O/S from scratch. When I try to install Xilinx ISE > 9.2 Foundation (Evaluation) on my Centos 5.1 x86_64 machine, the > './setup' script in the DVD's root-directory doesn't work. > > When I run it from the shell, it says 'Permission denied.' I did not > have this problem with Centos 4.5. > > I tried the 'Webpack 9.2' web-download, and that setup script has no > problem running under Centos 5.1. > Did I miss something? When I installed Centos 5.1, I selected all the > packages (compat libraries, etc.). Do a chmod on the script, it sounds like a permissions problem.Article: 126891
Hi Mike, I recently started working for a Lattice distributor in Ireland / UK and I am fairly shocked by your experience. > Lattice: Despite the abysmal experience of a visit by the UK/Ireland > Sales manager, I was still keen to learn of competing products, so I > attended a seminar arranged by a distributor. This was excellent, so In my own experience Lattice sales and FAE support has been very good. > I made enquiries about buying a development kit. It seemed that the > XP10 demo board would be best and the distributor was offering this at > the "special" price of $555. > I have got a feeling maybe they have quoted you for an XP2 standard eval board. XP2 was released about 6-8 months ago and would have been around that price when it came out first. XP2 is the latest NV based device family which is on a 90nm Flexi:Flash based arch. Regards Eoin Dowling FMG ElectronicsArticle: 126892
On Dec 5, 9:17 am, Andy <jonesa...@comcast.net> wrote: > On Dec 4, 11:03 am, rickman <gnu...@gmail.com> wrote: > > > > > On Dec 4, 7:51 am, "KJ" <kkjenni...@sbcglobal.net> wrote: > > > > "rickman" <gnu...@gmail.com> wrote in message > > > >news:58740cd5-a79f-4306-bff9-c274852f2a01@e6g2000prf.googlegroups.com... > > > > > On Nov 30, 5:15 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > > > >> "rickman" <gnu...@gmail.com> wrote in message > > > > >> > The examples are far too numerous to list, but here is one. > > > >> <snip> > > > >> > To make this unsynthesizable in a way that is sometimes attempted by > > > >> > newbies... > > > > >> > Example2: process (SysClk, Reset) begin > > > >> > if (Reset = '1') then > > > >> > DataOutReg <= (others => '0'); > > > >> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then > > > >> > if (SCFG_CMD = '1') THEN > > > >> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR & > > > >> > RTS; > > > >> > end if; > > > >> > end if; > > > >> > end process Example2; > > > > >> > You can imagine a register that clocks on both the rising and falling > > > >> > edge, but you can't build it in an FPGA. > > > > >> But that does not imply that it couldn't be synthesized using two sets of > > > >> flip flops whose results get combined. You might not find a synthesis > > > >> tool > > > >> in 2007 that accepts the above code, but that doesn't mean that there > > > >> won't > > > >> be one in 2008 that will. Whether there is such a tool or not depends on > > > >> how many users scream to brand A and X that they really need this. It > > > >> can > > > >> be synthesized, just not how you are focusing on how you think it must be > > > >> synthesized. > > > > > If you can build the second description, I would like to see that. Do > > > > you know this is possible or are you just speculating? I have never > > > > seen a good example of a register clocked on both edges done in an > > > > FPGA. > > > > Like I said, your description does not imply that it couldn't be synthesized > > > using two sets of flops suitably combined. See code below for functionally > > > equivalent code that implements your example 2 but does so in a way that I'm > > > sure you can see that it can be synthesized. Note, I'm not suggesting that > > > writing dual edge flop code is good practice or anything, I'm simply saying > > > that the code that you presented is synthesizable, since it is functionally > > > equivalent to the code that I list below which clearly is synthesizable. > > > That implies that your Example 2 code is just not supported by today's > > > tools, quite possibly due to the lack of any real demand for support for > > > such coding....but, like I said in the earlier post, 'not supported' is not > > > the same as 'not synthesizable'. > > > > KJ > > > > Example2a: process (SysClk, Reset) begin > > > if (Reset = '1') then > > > DataOutReg_re <= (others => '0'); > > > elsif rising_edge(SysClk) then > > > if (SCFG_CMD = '1') THEN > > > DataOutReg_re <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR & > > > RTS; > > > end if; > > > end if; > > > end process Example2a; > > > > Example2b: process (SysClk, Reset) begin > > > if (Reset = '1') then > > > DataOutReg_fe <= (others => '0'); > > > elsif falling_edge(SysClk) then > > > if (SCFG_CMD = '1') THEN > > > DataOutReg_fe <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR & > > > RTS; > > > end if; > > > end if; > > > end process Example2b; > > > > DataOutReg <= DataOutReg_re when (SysClk = '1') else DataOutReg_fe; > > > I am not sure you are correct in that the two circuits are > > equivalent. I was thinking about how such a circuit would not work in > > a practical sense, although logically it is the same as the one I > > wrote. So from a synthesis standpoint, this circuit could be > > synthesized. However, it would likely not work as intended since it > > depends too much on controlling delays. So I see your point, but I > > disagree that the two circuits are the same. > > > I don't argue that "not supported" is the same as "not > > synthesizable". But I think there is a very small set of useful > > designs that are synthesizable but not supported by most vendors. > > The following double edge flop implementation avoids potential > glitches on the output (after all, it is supposed to act like a > register). Not all synthesis tools support the single process style, > but it can easily be split into two clocked processes and a concurrent > assignment. > > process (clk, rst) is > variable qr,qf : std_logic; > begin > if rst = '1' then > qr := '0'; > qf := '0'; > elsif rising_edge(clk) then > qr := d xor qf; > elsif falling_edge(clk) then > qf := d xor qr; > end if; > q <= qr xor qf; -- combinatorial xor of registered qr,qf > end process; > > This description also illustrates a way to have combinatorial logic on > the output of registers, within a clocked process. That is a very > useful feature that is not supported by all tools. It also allows for > the exportation via signals (or output ports) from local variables > (registered values thereof), without creating a duplicate register > that is then (usually) optimized out. The only trouble is that this is not at all equivalent to the code I wrote. This code is describing two registers with two separate inputs and two separate outputs that are then XORed together. How is this like a register that is clocked on both edges of the clock?Article: 126893
On Dec 4, 2:35 am, Mike Treseler <mike_trese...@comcast.net> wrote: > rickman wrote: > > Yes, you are right that this is not a "global" variable. But the > > point is that the one way you have it coded does not work with XST. > > So why is that a real problem? > > The fact that XST does not throw an error. > > Instead, it silently creates hardware that doesn't sim > anything like the code. Yes, I was forgetting that "little" issue. > > There are at least two way to code it > > correctly. This sort of thing (not supporting all valid code styles) > > has plagued HDLs since they were invented. > > Not supporting every odd version is fine. > Producing a bad netlist is not. I agree. This is the sort of thing that is very hard to find in a design once it gets past your simulation and fails on the real chip. I suppose it would fail in a post route simulation, no? > > If you had > > procedures that were being shared I could see the point of it. But > > this is just breaking the code into modules for the sake of having > > modules, in my opinion. > > This is a simplified example with one purpose: > to demonstrate the bug to xilinx. Yes, I agree with you and I see that my concerns would not valid. > When I write production > code, I use use procedures for duplicated blocks of code. > I do sometimes like to share a variable between > two procedures. > For example, I might want to share an > input register variable between a collect_data > procedure and a readback procedure > that packs in a status bit. It works fine. > If I make a mistake, it shows up in the sim, > just like any other mistake. > > -- Mike TreselerArticle: 126894
I have a simple design (about 300 logic elements / 150 registers) written in Verilog. It's highly self-contained (only about ten signals on the interface). (For the curious, it performs a function for analogue video). It's now proposed to incorporate this in a design which is otherwise VHDL (and over which I shall have no control). Obviously, the Verilog could be converted, but this would be significant work (and I no have no experience at present of VHDL). For this reason (and particularly since the interface is simple), I'd like to keep my part of the design in Verilog. Is mixed-language design well-supported? If so, does anyone have general advice or words of caution? MikeArticle: 126895
On Dec 5, 3:24 am, Alex Freed <al...@mirrow.com> wrote: > I'm planning to use Spartan 3e and SDRAM for a product - sort of a > simple video "card" for an embedded CPU system. > > I got myself the Spartan 3e STARTER kit and I'm trying to use the SDRAM > on board. Found the MIG 1.6 and the pre-configured "bl2cl2" set of > files. Got them to synthesize by editing a full (wrong for me) path to > "params" file. So far so good. Changed the UCF to use the 50 MHz clock > rather than the external one. The resulting bit file loads and does > *something*. At least there are pulses on "data valid" LED. > > I may get somewhere if I continue on this path but it will take me a > long time to figure out how this core works. > > I wonder if anyone knows of an existing design that uses SDRAM on this > board interfaced to something: soft CPU, video generator, etc. > > Thanks. > > -Alex. I've found that www.xilinx.com is an excellent resource for Spartan FPGA questions. There's a design that uses the board's DRAM here: <http://www.xilinx.com/products/boards/s3estarter/ reference_designs.htm> G.Article: 126896
hello when i look at the timing report of my fpga i see that the why do i see negative clock hold time of my input pins is NEGATIVE Thold= -5ns i dont understand why thanks for the helpArticle: 126897
We have been promising this for a while and I am finally pleased to show first images and details of Drigmorn1 here http://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We are aiming this to be the cheapest develoment board out there so if know any cheaper do let me know. We have some more testing to do before we let it out in the wild but hopefully that will be complete before Christmas to allow shipment before the holidays. Use of this board is simplistic. A simple 5v jack for power and a RS232 interface to allow control by a PC using a terminal emulator etc. like Hyperterminal. Special variants do allow use as part of customer boards or prototypes and we should have some application notes coming on these more unusual uses of this board. I am also interested in what features everyone would like as and when we do a Drigmorn2 bearing in mind it is a very cost sensative design. It's a derivative of the new version Craignell family (obsolete and enhanced DIL/DIP component replacements) and pictures of those will be available soon too. We have done a lot of work to improve manufacturing yield on these and the Drigmorn1 and some of the work we have done here will allow the even smaller narrow version Craignells to made Q1/2008. John Adair Enterpoint Ltd.Article: 126898
"guy" <MADORIG@gmail.com> wrote in message news:47b45cc8-d072-405e-a513-6173c6cf1d5e@d61g2000hsa.googlegroups.com... > hello > when i look at the timing report of my fpga > i see that the why do i see negative clock hold time > of my input pins is NEGATIVE > Thold= -5ns > > i dont understand why > > thanks for the help I assume you mean a negative data hold time (with respect to the clock). This is caused by having a much greater delay in the pad to D input of a flip flop than in the pad to clock input. Having combinatorial logic between the pad and the flip flop could be one cause. Presumably your setup time requirement is rather lengthy too.Article: 126899
rickman wrote: > The only trouble is that this is not at all equivalent to the code I > wrote. This code is describing two registers with two separate inputs > and two separate outputs that are then XORed together. How is this > like a register that is clocked on both edges of the clock? Like this? http://home.comcast.net/~mike_treseler/double_edge.pdf http://home.comcast.net/~mike_treseler/double_edge.vhd -- Mike Treseler
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z