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Messages from 79675

Article: 79675
Subject: Re: SD Card and FPGA
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 23 Feb 2005 08:56:56 +0100
Links: << >>  << T >>  << A >>

"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag
news:6kKSd.65146$2e4.63938@news.chello.at...
> It seems that the SD/MMC cards get popular for FPGA designs
> today. These cards are real consumer products and are in effect
> cheaper than bare NAND chips (for low/medium volume).
> I would like to summarize the facts I've found in c.a.f [1] and on
> various web sites.

http://www.tietokone.fi/uutta/uutinen.asp?news_id=22555

at embedded 2005 a connector manufacturer said they already have microMMC
connector
(production availability in a few months)

microMMC is even smaller than miniSD :)

Antti



Article: 79676
Subject: re:Debugging error in VHDL
From: payton.quackenbush@gmail-dot-com.no-spam.invalid (pdq)
Date: Wed, 23 Feb 2005 02:07:47 -0600
Links: << >>  << T >>  << A >>
Without seeing the actual code affected, here are the likely
problems:

> 
> HDLParsers:3324 - IN mode Formal enable of add8bit_wc with
> no default value must be associated with an actual value.
> 

You're have no signal connected to the
add8bit_wc input port.

> 
> HDLParsers:162 - Read symbol PORT, expecting ';'.
> 

You're probably missing a [b:3ce96a8410];[/b:3ce96a8410] in your
code.

If these still don't work, post the code and you'll get a more
specific answer.


Article: 79677
Subject: Debugging error in VHDL
From: akshye@rediffmail-dot-com.no-spam.invalid (akshye)
Date: Wed, 23 Feb 2005 02:07:47 -0600
Links: << >>  << T >>  << A >>
I have got two errors in my VHDL program of an ALU. The errors are

HDLParsers:3324 - IN mode Formal enable of add8bit_wc with
 no default value must be associated with an actual value.
HDLParsers:162 - Read symbol PORT, expecting ';'.

Anyone there please help me out.


Article: 79678
Subject: reading from CF
From: cuarentaperros@msn-dot-com.no-spam.invalid (pepeprisas)
Date: Wed, 23 Feb 2005 02:07:47 -0600
Links: << >>  << T >>  << A >>
Hi to everyone, 

I have an Avnet XILINX Virtex-II Pro FPGA xc2vp7ff896 and I am trying
to make simple designs work on this board.
I'm using EDK 6.3 for designing purposes and Impact to generate the
ace file and copying it to the compact flash card. 
I have already tried 3 or 4 different designs and none of them seem to
work on this board.
I think i'm doing everthing correctly since on power up I choose the
design to be executed with the dip switches on S1 and reset the board
with the first dip switch on S2 like the manual says.
Although everything seems to work correctly (no error lights on the
board) there is no type of response from the application through
serial port of the board on to the hyperterminal session on my PC.
Nevertheless when I try booting the .ace files that come preconfigured
from factory on the compact flash they all work correctly.
¿Is there something i'm missing making the design?
When choosing files to add to the ace file, ¿do I choose only the .bit
file or do I also choose the .elf file? When I choose both I have
error lights on the board.
¿Is there any way of debugging the application without the JTAG
parallel cable?
¿Do I have to include SysACE component in EDK designs in order to be
able to boot from the CF card? If I include SysACE component EDK no
longer lets you choose SDRAM component, necessary for nearly all my
designs.

Thankyou.


Article: 79679
Subject: re:Synchronizing multibit bus
From: payton.quackenbush@gmail-dot-com.no-spam.invalid (pdq)
Date: Wed, 23 Feb 2005 02:07:48 -0600
Links: << >>  << T >>  << A >>
> Does that mean that using a multi-stage flip flop chain to
synchronize
> the asynchronous input bus will lead to invalid values ?

Yes, this is called the correlation issue.  You can put any number of
flip-flop synchronizers in the design, but you need different
synchronizers for each individual bit (remember, flip flops are by
design for single bits, not busses).  Thus each bit's metastability
is independent of each other.

So, you can have one of the bits in the bus go metastable, and even
though there are multiple synchronizers to protect you from reading
the metastable bit, its metastability delayed the bit propagation by
one or more clock cycles.   Thus, the end result is that all the bits
look correct except one (because that bit is one or more clock cycles
delayed).


Article: 79680
Subject: re:How to handle clock skew?
From: payton.quackenbush@gmail-dot-com.no-spam.invalid (pdq)
Date: Wed, 23 Feb 2005 02:07:48 -0600
Links: << >>  << T >>  << A >>
> As a result there is always the possibility of incorrect circuit
> functionality due to clock skew.

Sure, and that is one reason why static timing analysis tools have
been created.  If you constrain your clock paths using the timing
analyzer, you can sets requirements on the skew so that the tools
either route the clocks well, or fail with timing errors.  Look into
the Quartus documentation for how to actually implement this.

Also, depending on the part you are using, you probably have a PLL
available, as well as global clock nets, which will do an excellent
job of generating a low-skew global clock.


Article: 79681
Subject: re:Source of reset for synchronous reset can lead to metastabil
From: payton.quackenbush@gmail-dot-com.no-spam.invalid (pdq)
Date: Wed, 23 Feb 2005 02:07:48 -0600
Links: << >>  << T >>  << A >>
> The problem is a logic race, not metastability.
> One way or another, the reset pulse needs to
> be synchronized before it gets to the global
> reset network on the fpga.

This is absolutely false.  Asynchronous resets are safe on the
assertion of them (who cares if some of the flops go
metastable--you're in reset), but can be disastrous on their
deassertion.  If reset is deasserted too close to the clock edge,
flops can go metastable.

For an excellent discussion of synchronous vs. asynchronous resets,
and techniques for safely resynchronizing asynchronous resets into a
clock domain please see the following papers:

http://klabs.org/richcontent/General_Application_Notes/reset_sync_async_v2.pdf

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets_rev1_1.pdf


Article: 79682
Subject: Virtex-4 FPGA with Jbits3.0?
From: insidebeans@yahoo.com-dot-br.no-spam.invalid (Joelmir Jose Lopes)
Date: Wed, 23 Feb 2005 02:07:49 -0600
Links: << >>  << T >>  << A >>
I would like to acquire the Virtex-4, however, I would
like to know which the tool that could make partial and dynamic
reconfigurable with such FPGA.  
Did I use JBits for Virtex, however he was not very good, does exist 
other tool  for the Virtex-4 for partial and dynamic reconfigurable
this system? 
Which tool do me use for the Virtex-4 to do the partial and dynamic
reconfigurable?    :roll: 
Thankful
Joelmir


Article: 79683
Subject: Open Request for Help
From: scraven@vt-dot-edu.no-spam.invalid (scraven)
Date: Wed, 23 Feb 2005 02:07:49 -0600
Links: << >>  << T >>  << A >>
I'll expand my request to all. 

I am seeking to build a multiprocessor system of Microblazes linked
using the FSL.  Unfortunately, I have been unable to find any
documentation on this.  The Xilinx AppNote 529 deals with an external
IP core and has been little help.

Any suggestions / info would be greatly appreciated.

Much thanks,
Stephen Craven


Article: 79684
Subject: Re: (Q) interconnections between microblazes
From: scraven@vt-dot-edu.no-spam.invalid (scraven)
Date: Wed, 23 Feb 2005 02:07:49 -0600
Links: << >>  << T >>  << A >>
Matt,

I am attempting a multiprocessor system using the microblaze in
support of reconfigurable computing research.  Would it be possible
for me to obtain a copy of the system.mhs file you mentioned?

Information on connecting MBs using the FSL is difficult to find.

Thanks!
Stephen Craven
Configurable Computing Lab
Virginia Tecg

> Matthew Ouellettewrote:
Jae,
> 
> I would recommend the FSL connections, as they make good
> point-to-point type of communication that you describe.
> 
> In a separate email, I will send you a MHS file of a
dual-MicroBlaze
> system, along with C code.  You should extend this system by adding
> FSL interfaces to other MicroBlaze nodes in your system.
> 
> ...
> 
> Matt
> 
> 


Article: 79685
Subject: re:C compiler for Picoblaze
From: moti@terasync-dot-net.no-spam.invalid (Moti Cohen)
Date: Wed, 23 Feb 2005 02:07:49 -0600
Links: << >>  << T >>  << A >>
Hi Francesco,
I would realy like to get your free C compiler for Picoblaze
and to help you with its testing ..
You are welcome to send it to me to my email

Best regards, Moti.


Article: 79686
Subject: re:xil_malloc vs malloc
From: nicolas.gac@lis.inpg-dot-fr.no-spam.invalid (nicolas.gac)
Date: Wed, 23 Feb 2005 02:07:49 -0600
Links: << >>  << T >>  << A >>
I have got the same problem with EDK 6.3 for a powerPC on a V2P.
OS = Standalone

I opened a webcase on Xilinx web site. I will tell you if they say
something new about this case.

Nicolas


Article: 79687
Subject: interrupt handler problem
From: digitreaco@yahoo-dot-de.no-spam.invalid (digi)
Date: Wed, 23 Feb 2005 02:07:50 -0600
Links: << >>  << T >>  << A >>
Hallo to all!

I use memec development boart with virtexIIpro with ppc_405. I have
designed my own IPCore witch a interrupt signal.
And there i have a problem witch the Interrupt Handler. When a
Noncritical Interrup accur the ppc stops and only way go further is
to turn it off. I have debugg it and i saw that, when the interrupt
accur it goes to vectrortable 0x0500 store the register and then
begin calculate the address of my handler. And there is the
Problem!!! By calculating it stops and the PowerPC make notihng more
:-(

I think it could be a timing problem with my external SDRAM but i'm
not sure.
Can me somebody help there?
Thanks!


Article: 79688
Subject: Re: C compiler for Picoblaze
From: eng_ramy_gad@yahoo-dot-com.no-spam.invalid (ramy)
Date: Wed, 23 Feb 2005 02:07:50 -0600
Links: << >>  << T >>  << A >>
plz send it to me on this mail 

eng_ramy_gad@yahoo.com


Article: 79689
Subject: Problems with a 4-MicroBlaze Multiprocessor Architecture
From: sergio.tota@polito-dot-it.no-spam.invalid (sergio.tota)
Date: Wed, 23 Feb 2005 02:07:51 -0600
Links: << >>  << T >>  << A >>
Dear all,

I'm a new member of this board so a big hello to everybody.

I'm experiencing some problems with a multiprocessor architecture
based on the MicroBlaze.

I'm using ISE 6.3 and EDK 6.3.

I made 2 working multiprocessor systems with 2 CPUs.

The first use only one OPB bus and both the processors are linked to
such bus,

The second implementation use ONE OPB bus for each processor, for a
total of 2 processors and 2 OPB bus.
In this version obviously each processor lives "stand-alone" with no
interaction with the other.
(I  used 2 ethernet IPs to let talk each-other...)

My problems started when I tried to implement a system with 4
processors linked to the same OPB bus.

The synthesis and P&R flow worked correctly and no errors were
given.

I then wrote 4 similar applications, one for each processor.

What I found was that only the first 2 processors worked and the other
2 seemed to be "dead".

What I thought first is that due to collisions, the last 2 processors
were never able to access to the bus,
So I tried to "disable" the first 2 processors ( not uploading the
firmware into the blockram) to see if the other 2 were able to
"scream" but nothing happened.

It seams that for some strange reason, if I use more than 2 processor
on an OPB bus, I can let them working correctly....( I don't want to
use the FSL for now...)

Any idea?

Thanks a lot!

Sergio


Article: 79690
Subject: Re: Tristate Discussion
From: =?ISO-8859-1?Q?Andr=E9s?= <nospam_nussspucke@gmx.de>
Date: Wed, 23 Feb 2005 09:55:20 +0100
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
>>Is it possible to use a tristate VHDL description in a hierarchical design 
>>that is in a sub module or do I have to use it only on the top level 
>>description
> 
> 
> You can use it in any module. Just declare your signals inout. You
> can even use tri-state busses internal to avoid coding the MUXs.
> The synthesizers are smart enough to substitute the tri-state busses
> by MUXs. I've used this to define in one module which IO components
> are integrated for the processor only by component declarations.
> 
> 
>>WHEN using QuartusII version 4.2  ?
> 
> Yes Quartus does fine. It has (or had) only a problem when you
> assigne the 'Z' value inside a clocked process. Better do it outside of
> a process with a concurrent statement.
> 
> Martin 
> 
> 

Hi Martin,

thank you for your reply.

What do you mean with "Just declare your signals inout" ?

I have a sub-module called "sdram.ctrl.vhd" which has an inout port 
"DQ[15..0]". The tristate description is within that module.
On my top level file I instantiate the module with

i4 : sdram_ctrl
      port map ( ...
                 DQ => top_signal_dq,
                 ...
                );
"top_signal_dq" is of STD_LOGIC_VECTOR(15 DOWNTO 0).

In the top level file I make then the assignment:

DQ_TOP <= top_signal_dq;

where DQ_TOP is a bidirectional port of the top level.


So the question is:
Can I connect two inout lines with a signal of STD_LOGIC ?
Or should I make the direct assignment ?

i4 : sdram_ctrl
      port map ( ...
                 DQ => DQ_TOP,
                 ...
                );

Kind Regards
Andrés

Article: 79691
Subject: Re: Problems with a 4-MicroBlaze Multiprocessor Architecture
From: =?ISO-8859-15?Q?G=F6ran_Bilski?= <goran.bilski@xilinx.com>
Date: Wed, 23 Feb 2005 10:16:57 +0100
Links: << >>  << T >>  << A >>
Hi,

If you connect four MicroBlazes to the same opb bus, I suspect that the last two 
MicroBlaze will get very little access to the bus.

Not uploading firmware for the first one, will not stop them from executing.

So what communication do you need between the MicroBlazes?
Have you looked at using the FSL as the inter communication channel?

Göran Bilski

sergio.tota wrote:
> Dear all,
> 
> I'm a new member of this board so a big hello to everybody.
> 
> I'm experiencing some problems with a multiprocessor architecture
> based on the MicroBlaze.
> 
> I'm using ISE 6.3 and EDK 6.3.
> 
> I made 2 working multiprocessor systems with 2 CPUs.
> 
> The first use only one OPB bus and both the processors are linked to
> such bus,
> 
> The second implementation use ONE OPB bus for each processor, for a
> total of 2 processors and 2 OPB bus.
> In this version obviously each processor lives "stand-alone" with no
> interaction with the other.
> (I  used 2 ethernet IPs to let talk each-other...)
> 
> My problems started when I tried to implement a system with 4
> processors linked to the same OPB bus.
> 
> The synthesis and P&R flow worked correctly and no errors were
> given.
> 
> I then wrote 4 similar applications, one for each processor.
> 
> What I found was that only the first 2 processors worked and the other
> 2 seemed to be "dead".
> 
> What I thought first is that due to collisions, the last 2 processors
> were never able to access to the bus,
> So I tried to "disable" the first 2 processors ( not uploading the
> firmware into the blockram) to see if the other 2 were able to
> "scream" but nothing happened.
> 
> It seams that for some strange reason, if I use more than 2 processor
> on an OPB bus, I can let them working correctly....( I don't want to
> use the FSL for now...)
> 
> Any idea?
> 
> Thanks a lot!
> 
> Sergio
> 

Article: 79692
Subject: Quartus DESIGN ASSISTANT tool
From: =?ISO-8859-1?Q?Andr=E9s?= <nospam_nussspucke@gmx.de>
Date: Wed, 23 Feb 2005 10:52:13 +0100
Links: << >>  << T >>  << A >>
Hi FPGA people,

I am using the VHDL module showed
to synchronize my external asynchronous reset into my FPGA.
When the external asynchronous reset gets inactive
the flip flop chain makes sure that Reset_sync is
deactivated synchronously.

The QuartusII (version 4.2) DESIGN ASSISTANT shows the following
MEDIUM warning after synthesis:

 >External reset ARESET_N should be synchronized using two cascaded 
 >registers

My question: Why should I synchronize the Areset_n to feed
the Aset port of the flip flops ? If I did so
there would arise the problem that the output of the flip flop chain
(Reset_sync) would become uncertain when the PLL is not locked.

Should I let is that way or should I trust the recommendation
of the DESIGN ASSISTANT tool ?

What is your opinion ?


LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY safe_reset IS
PORT ( Clk           : IN  STD_LOGIC;
        Areset_n      : IN  STD_LOGIC;
        PLL_locked    : IN  STD_LOGIC;
        Reset_sync    : OUT STD_LOGIC
      );
END safe_reset;


ARCHITECTURE rtl OF safe_reset IS

COMPONENT reset_flipflop
           PORT ( Clock : IN  STD_LOGIC;
                  Aset  : IN  STD_LOGIC;
                  Data  : IN  STD_LOGIC;
                  Q     : OUT STD_LOGIC
                );
END COMPONENT;

SIGNAL l_q1 : STD_LOGIC;
SIGNAL l_q2 : STD_LOGIC;
SIGNAL l_q3 : STD_LOGIC;
SIGNAL l_q4 : STD_LOGIC;

SIGNAL l_ena_shift : STD_LOGIC;

SIGNAL l_areset    : STD_LOGIC;

BEGIN

Reset_sync  <= l_q4;
l_ena_shift <= not ('0' xor Pll_locked);
l_areset    <= not Areset_n;


i1 : reset_flipflop
      PORT MAP ( Clock => Clk,
                 Aset  => l_areset,,
                 Data  => l_ena_shift,
                 Q     => l_q1
               );
i2 : reset_flipflop
      PORT MAP ( Clock => Clk,
                 Aset  => l_areset,
                 Data  => l_q1,
                 Q     => l_q2
               );
i3 : reset_flipflop
      PORT MAP ( Clock => Clk,
                 Aset  => l_areset,
                 Data  => l_q2,
                 Q     => l_q3
               );
i4 : reset_flipflop
      PORT MAP ( Clock => Clk,
                 Aset  => l_areset,
                 Data  => l_q3,
                 Q     => l_q4
               );

END rtl;

Article: 79693
Subject: what's the difference between syn FIFO and asyn FIFO?
From: "changewhere" <changewhere@126.com>
Date: Wed, 23 Feb 2005 19:04:59 +0800
Links: << >>  << T >>  << A >>
Hi,
    I'm designing a itu656 video data format decoder, where I need use a
FIFO to send the active pixel to the next module for processing.
    But, as you known, I'm a newbie in EDA field. I can't say what kind of
FIFO will be useful in this design and I don't know how to use the xilinx
FIFO ip core.
    Anybody has a project like this? Can you give me a application note of
how to use the xilinx FIFO IP Core?
    Thank you!
                                                                        willie
CHEN
                                                                        kmust,china





Article: 79694
Subject: XST: How to select the architecture for synthesis?
From: schmalisch@yahoo.de (Mathias Schmalisch)
Date: 23 Feb 2005 04:02:48 -0800
Links: << >>  << T >>  << A >>
Hi,

I have an VHDL toplevel entity with multiple architectures. If I try
to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
then only the last architecture will be synthesized.

Therefore my question: Is it possible to select the architecture that
will be synthesized and how this work?

Best Regards
Mathias

Article: 79695
Subject: Altera JTAG Jam STAPL player portet to Linux for Byteblaster?
From: "Nils Koehler" <nils.koehler@ibt-interfaces.de>
Date: Wed, 23 Feb 2005 13:09:30 +0100
Links: << >>  << T >>  << A >>
Hi all,



Has anyone ported the Altera Jam STAPL JTAG player

for the Byteblaster, to use it as a linux utility?



Kindest Regards



Nils Koehler






-- 
-----------------------------------------------
Nils Köhler
IBT Interfaces
Im Taubhaus 19
63322 Rödermark
Germany

Tel:  +49-6074-6964-160
Fax: +49-6074-6964-161



Article: 79696
Subject: Re: XST: How to select the architecture for synthesis?
From: Tuukka Toivonen <tuukkat@killspam.ee.oulu.finland.invalid>
Date: Wed, 23 Feb 2005 12:49:29 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2005-02-23, Mathias Schmalisch <schmalisch@yahoo.de> wrote:
> I have an VHDL toplevel entity with multiple architectures. If I try
> to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
> then only the last architecture will be synthesized.
>
> Therefore my question: Is it possible to select the architecture that
> will be synthesized and how this work?

In principle you can do that in VHDL using the
configuration specification like

for all : xxx use entity yyy(rtl)

..but my experience is that very few of synthesis programs support it.
At least Synopsys Design Compiler doesn't. I don't know a better
solution except that just to comment out other architectures and leave
just one. If anyone knows a better way, let me know.

Article: 79697
Subject: Re: How to select the architecture for synthesis?
From: "Ansgar Bambynek" <a.bambynek_xxx_@avm.de>
Date: Wed, 23 Feb 2005 15:38:03 +0100
Links: << >>  << T >>  << A >>
Hi,

any particular reason why you do have several architectures within your
entity?

Usually as you have already mentioned the last architecture gets
synthesized.
You might check the XST manuals or the Xilinx homepage if pragmas might
help.

According to the constraints guide for ise6.3i p. 821 xst can handle
translate_on and translate_off.
The constraints guide is downloadable as zipped pdf from the XILINX homepage

HTH

Ansgar

--
Attention please, reply address is invalid, please remove "_xxx_" ro reply
"Mathias Schmalisch" <schmalisch@yahoo.de> schrieb im Newsbeitrag
news:962628c0.0502230402.6158e525@posting.google.com...
> Hi,
>
> I have an VHDL toplevel entity with multiple architectures. If I try
> to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool,
> then only the last architecture will be synthesized.
>
> Therefore my question: Is it possible to select the architecture that
> will be synthesized and how this work?
>
> Best Regards
> Mathias



Article: 79698
Subject: Spartan-3 partial reconfiguration trouble
From: "Pablo Bleyer Kocik" <pablobleyer@hotmail.com>
Date: 23 Feb 2005 06:49:42 -0800
Links: << >>  << T >>  << A >>
 Hello group.

 I am trying to get my Spartan3-based design to partially reconfigure
itself using Answer Record #18416 as a guideline
(http://www.xilinx.com/xlnx/xil_ans_printfriendly.jsp?BV_UseBVCookie=yes&getPagePath=18416).
My design basically implements a custom MCU with code/data in BRAM, and
an audio processing structure --which is actually the section I am
interested in reconfiguring dynamically-- consisting of a bunch of
filters that use SP-3 embedded multipliers, some accumulators and
distributed RAM. I also prepared my design for partial reconfiguration
following the information available in Application Note #290
(http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf).

 To carry out the reconfiguration process, my board exports some FPGA
IOs to the external configuration interface and then these are
controlled by the custom embedded MCU running inside the same FPGA
(http://www.nongnu.org/s430/). The difference bitstream is read by the
MCU from an external memory card. However when it attempts to perform
the reconfiguration weird things happen. Most of the time the boards
just freezes and sometimes the chip turns really hot (which reminds me
that I am literally playing with fire here :P ).

 I have never been able to successfully reconfigure the device using
this method. Perhaps, as the answer record points out, this has
something to do with the unmodified bits resetting during
reconfiguration. Are there any other procedures or gotchas I am not
aware of? The method to break down the design for partial
re-configuration is really cumbersome and I may be doing several
mistakes there. Is there a way to instruct ISE to break the design
automatically?

 Also, does somebody know if there is an update on the status of the
hidden ICAP of the SP-3? Is this actually usable? I recall reading in a
previous post some months ago that someone at Xilinx (Austin Lesea?)
was going to find out if there was a way to make it work.

 The whole idea of my project is to use partial-reconfiguration to
support many types of audio filters (this is an audio effects
processor). Maybe it is going to be much better to ditch my current
SP-3 design in favor of a Virtex one that supports modular blocks. Am I
right?

 Best regards.

--
PabloBleyerKocik /
pbleyer         /"Reliable software must kill people reliably."
@embedded.cl   / -- Andy Mickel


Article: 79699
Subject: FPGA : file generation
From: santhosh <nsanthosh@techemail.com>
Date: Wed, 23 Feb 2005 06:54:45 -0800
Links: << >>  << T >>  << A >>
Getting unwanted zeroes generated in the coe file....Any one guess what can be the reason?



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