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Hi all again,
if i see this in the system.vhd:
-- Internal signals
.
.
.
.
. signal gpio_top_0_wb_dat_i : std_logic_vector(31 downto 0);
.
.
.
gpio_top_0 : gpio_top_0_wrapper
port map (
wb_clk_i => net_gnd0,
wb_rst_i => net_gnd0,
wb_cyc_i => net_gnd0,
wb_adr_i => net_gnd8(0 to 7),
wb_dat_i => gpio_top_0_wb_dat_i,
wb_sel_i => net_gnd4(0 to 3),
wb_we_i => net_gnd0,
wb_stb_i => net_gnd0,
wb_dat_o => open,
wb_ack_o => open,
wb_err_o => open,
wb_inta_o => open,
aux_i => net_gnd31,
ext_pad_i => net_gnd31,
clk_pad_i => net_gnd0,
ext_pad_o => open,
ext_padoe_o => open
);
opb2wb_0 : opb2wb_0_wrapper
port map (
OPB_Clk => sys_clk_s,
rst => mb_opb_OPB_Rst,
opb_abus => mb_opb_OPB_ABus,
opb_be => mb_opb_OPB_BE,
opb_dbus => mb_opb_OPB_DBus,
opb_rnw => mb_opb_OPB_RNW,
opb_select => mb_opb_OPB_select,
opb_seqaddr => mb_opb_OPB_seqAddr,
sl_dbus => mb_opb_Sl_DBus(192 to 223),
sl_errack => mb_opb_Sl_errAck(6),
sl_retry => mb_opb_Sl_retry(6),
sl_toutsup => mb_opb_Sl_toutSup(6),
sl_xferack => mb_opb_Sl_xferAck(6),
wb_data_o => gpio_top_0_wb_dat_i,
wb_data_i => net_gnd32(0 to 31),
wb_addr_o => open,
wb_cyc_o => open,
wb_stb_o => open,
wb_sel_o => open,
wb_we_o => open,
wb_ack_i => net_gnd0,
wb_err_i => net_gnd0,
wb_rty_i => net_gnd0
);
is opb2wb_0->wb_data_o and gpio_top_0->wb_dat_i connected together ?
if yes i thing i have found a way to connect easily both signal :)
regards
Jonathan
"Jonathan Dumaresq" <jdumaresq@cimeq.qc.ca_nospam> a écrit dans le message
de news: Sh6Rd.30695$6f.30228@charlie.risq.qc.ca...
>
> "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> a écrit dans le
> message de news: 42125d33$0$311$ba620e4c@news.skynet.be...
>> Jonathan Dumaresq wrote:
>>> yes i con buit it too..
>>>
>>>
>>> When I look at the system.pbd, I expected to to see a new bus for the
>>> wb. But i did'nt see it. I don't know if we need to see it or not.
>>
>> No you won't see a new bus. This wrapper just export all wishbone bus
>> signals as port. Then you need to connect them manually.
>
> How can i connect them manualy ?
>
> regards
>
> Jonathan
>
>>
>>
>>> But i see that the wrapper is connected to the opb bus as a slave.
>>
>> Yes, the opb2wb wrapper translate OPB access to WishBone access. So it's
>> an OPB Slave and a WishBone master.
>>
>>> The other question that i have is how to built a edk-core compatible
>>> with verilog file ?
>>>
>>> As i can see ther is only the vhdl file that can be use to make an edk
>>> core compitible.
>>>
>>> so if anyone have any idea of what we have to do to plug a simple
>>> wishbone GPIO connected to opbbus via the wrapper....
>>
>> Just use the wizard and you can use a verilog design. But AFAIK, you
>> can't
>> easily use a mixed verilog/vhdl ...
>>
>>
>> Sylvain
>
>
Article: 79351"SD" <sourabh.dhir@gmail.com> schrieb im Newsbeitrag news:1108668502.344775.89450@c13g2000cwb.googlegroups.com... > adders, subtractors etc etc). My question is whats the best way to find > out the exact delay using free Xilinx WebPack? the synthesis report > does give me a max combination path delay, is that what I should be > looking at? Sythesis reoprt is just a rough estimate, often ways wrong. What you need is the timing report after Place & Route. If you set some timing constrainst in your UCF, the timing analyzer will check those and write out a report if the deign meets your requirement or not. A simple timing constaint is NET my_clock period = 10ns; This tells the timing analyzer checks if the logic between your FlipFlops need less than 10 ns propagation delay (including clock2out and setup times). There are much more timing constraints, but this is getting more complex. Regards FalkArticle: 79352
Confluence 0.10.3 includes the initial FNF C model generator.
http://www.confluent.org
The resulting C code is significantly different than that produced by
the pre-FNF generator. For now, there is no VCD, testbench, or piped
simulation interface support.
Some new features:
- New simulator data structure.
- Constructor and destructor functions.
- Init and calculation functions.
- Enables running multiple simulation models at once.
- Provides access to all named signals in a design:
debug = sim.signals.top_level.subsystem1.output2;
- Transition level modeling.
- Calculates values for each transition, not just per clock cycle.
- Built-in FNF primitive functions.
Confluence 0.10.3 includes the Icarus Verilog FNF generator, providing
a path from Verilog to C (not to mention VHDL, NuSMV, and JHDL).
Aside from compilation, the C model generator has not undergone
extensive testing. Bug feedback is appreciated. A code review of the
FNF primitive functions would especially be helpful:
$ fnf -read_fnf out.fnf -write_c out # See out.c for FNF primitives.
Confluence and FNF support for black-boxes, timing constraints,
properties, and SystemC generation are next on the list.
http://www.confluent.org/wiki/doku.php?id=wishlist
-Tom
Article: 79353>>> >>>When I look at the system.pbd, I expected to to see a new bus for the wb. >>>But i did'nt see it. I don't know if we need to see it or not. >> >>No you won't see a new bus. This wrapper just export all wishbone bus >>signals as port. Then you need to connect them manually. > > > How can i connect them manualy ? Use the "Port" tab in the "add/edit cores" dialog windows like what you use to connect clock & reset signals together ... Connect all signals like "wb_stb_i" to the "wb_stb_o" of the other core, pretty easy ... SylvainArticle: 79354
I have only tested my master pcore with a PLB BRAM in simulation and then in hardware (ML 310 with V2P30). I'm planning to migrate to using the PLB DDR (256 MB DDR mem that comes with the board). What kind of board/hardware are you using? Unfortunately, I do not have experience with the retry issue you are having. I imagine you re-issue the request, using the same parameters, but you have already tried that. Any one else with experience with this issue? NN At 11:25 PM 2/17/2005 +0530, Kumar wrote: Hi , Thanks for replying, i really appreciate..yeah i will go thru the thread.. mean while i will probably explain u in detail.... I am desinging an master interface for PLB for EDK 6.3i (exactly for what u had done) and i tried edk simulation with BRAM, then my transaction went thru smoothly(ie no retry(rearbitrate) from slave).... but the moment i tried with SDRAM as my externl memory i get an Sl-rearbitrate from the slave and the PLB arbiter de-asserts the PLB_PAValid signal immedielty afetr seeing Sl_rearbitrate @ the pos edge of the clk.... then after that my master kept on requesting for the same address for which it didn't get an addr ack and got the retry(rearbitrate).... but the arbiter doesn't arbitrate at all after that(seems like).. and that PLB_PAValid signal is not going high at all......so i cldn't proceed my transaction after that.....hope i am making sense to you...Please i would really appreciate if you could help me out in this.i am really stuck on this.......i tried all possiblities from the master side(like de-asseting and asserting the request again , nad later after some clock....but :-( no response from the arbiter.....) Looking fwd for you answer... thanx , Mack. On Thu, 17 Feb 2005, Nju Njoroge wrote: > Hi, > > I had designed a simple PLB master and posted some questions on the news > group. The thread message was titled "Designing a simple PLB Master using > EDK 6.3i". The last message in the thread was 2/1/2005. Read it is to see > if it helps in general (refer to the PLB PDF document that I referenced in > the thread). > > Addressing your specific question, I have never dealt with the problem you > are dealing with. Is the slave asking you to "retry" the request again? > > All the best, > > NN > On 16 Feb 2005 mmkumar@gmail.com wrote: > > > Hi, > > I am desging an master interface for 64-bit PLB.when i am not locking > > the bus and if i get a Mn_rearbitrate from the slave ,and am > > de-asserting and asserting the request after one clk.But it seems like > > the arbiter is not arbitrating the request from the me(master) after it > > got an M1_rearbitrate(never i get the bus , after that), how i can i > > proceed further to do my data transfer. > > > > thanx, > > mack. > > > > > > > >Article: 79355
>From a Xilinx Engineer: When you instantiate only a FIFO and run the design through PAR, then perform a back-annotated timing simulation with an SDF file, I have found that often time the critical path in the design is from input pad to flop, or output flop to pad, not flop to flop within the FIFO. If you apply a period constraint of 50MHz, that will only cover register to register paths, not from the input pad to flop, or output flop to pad. In order to cover these paths, you should add additional OFFSET IN/OUT constraints. If you include these constraints and all constraints are met, then setting your timing simulation period to 50MHz and applying clock setup/hold times as stated in the timing report, your timing simulation should work. I don't know if this is what you are running into or not, but I have seen this cause problems with timing simulations of a stand-alone core (outside of a user design). For more information on applying OFFSET IN/OUT constraints, refer to support.xilinx.com: http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/cgd/cgd0145_98.htmlArticle: 79356
Hello Group, Thank you all for the help with my last question. I have another issue with the Behaviour vs. PAR models as it relates to FIFOs. I find that in the behavior model the read cycle looks as if it takes two clock cycles to get new data and in the PAR model the data comes more readily, around 11ns, about half a cycle. I suspect that the Behavior model might be two cycles delay since the Read_Enable sets up on a rising edge of a clock. However the read cycle does not initiate until one cycle later, when the Read_Enable is high, albeit going low. And then there is one more clock delay in the read output. If I were modeling this on the top level I would delay my clock a tad, so the read enable was already set up, and then the output would come one cycle later, not two. Unfortunetely, this is an instantiated component in a lower level, wherein the read enable is generated by the same clock that runs the FIFO. I guess this is the problem of infinitely fine timing units called deltas? It would be an ugly and time consuming process to run everything through the PAR and post sim. I suppose I could run a separate clock, down the hierarchy to run just the FIFO, for simulation purposes. But I am hoping that this group knows a better solution. Thanks, Brad Smallridge b r a d @ a i v i s i o n . c o mArticle: 79357
Hello, I'm trying to disable "Critical-word first" loads for cache loads. That is, when the cache is performing a cache refill, it first loads the target data from memory, then loads the remaining words in the cacheline from memory--all as part of a burst transaction. I'm looking for a way to disable this type of cache fill. Instead, I would like the cache to load the cacheline starting from the base address of the cacheline. Any one tried this before? The reference guide claims that the PLB memory controller can send back the data in the order it desires (http://www.xilinx.com/bvdocs/userguides/ppc_ref_guide.pdf, page 146). However, in reality, when my PLB slave pcore sends back the data in order of ascending addresses, the processor assumes that I sent it back the target data first, so it uses the wrong word. Thanks, NNArticle: 79358
I think it would be GREAT having a C compiler for it !! Good work Ahmed Abdel HamidArticle: 79359
I want it to sample these data coming in and then store the data to different bins, i.e. there are data somewhere from 0 to 255 going into the FPGA, the FPGA reads this data and increase the bin count, for example, the FPGA sees 3 coming in, so bin3 count= 1, then a 10 comes in, bin10 count = 1, then 3 comes in, so bin3 count = 2, etc....Article: 79360
Hi everyone, My program is supposed to loop and loop until an error occur, then it supposed to stop. Is there a way to do this in Verilog and Spartan3? I want to be able to get a message pop up on the PC when this error occurs also. Is it possible to do this with JTAG? Or is there another way? Thanks, AnnArticle: 79361
AL wrote: > Hi everyone, My program is supposed to loop and loop until an error occur, > then it supposed to stop. Is there a way to do this in Verilog and Spartan3? > I want to be able to get a message pop up on the PC when this > error occurs also. > Is it possible to do this with JTAG? Or is there another way? Verilog describes logic, and it is possible to make logic to do that. You can use a counter, for example. AL also wrote: > I want it to sample these data coming in and then store the > data to different bins, i.e. there are data somewhere from 0 > to 255 going into the FPGA, the FPGA reads this data and > increase the bin count, for example, the FPGA sees 3 coming > in, so bin3 count= 1, then a 10 comes in, bin10 count = 1, > then 3 comes in, so bin3 count = 2, etc.... This is the property of RAM, which is easy to write in verilog, it looks pretty much like a C array. Don't forget to clear it before writing to it. To increase the count you will need to read it, increment it, and write it, most likely in separate clock cycles (clock edges if you are really lucky). Good luck! -- glenArticle: 79362
Hi Has someone experience in using the OSERDES in combination with a commercial Deserializers like MAX9206/MAX9208 or SCAN921226 ? I was wondering whether it would be possible to meet the jitter requirements and thereby preventing that the deserializer's PLL unlocks. I can' find the right information for this in the Virtex-4 DC and Switching Characteristics. To generate e.g. 500Mb/s one needs to use a (500*12/10) / 2 MHz = 300MHz clock for the OSERDES. The OSERDES will use both edges of the clock to generate data in DDR mode. This will introduce some jitter and using a DCM with a multiplication factor of 5x for "CLK" will worsen the situation a lot. I guess it will be hard to prove the stability by means of static timing analysis. Further, the OSERDES is not capable to generate packages of 12 bits that are required for most deserializers (1 start + 10 data + 1 stop bit). Probably this can be solved by some reshuffle module. Finally, will the OSERDES width expansion run slower than one without? I couldn't find this information. RoelArticle: 79363
Here are the answers from our spreadsheet: Assuming 70% device utilization (which has an impact on jitter) and a -11 speedgrade, a 100 MHz clock multiplied by 3, divided by 1 in FX mode generates a jitter of 29% or 987 ps. Duty-cycle distortion is a non-issue in Virtex-4, where it is very small. I do not have data for the jitter toleance of your receiving SERDESes. Peter Alfke, Xilinx ApplicationsArticle: 79364
I forgot: To send out 12 bits, you can send two successive words of 6 bits each. Peter AlfkeArticle: 79365
Nevin wrote:
>We are experiencing problems with our VirtexII FPGA. Preliminary
>debugging indicates that it may be bad hardware. We want to verify that
>the cells in the FPGA are good. Is there any kind of diagnostic tool
>available to scan FPGA and verify hardware integrity? Thanks in
>advance,
>
>
>
Talk to xilinx. They test the cells before shipping, although it is
possible a fault might have made it out undetected, in which case they
will be VERY interested in knowing what the fault is as well as how to
detect it. It is extremely rare for a cell to go bad later, but again
there is a possibility. Generally speaking, if the FPGA does have a
hard failure, it is usually going to occur on an I/O that got
overstressed (often by ESD). What are the symptoms that lead you to
believe it is a hardware fault?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 79366Nju, PLBC405DCURDWDADDR[1:3] must be driven to the PPC in the order in which you deliver the data. See the PPC processor block manual for more detail. - Peter Nju Njoroge wrote: > Hello, > > I'm trying to disable "Critical-word first" loads for cache loads. That > is, when the cache is performing a cache refill, it first loads the target > data from memory, then loads the remaining words in the cacheline from > memory--all as part of a burst transaction. I'm looking for a way to > disable this type of cache fill. Instead, I would like the cache to load > the cacheline starting from the base address of the cacheline. Any one > tried this before? The reference guide claims that the PLB memory > controller can send back the data in the order it desires > (http://www.xilinx.com/bvdocs/userguides/ppc_ref_guide.pdf, page 146). > However, in reality, when my PLB slave pcore sends back the data in order > of ascending addresses, the processor assumes that I sent it back the > target data first, so it uses the wrong word. > > Thanks, > > NN > > >Article: 79367
Mouarf wrote: > hello all, > > I've made a prototype board with an XC9572XL CPLD (3.3V). I'm currently > building a parallel programming cable version II > (?)(http://www.xilinx.com/support/programr/files/0380507.pdf) > > I wonder wether I can set Vcc to 3.3V or not since parallel port I/O are > 5V (but logic levels migth be tolerant). > > If not, is the XC9572XL device programmable with a 5V powered cable? I program XC95144XL with its own 3.3V power supply. I didn't know that I could program it with the power supplied by the cable. > > > Does anyone have the schematics of a parallel cable version III or IV? http://toolbox.xilinx.com/docsan/2_1i/data/common/jtg/fig26.htm I build one according to this schematic and it works well with XC95144XL. vax, 9000 > > Thanks for your help.Article: 79368
Hi - On 17 Feb 2005 11:17:30 -0800, "Nevin" <electrostaticman@gmail.com> wrote: >We are experiencing problems with our VirtexII FPGA. Preliminary >debugging indicates that it may be bad hardware. We want to verify that >the cells in the FPGA are good. Is there any kind of diagnostic tool >available to scan FPGA and verify hardware integrity? Thanks in >advance, If you have strong evidence of a hardware error, you may want to talk to Josh Rosen at Polybus Systems, who's done quite a bit of work on FPGA test patterns. For more, go to http://polybus.com But I agree with Ray. While I've seen I/O cells get fried (and maybe someone whose e-mail moniker is electrostaticman has seen this, too), I've rarely found internal hardware faults in FPGAs, and always make a point to look elsewhere first. Good luck, Bob Perlman Cambrian Design WorksArticle: 79369
Falk, Thanks for the input. What if my design is a pure combination logic (unregistered), I mean no clocks. So now whatever the synthesis report gives me, is it still way off the mark??Article: 79370
Hi,
I don't think you will have a problem with the binning. Assuming this is for
an ADC digital capture the calculations get a bit more complex.
For the simple bin count (histogram) using the digital reading to address a
specific counter (one of 255) and just increment the counter currently
addressed should be a quick FPGA design.
At best I think this would give you a missing codes test. For INL and DNL
you need to capture more information and sequence is important.
(monotonicity etc. are part of the typical INL/DNL test)
You may need to capture the digital codes to memory and depending on the
input signal (different methods could use a ramp, sine, or other input
signal) processes the result. If the input is a ramp from a DAC then there
is a fair amount of work to interpolate the DAC steps vs the ADC reading to
get a good INL/DNL result (minimize the quantization error.)
Have fun,
Bart
On Thu, 17 Feb 2005 15:45:38 -0800, AL wrote:
>
>
>I want it to sample these data coming in and then store the data to different bins, i.e. there are data somewhere from 0 to 255 going into the FPGA, the FPGA reads this data and increase the bin count, for example, the FPGA sees 3 coming in, so bin3 count= 1, then a 10 comes in, bin10 count = 1, then 3 comes in, so bin3 count = 2, etc....
Article: 79371Hi , Thanx.Yeah I am trying for ML310 xc2vp30 .but before taking to the board i tried some edk simulation with SDRAM ...and got that problem..if any one understood my problem, help me out in this... regards, Mack. Nju Njoroge wrote: > Hi, > > I had designed a simple PLB master and posted some questions on the news > group. The thread message was titled "Designing a simple PLB Master using > EDK 6.3i". The last message in the thread was 2/1/2005. Read it is to see > if it helps in general (refer to the PLB PDF document that I referenced in > the thread). > > Addressing your specific question, I have never dealt with the problem you > are dealing with. Is the slave asking you to "retry" the request again? > > All the best, > > NN > On 16 Feb 2005 mmkumar@gmail.com wrote: > > > Hi, > > I am desging an master interface for 64-bit PLB.when i am not locking > > the bus and if i get a Mn_rearbitrate from the slave ,and am > > de-asserting and asserting the request after one clk.But it seems like > > the arbiter is not arbitrating the request from the me(master) after it > > got an M1_rearbitrate(never i get the bus , after that), how i can i > > proceed further to do my data transfer. > > > > thanx, > > mack. > > > >Article: 79372
Jon Beniston wrote: >>so it seems that EDK tool chain does not have pthread library and >>header file. > > No. > >>How can we fix this problem ? Anyone have experience on this? > > You will have to port pthreads to microblaze. I'm not sure pthreads is > really the most approriate threading library for MB though. pthreads work under uClinux on microblaze. The pthreads demo apps compile and run in a reasonably sane manner, though I've never tested any significant larges apps with it. JohnArticle: 79373
Hi, I'm trying to print a waveform from ChipScope Pro 6.3 under Windows. I have a waveform window open, and a printer selected, however when I try to select the "Print" option from the File menu, nothing happens. It's quite strange - after the mouse hovers on the "Print" menu item for about a quarter of a second, a small gray square (maybe 3x3 pixels?) appears next to it. No amount of clicking can cause the Print wizard to launch. Anyone seen this and know a workaround? Thanks, JohnArticle: 79374
Hey, Have you just tested the BRAM version in hardware? Try doing this first. After you get rid of the kinks for the PLB BRAM in hardware, then replace it with it with the PLB DDR version. *Theoretically*, you should be able exchange the pcores and it should work in hardware. Reading/Writing to the PLB DDR should be the same as PLB BRAM because the slave pcore controller is supposed to abstract away the memory type you are using. (Make sure the UCF file is set-up properly for the DDR--you can do this quickly with Base System Builder by creating a new project.) Good luck, NN On 17 Feb 2005 mmkumar@gmail.com wrote: > Hi , > Thanx.Yeah I am trying for ML310 xc2vp30 .but before taking to the > board i tried some edk simulation with SDRAM ...and got that > problem..if any one understood my problem, help me out in this... > > regards, > Mack. > Nju Njoroge wrote: > > Hi, > > > > I had designed a simple PLB master and posted some questions on the > news > > group. The thread message was titled "Designing a simple PLB Master > using > > EDK 6.3i". The last message in the thread was 2/1/2005. Read it is to > see > > if it helps in general (refer to the PLB PDF document that I > referenced in > > the thread). > > > > Addressing your specific question, I have never dealt with the > problem you > > are dealing with. Is the slave asking you to "retry" the request > again? > > > > All the best, > > > > NN > > On 16 Feb 2005 mmkumar@gmail.com wrote: > > > > > Hi, > > > I am desging an master interface for 64-bit PLB.when i am not > locking > > > the bus and if i get a Mn_rearbitrate from the slave ,and am > > > de-asserting and asserting the request after one clk.But it seems > like > > > the arbiter is not arbitrating the request from the me(master) > after it > > > got an M1_rearbitrate(never i get the bus , after that), how i can > i > > > proceed further to do my data transfer. > > > > > > thanx, > > > mack. > > > > > > > >
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