Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 78275

Article: 78275
Subject: Re: XC4005-6PQ160C datasheet
From: Greg Neff <greg@nospam.com>
Date: Thu, 27 Jan 2005 18:19:39 -0500
Links: << >>  << T >>  << A >>
On 27 Jan 2005 13:11:24 -0800, si.ci@seznam.cz (SimonX) wrote:

>Has anybody datasheet of XC4005-6PQ160C or XC4000 seria? Thanks for
>link or sending ... Simon (c-aza@c-mail.cz)

Today is your lucky day.  I just happened to have a Xilinx CD from
1995 with these:

www.microsym.com/XC4000.PDF 
www.microsym.com/XC4000FM.PDF 

Enjoy.

================================

Greg Neff
VP Engineering
*Microsym* Computers Inc.
greg@guesswhichwordgoeshere.com

Article: 78276
Subject: Problem with XSysAce_SectorRead
From: "Newman" <newman5382@yahoo.com>
Date: 27 Jan 2005 15:53:22 -0800
Links: << >>  << T >>  << A >>
I've got an V2PRO and sysace adpater from Memec.  I got it so the
SysAce Board configures the V2PRO board.  The software code Does

XSysAce_Initialize   ... // returns OK
XSysAce_SelfTest     ... // returns OK
XSysAce_Lock         ... // returns OK

-- bit 8 Ready for CompactFlash controller command
ACE Status Reg Read 0x00150392

-- MPULBAREG
Write   0x00000000

-- SECCNTCMDREG
Write   0x0301

-- DATABUFREG
Read 32 Buffers of data

The problem is that I cannot seem to get the CompactFlash controller
reg bit 8 to go ready again. It stays at 0x003502B2.

I tried to keep reading the data even after I thought I read it all in
the hopes that the the status bit would go ready with no change
observed.

Any suggestions on what I am missing would be appreciated.
-Newman


Article: 78277
Subject: Re: EPCS binary files...
From: "Jeroen" <jayjay.1974@xs4all.nl>
Date: Fri, 28 Jan 2005 01:47:17 +0100
Links: << >>  << T >>  << A >>

"Jedi" <me@aol.com> wrote in message news:Ws7Kd.265$zi5.261@read3.inet.fi...
> Jedi wrote:
> > Hello..
> >
> >
> > Is there a tool which can generate binary files for EPCS memories?
> >
> > Quartus programmer doesn't generate them...only on-the-fly when
> > programming EPCS or compatible devices...
> >
> >
> > rick
> >
>
> Stupid me (o;
>
>
> It's just .rpd file bit-reversed (o;
>

Under 'File->Convert programming files' you can generate all kinds of files.

Jeroen



Article: 78278
Subject: Rocket I/O + Optical Fiber
From: Quiet Desperation <nospam@nospam.com>
Date: Thu, 27 Jan 2005 17:05:26 -0800
Links: << >>  << T >>  << A >>
Any good info locations online about simply tying Rocket I/O to an
optical transmitter and receiver? I'm looking to do near 10 Gbps. We do
a lot of stuff at my work that requires transferring lots of data from
one box to the next. I'm thinking Aurora or maybe just the generic
core. It's Virtex Pro X to Virtex Pro X in a closed system so I don't
need any particular protocol.

The Xilinx site has lots of nice info, but they seem to be rather
obsessed about backplane applications. My needs are more point to point
between units mounted in a rack using optical fiber. There's a mention
here and there on the site, but I can't find anything meaty, like an
App Note.

I'm looking for info on recommended optical devices, PWB trace design
between the FPGA and the optical device, and other point to point
application info.

Article: 78279
Subject: Xilinx ISE 6.3i compxlib freeze
From: "Dan" <steuben@gmail.com>
Date: 27 Jan 2005 17:28:22 -0800
Links: << >>  << T >>  << A >>
I'm trying to compile the simulation libraries and I have a big
problem: compxlib causes my computer to freeze in the middle of the
compilation. Some background:

Windows XP service pack 2
Xilinx ISE 6.3.03i
Xilinx EDK 6.3.02i
ModelSim SE 6.0b

The problem occurs both when I try to compile the simulation libraries
from the command line (compxlib -s mti_se -f all -l all) and from the
ISE interface.

Has anyone else encountered this problem? I haven't been able to find
any good answers on the Xilinx support site and before I open a tech
support call, I was curious if any of you have seen this problem -- and
fixed it -- before.

Regards,
Dan

--
Daniel Alex Finkelstein
Graduate Research Fellow
Computer & Information Science
Polytechnic University
5 MetroTech Center
Brooklyn, NY 11201
tel: 718-260-3378
fax: 718-260-3609
url: http://pages.poly.edu/~dfinke01


Article: 78280
Subject: See Peter's High-Wire Act next Tuesday
From: "Peter Alfke" <peter@xilinx.com>
Date: 27 Jan 2005 17:50:46 -0800
Links: << >>  << T >>  << A >>


If you click on

http://seminar2.techonline.com/s/xilinx_feb0105

and register for the Feb.1 Xilinx TechOnLine, then you can witness my
presentation about Virtex-4 performance. It's a daring high-wire act
between engineering and marketing. Wish me luck!

The time is Tuesday, Feb 1, noon to 1 pm Pacific time.
It would be nice to feel that I can count on some friends in the
invisible audience.

Peter Alfke, Xilinx Applications


Article: 78281
Subject: EDK 6.3 Eval with Spartan 3 Starter Kit
From: "newman5382" <newman5382@yahoo.com>
Date: Fri, 28 Jan 2005 02:21:04 GMT
Links: << >>  << T >>  << A >>
Does anybody know what the limitations are with the EDK 6.3 Evaluations 
software that comes with the Xilinx Spartan III Starter Kit DO-SPAR3-DK.

- Newman 



Article: 78282
Subject: Re: See Peter's High-Wire Act next Tuesday
From: "Bob" <nimby1_notspamm_@earthlink.net>
Date: Fri, 28 Jan 2005 03:40:34 GMT
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> wrote in message
news:1106877046.479990.51180@z14g2000cwz.googlegroups.com...
>
>
> If you click on
>
> http://seminar2.techonline.com/s/xilinx_feb0105
>
> and register for the Feb.1 Xilinx TechOnLine, then you can witness my
> presentation about Virtex-4 performance. It's a daring high-wire act
> between engineering and marketing. Wish me luck!
>
> The time is Tuesday, Feb 1, noon to 1 pm Pacific time.
> It would be nice to feel that I can count on some friends in the
> invisible audience.
>
> Peter Alfke, Xilinx Applications
>

Peter,

Thanks for the heads-up.

You'll do great. And remember, we'll all be sitting behind our monitors --
NAKED!!! Thinking about this fact should relieve any potential nervousness
you will have.

Bob



Article: 78283
Subject: Re: Rocket I/O + Optical Fiber
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 28 Jan 2005 16:47:42 +1100
Links: << >>  << T >>  << A >>
On Thu, 27 Jan 2005 17:05:26 -0800, Quiet Desperation
<nospam@nospam.com> wrote:

>Any good info locations online about simply tying Rocket I/O to an
>optical transmitter and receiver? I'm looking to do near 10 Gbps. We do
>a lot of stuff at my work that requires transferring lots of data from
>one box to the next. I'm thinking Aurora or maybe just the generic
>core. It's Virtex Pro X to Virtex Pro X in a closed system so I don't
>need any particular protocol.
>
>The Xilinx site has lots of nice info, but they seem to be rather
>obsessed about backplane applications. My needs are more point to point
>between units mounted in a rack using optical fiber. There's a mention
>here and there on the site, but I can't find anything meaty, like an
>App Note.
>
>I'm looking for info on recommended optical devices, PWB trace design
>between the FPGA and the optical device, and other point to point
>application info.

Have you looked at XFP?  The parts are readily available.  The spec
includes reference PCB designs, etc.

http://www.xfpmsa.org
http://www.xfpmsa.org/XFP_SFF_INF_8077i_Rev4_0.pdf

You can get expensive 1310nm plugin optics to go a few km, or even
more expensive 1550nm plugin optics to go up to 80km.
I'm not aware of any cheap 850nm short range plugins though.
How far apart are the units in your rack?

Regards,
Allan

Article: 78284
Subject: PCI X MSI Capability (XILINX Core)
From: kedarpapte@gmail.com (Kedar P. Apte)
Date: 27 Jan 2005 23:37:20 -0800
Links: << >>  << T >>  << A >>
Hi All,
 
I am simulating a design with PCI X support (XILINX PCI X Core)
to test MSI function of the PCI x device
I am doing the following things at initialisation stage of the pci x
device
 
1. read capability pointers for MSI ID 
2. initialise PCI high and low addresses (64 bit)
3. initialise 16 bit message.
4. enable MSI in the MSI control register specifying no. of messages
in bit [6:4] of MSI control register.
 
I am facing following porblems
1. The INTA line is not getting asserted. as I am enabling MSI.
2. but no transaction is happening from the device for sending MSI
when internally the interrupt is getting asserted.
 
can anybody tell me if anything I am missing or anything is wrong.
 
Thanks in advance
Rgds
kedar

Article: 78285
Subject: Re: ProASIC§ Released
From: Luc <lb.edc@pandora.be>
Date: Fri, 28 Jan 2005 09:01:08 +0100
Links: << >>  << T >>  << A >>
No, no,

It is called XP, based on 130nm flash tech from fujitsu.
Performance-wise like the EC,and non-volatile like the ispXPGA. But
this was EČ, and therefore a lot more expensive. You can expect the XP
in the price range of the EC.

Regards,

Luc

On Thu, 27 Jan 2005 11:09:52 -0800, "Antti Lukats"
<antti@openchip.org> wrote:

>ispXPGA? those are "old" stuff it was available long time before EC/ECP was announced, I did think jg was referring something new, eg not-announced lattice product...
>
>antti


Article: 78286
Subject: Re: Cheap source for GAL's
From: "Yad" <yad1@att.net>
Date: 28 Jan 2005 00:04:15 -0800
Links: << >>  << T >>  << A >>
Contact UK- Atmel Sales; GD Technik is the local Atmel Disti in UK

Atmel offers ATF22V10C/CQ/CQZ for 5 V apps

and ATF22LV10C/CQZ for 3.3 v Apps.

These are GAL equivalent PLDs , pin compatible to Lattice.

If you can use a -15 ns Speed part in DIP package you should be able
to source these easily OR www.digikey.com

Yad


Article: 78287
Subject: Re: =?ISO-8859-1?Q?ProASIC=A7_Released?=
From: Jedi <me@aol.com>
Date: Fri, 28 Jan 2005 08:43:10 GMT
Links: << >>  << T >>  << A >>
Luc wrote:
> No, no,
> 
> It is called XP, based on 130nm flash tech from fujitsu.
> Performance-wise like the EC,and non-volatile like the ispXPGA. But
> this was EČ, and therefore a lot more expensive. You can expect the XP
> in the price range of the EC.

Actually price range will be EC + external SPI flash (o;


rick


> 
> Regards,
> 
> Luc
> 
> On Thu, 27 Jan 2005 11:09:52 -0800, "Antti Lukats"
> <antti@openchip.org> wrote:
> 
> 
>>ispXPGA? those are "old" stuff it was available long time before EC/ECP was announced, I did think jg was referring something new, eg not-announced lattice product...
>>
>>antti
> 
> 

Article: 78288
Subject: Re: Pin Sort
From: usrdr@yahoo.co.uk
Date: 28 Jan 2005 01:27:10 -0800
Links: << >>  << T >>  << A >>
I'll use Xilinx CoolRunnerII. I have got Nuhorizons CoolRunnerII
evolution board. I think CPLD is unnecessary. Because FPGA is same or
cheap price, it can take more big program from CPLD and a lot of people
use FPGA. Books tell about FPGA.
Thank for your answer


Article: 78289
Subject: Re: Copying/Reverse Engineering PAL
From: "logjam" <grant@cmosxray.com>
Date: 28 Jan 2005 02:05:16 -0800
Links: << >>  << T >>  << A >>
I setup the forum for the project.

Go to:
http://www.stockly.com/forums/index.php?

I've only added datasets for the TSM and a crazy picture, but other
than that there is not much.  Please stick around if you're interested!
I could use the company.  ;)


Article: 78290
Subject: LVDS without termination
From: Kolja Sulimma <news@sulimma.de>
Date: Fri, 28 Jan 2005 11:11:47 +0100
Links: << >>  << T >>  << A >>
Austin Lesea wrote at 2003-10-02 08:03:57 PST
"Also look at what happens when you do not have a 100 ohm termination. 
For some signals, and lengths of pcb, it may not be required." and
"If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few
signals."

I need to get 16 LVDS pairs into one edge of a Spartan-3. This is really 
  simple to layout without termination resistors and really complicated 
(with our board technology) if I add termination resistors.

Without termination the maximum signal length is 4mm. The chip driving 
the LVDS signals uses current mode output drivers.

My question now is what will happen if I try to use LVDS without 
termination? Will the current mode drivers produce a very large output 
signal swing? dangerous overshoot? (They are 3.3V powered)
We want to run data at 480 Mbps over each pair so surely reflections 
with less than 30ps roundtrip time are not that much of a problem?

If the current mode drivers require the 100R at their output, could I 
add them at the source? To get many resistors much closer than 4mm on a 
bga is difficult anyway.

Thank you in advance for your suggestions.

Kolja Sulimma

Article: 78291
Subject: Re: LVDS through connectors
From: "Ian Dedic" <ian.dedic@fme.fujitsu.com>
Date: 28 Jan 2005 02:54:26 -0800
Links: << >>  << T >>  << A >>
Ben Twijnstra wrote:
> Hi Georgi,
>
> > Any thoughs about vias on the signal traces?
>
> Avoid them as much as possible (they're major jitter sources), make
them
> blind vias or counter-bore them to make them as short as possible
> (cheaper), and make sure that the signal path goes from the top end
of the
> metal to the bottom (or the other way around). Leftover metal does
nasty
> things to the signal.
>
> See
>
>
http://www.tycoelectronics.com/products/simulation/files/papers/dc00brdh.pdf
>
> for some great information on this.
>
> Ok, you're not running at 5Gbps, but it never hurts following these
rules.
>
> Best regards,
>
>
> Ben


It all depends what your priorities are -- size, surface mount/through
hole, cost (especially if you want cables), robustness, availability...

If you don't mind using a small surface-mount connector there are
plenty around (Samtec, Mictor etc) which will do this, but they may be
difficult to get in small quantities, and if you need cables they can
be expensive and/or fragile -- and the connectors themselves won't take
a lot of stress.

We've also used standard dual-row 0.1" pitch headers/plugs with no
problem at over 1Gb/s with 100ps risetime signals (from an Agilent
81250 ParBERT); so long as you use a pin arrangement like this

GND GND
D0  D0B
GND GND
D1  D1B
GND GND

the differential impedance is close to 100ohms with negligible
crosstalk or reflections -- there's a virtual ground plane down the
centreline.

Using the back of the PCB for tracking there's also no stub/via problem
with the through-hole versions, if you shrink the internal pads on the
via hole barrel and widen the space to the ground planes you can get
the through hole connection to be about 50ohms single-ended.

Or robust surface-mount versions are also widely available if you want
to keep tracking on the top of the PCB, but you might need to cut away
the ground plane on the layer under the (wide) signal pins to reduce
capacitance and keep the 50ohms sigle-ended impedance.

The connectors are widely available, through-hole (strong, easy to
mount) or robust surface-mount, can be had polarised and/or latching,
and you can easily make up your own cables using standard
small-diameter coax with the screen split into two grounds either side
of the signal.

It might sound unlikely that you can use bog-standard 0.1" headers at
these frequencies, but it works just fine given these precautions (and
of course equalised tracking lengths for the diff pairs).

Ian


Article: 78292
Subject: MPI ? in EDK
From: "Hur" <jaeyoung_hur@yahoo.com>
Date: Fri, 28 Jan 2005 13:53:13 +0100
Links: << >>  << T >>  << A >>
hi

Is anyone aware that EDK6.3 (with Virtex II pro, ML310 board) support MPI ?

if yes please point me out which document i should start with....

thankyou



Article: 78293
Subject: Re: Rocket I/O + Optical Fiber
From: Quiet Desperation <nospam@nospam.com>
Date: Fri, 28 Jan 2005 05:17:07 -0800
Links: << >>  << T >>  << A >>
In article <qvjjv0l17f669ebnfd8avu14h67ifvtnqh@4ax.com>, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

> 
> You can get expensive 1310nm plugin optics to go a few km, or even
> more expensive 1550nm plugin optics to go up to 80km.
> I'm not aware of any cheap 850nm short range plugins though.
> How far apart are the units in your rack?

We might have up to 20 feet in some cases between different racks.
Trivial for fiber, but very spendy when it's a bundle of expensive
special order differential, delay matched cables for Gore or Meritec.

I recently did 18 differential signals in parallel at 1 Gbps
succeessfully across 10 feet (LVDS signals from a Virtex). The timing
window was 500 ps. It works great, thanks to the ability to set clock
timing in the DCM, but the cable harness is heavy and big $$$.

I can't imagine four optical components and two fiber cables costing
more. Not to mention all the mechanical design issues that go away on
the units themselves- both the connector design and PWB routing from
the I/O connector to the FPGAs. There's endless savings in parts and
labor to be had here.

We're also forced right now to colocate units we might prefer to
seperate by some distance.

Thanks for the info.

Article: 78294
Subject: Is Atmel producing Altera EPCS memories???
From: Jedi <me@aol.com>
Date: Fri, 28 Jan 2005 14:17:00 GMT
Links: << >>  << T >>  << A >>
According to a Lattice internal Atmel is the manufacturer
of the overprized Altera EPCS devices.

At least it would make sense since Atmel is not responding
to SPI flash memory requests...they just keep on forwarding
emails.

 From the technology point of view it should be either ST or
Nexflash. OTOH they send samples almost right away...
well...had to kick Nexflash several times until they do (o;


rick


Article: 78295
Subject: Re: LVDS without termination
From: "Gabor" <gabor@alacron.com>
Date: 28 Jan 2005 07:08:42 -0800
Links: << >>  << T >>  << A >>
Kolja Sulimma wrote:
> Austin Lesea wrote at 2003-10-02 08:03:57 PST
> "Also look at what happens when you do not have a 100 ohm
termination.
> For some signals, and lengths of pcb, it may not be required." and
> "If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few
> signals."
>
> I need to get 16 LVDS pairs into one edge of a Spartan-3. This is
really
>   simple to layout without termination resistors and really
complicated
> (with our board technology) if I add termination resistors.
>
> Without termination the maximum signal length is 4mm. The chip
driving
> the LVDS signals uses current mode output drivers.
>
> My question now is what will happen if I try to use LVDS without
> termination? Will the current mode drivers produce a very large
output
> signal swing? dangerous overshoot? (They are 3.3V powered)
> We want to run data at 480 Mbps over each pair so surely reflections
> with less than 30ps roundtrip time are not that much of a problem?
>
This may depend on the drivers, but what I've seen from standard quad
driver chips is that the outputs will eventually drive near the rails,
in your case 3.3V or ground.  Realize that initially the driver is
limited by its impedance and the characteristic impedance of the driven
lines even though they are not terminated.  For longer lines the
voltage
at the driver will rise in small steps separated by the round-trip
delay
time.  For short lines you'll see more of a ramp.
I wouldn't expect much overshoot due to the current limit of the
drivers,
however I would expect problems running at 480 Mbps NRZ.  You may not
have a problem with clock lines, but if data is in one state for
several
bit periods, the voltage that develops may prevent the next signal
transition from happening fast enough.
> If the current mode drivers require the 100R at their output, could I

> add them at the source? To get many resistors much closer than 4mm on
a
> bga is difficult anyway.
For short lines I would say this is a reasonable approach and will work
much better than no termination.
> 
> Thank you in advance for your suggestions.
> 
> Kolja Sulimma


Article: 78296
Subject: Re: Pin Sort
From: "Gabor" <gabor@alacron.com>
Date: 28 Jan 2005 07:13:30 -0800
Links: << >>  << T >>  << A >>

usrdr@yahoo.co.uk wrote:
> I'll use Xilinx CoolRunnerII. I have got Nuhorizons CoolRunnerII
> evolution board. I think CPLD is unnecessary. Because FPGA is same or
> cheap price, it can take more big program from CPLD and a lot of
people
> use FPGA. Books tell about FPGA.
> Thank for your answer

When you make a price comparison between CPLD and FPGA make sure
to include the configuration storage for the FPGA.  These have
come down in price lately, but can still represent a large portion
of the total cost when using a small FPGA.  Also remember that the
CPLD comes up "hot" so it can handle things like processor reset,
while an FPGA takes time to load.  Also if you decide to load the
FPGA from a processor to save the configuration memory cost, you
can't also use it to implement processor reset.


Article: 78297
Subject: Re: Rocket I/O + Optical Fiber
From: "tom" <tnbiggs@yahoo.com>
Date: 28 Jan 2005 08:59:26 -0800
Links: << >>  << T >>  << A >>
Where are you buying your cables? I find it hard to believe that the
cost of the optics + fiber is cheaper than a cable. In my experience
the cost is very much cheaper when you stay electrical, when your
distances are not very far. Why not use standard cables like those made
for Infiniband (meant for 3.125GHz)? There's also a standard for 10G
Ethernet over copper cable. There's a reason it exists: cost!

-tom

Quiet Desperation wrote:
> In article <qvjjv0l17f669ebnfd8avu14h67ifvtnqh@4ax.com>, Allan
Herriman
> <allan.herriman.hates.spam@ctam.com.au.invalid> wrote:
>
> >
> > You can get expensive 1310nm plugin optics to go a few km, or even
> > more expensive 1550nm plugin optics to go up to 80km.
> > I'm not aware of any cheap 850nm short range plugins though.
> > How far apart are the units in your rack?
>
> We might have up to 20 feet in some cases between different racks.
> Trivial for fiber, but very spendy when it's a bundle of expensive
> special order differential, delay matched cables for Gore or Meritec.
>
> I recently did 18 differential signals in parallel at 1 Gbps
> succeessfully across 10 feet (LVDS signals from a Virtex). The timing
> window was 500 ps. It works great, thanks to the ability to set clock
> timing in the DCM, but the cable harness is heavy and big $$$.
>
> I can't imagine four optical components and two fiber cables costing
> more. Not to mention all the mechanical design issues that go away on
> the units themselves- both the connector design and PWB routing from
> the I/O connector to the FPGAs. There's endless savings in parts and
> labor to be had here.
>
> We're also forced right now to colocate units we might prefer to
> seperate by some distance.
> 
> Thanks for the info.


Article: 78298
Subject: Re: LVDS without termination
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 28 Jan 2005 18:23:02 +0100
Links: << >>  << T >>  << A >>

"Gabor" <gabor@alacron.com> schrieb im Newsbeitrag
news:1106924922.935665.312220@f14g2000cwb.googlegroups.com...
> Kolja Sulimma wrote:

> > I need to get 16 LVDS pairs into one edge of a Spartan-3. This is
> really
> >   simple to layout without termination resistors and really
> complicated
> > (with our board technology) if I add termination resistors.

1st) AFAIK LVDS without termination does not work, since the outputs are
CURRENT mode, without a termination no clean output voltage.
2nd) you have Saprtan-3 which has DCI, Digital Controlled Impedance, so no
need for external termination, this can be done inside the FPGA.

Regards
Falk




Article: 78299
Subject: How do I get the contents in FPGA
From: jdy0803@hotmail.com
Date: 28 Jan 2005 10:37:40 -0800
Links: << >>  << T >>  << A >>
Hi

I have a Altera FPGA(model:ACEX).
I'd like to get all data in FPGA.
Is there any way to get all contents from that FPGA to my computer?
Can you let me know if there is a way(software or hardware tool)?
Thanks.




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search