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Pedantically you are right. Practically, three resistors and a capacitor are better. Peter AlfkeArticle: 78151
The 4VLX25 has an issue with the timing of the last bit shifted out on
TDO in that TDO tristates too early. This results in the final bit
being misread, typically as a 1. Sadly, the last bit in the device
status register is the CRC bit and this results in the the warning
message you see. This issue is detailed in the device errata
http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?BV_SessionID=@@@@1670514069.1106675756@@@@&BV_EngineID=cccfadddjhehjdfcflgcefldfhndfmo.0&category=-1210882&ipoid=24318118&iLanguageID=1
along with some possible work-arounds
Rudolf Usselmann wrote:
> Hi !
> Impact is reporting some strange errors when attempting to
> program a xc4vlx25. First I get "Error in status register
> CRC bit is NOT 0", and than during verify I get 45-52
> mismatches, seems to be different from trial to trial.
> Tried several boards, seems to be persistent ...
>
> Any ideas what might be causing that ?
>
> Oh, yes I am using Par. Cable 4, and ISI 6.3.03i.
>
> Thanks,
> rudi
> =============================================================
> Rudolf Usselmann, ASICS World Services, http://www.asics.ws
> Your Partner for IP Cores, Design, Verification and Synthesis
--
*CAUTION:* Shameless self-promotion follows...
Article: 78152On Tue, 25 Jan 2005 03:58:00 GMT, "Martin Riddle" <martinriddle@hotmail.com> wrote: >Look up the Docs for XFLOW. Xilinxs' command line utilities. I did the complete 600MB+ download but it doesn't include the proper docs. So, I did lots more downloads and eventually found XFLOW in the 'Development System Reference Guide'. It's not obvious that XFLOW gives you anything over rolling your own makefile, so I stuck with what I know. Anyway, I got the 'watchvhd' example through the flow to a bit file, and the short answers are: >"Rick Thompson" <nospam@nospam.com> wrote in message news:tshav0hht1185ajvg9pfja9kottbdct7p5@4ax.com... >> Hi all - >> >> I'm just doing my first device (a Spartan 3S200 or 400) after a break >> of 5 years, and I'd like to do a scripted flow (I've done this >> previously with 4K&Virtex/Leonardo/Foundation, running >> par/map/ngdbuild/etc from a makefile). Can anyone tell me if this is >> possible with the free Webpack tools, yes >>or will I have to buy something? no >> Is the free XST scriptable? yes >>Is XST any good? Haven't compared it with anything else, but it looks pretty professional. Also appears to have good language support. >> >> Finally, any ideas on whether the flow has changed radically since >> 2000, or should I just be able to take up where I left off? All pretty much the same - ngdanno and ngd2vhdl have been replaced with netgen, and a few minor changes to options in ngdbuild and par, but that's about it. >> >> Cheers - >> >> Rick >> >Article: 78153
Let me give a more generic answer about ES. "Engineering Samples" is really an inappropriate name, I would call it "Early Silicon" :-) The devices are thoroughly tested and perform according to the data sheet, as amended by an errate sheet. By definition, ES parts have an errate sheet (at best it says:"NO ERRATA") We call them ES because some long-term reliability qualification tests have not yet been completed. We might also have to change some masks to fix the errata problem(s). We therefore suggest that ES parts not be used in your final manufacturing. But any idea that ES parts are flakey, not completely tested, or unreliable is dead WRONG. Hope that helps. Peter Alfke, Xilinx ApplicationsArticle: 78154
> My local professional supplier (RS) still sell the PLCC68 68HC000 but in > tubes of 18. > Maybe it isn't obsolete as I thought? > Works out about =A311 each for the 16 MHz, or =A36 for the 8 MHz chips. Digikey sells the things for about $12 in quantities of 1. Are you in the US? > > > Tuesday I will be decapsulating/delidding/decapping the chips and > > photographing them with my digital camera. > > Perhaps you could borrow one of those USB camera microscopes for the job. I'm not crazy! ;) The microscope in the metallurgy lab has a high resolution video camera and a photograph lens ring attachment on it. ;) The pictures will be taken at full power magnification. > > > the same on the silicon layer as they do on the datasheet. > > At some point you will have to recreate the logic equations, and will have > to figure out how the 68K works. I'd read the app notes first and you may be > able to make a good start. I'm sure I could, but for some reason I have a drive to make it as NOS as possible. Never did understand those Model-T guys until now. ;) Just got the 512k board, getting ready to cut the PALs off. :)Article: 78155
> SCSI is dead. Do an IDE interface instead. > > Floppies are disappearing from modern machines. > Do an SD card interface instead. But in order to boot the mac a 5380 would have to be emulated, as well as the IWM, at least for the status register on the IWM, right? Or am Imissing something? I've got the data sheets and info on the IWM, so it can be done... I found another 512k board that has an MFM hard drive interface on it (after market), supposedly it boots. Maybe that will give me some insight.Article: 78156
I suggest a better distribution: first DCM: 16/5 second DCM: 24/25 final divider by 40 or 16/20 followed by 24/25 followed by divide by 10. Peter AlfkeArticle: 78157
I opened case for this 'out of memory' problem 3 days ago. Today one email arrived at me. It's about Xilinx Technical Support Satisfaction Survey But I did not receive any response to my case submission. Should I reopen it or wait for another response ? Or it's better to forget this case....:) regards "Davis Moore" <dmoore@RemoveTheObviousIEEEParts.org> wrote in message news:41F195F0.66AA88E4@RemoveTheObviousIEEEParts.org... > I sense confusion here... > > It appears to me that you are mixing up the address space of > your microblaze design and the address space of the computer > on which you are compiling your target design. > > Unfortunately, the error message is referring to the latter and not the > former. The computer on which you are compiling the design has run > out of memory. Try increasing your computer's memory if possible. > Some platforms have different memory limits. (Example: > WinXP usually reserves 1GB for OS and 2GB for applications.) > > Changing the address space of your microblaze design > is probably not going to get you anywhere with this problem. > > You can check http://support.xilinx.com for possible solutions. > If there are no solutions readily available to you you can open > a case with the Xilinx hotline for other possible workarounds. > > -Davis Moore > > > Hur wrote: > > > Thankyou > > > > i think you are right...possibly memory conflict......i would check BRAM > > size ....(if this is a way to check "memory conflict" --: ) > > > > by the way, in base system wizard (and microblaze reference guide), we > > can choose 8K, 16K, 32K...BRAM size... > > > > Question is that > > can we set BRAM size 12KB ? > > (base address 0000 0000 - 0000 3fff) > > > > thankyou again > > > > regards > > > > DerekSimmons@FrontierNet.net wrote: > > > I don't have experience with this platform but from the information you > > > provided, I would conclude it is a memory conflict. > > > > > > Why: The error message indicates that it could be from either an 'out > > > of memory condition' or a 'memory conflict'. You have stated that you > > > have set memory at 3 Gb. In the memory message it said that it is using > > > 1.95 Gb. Therefore I would conclude it is some kind of memory conflict > > > sense it is using less memory than you have allocated. Have you checked > > > for a conflict? > > > > > > Hur wrote: > > > > > >>dear > > >> > > >>In EDK6.3 XPS, microblaze netlist generation, > > >> > > >>Following 'out of memory' error occurred. > > >>Memory is 3GB, (sufficient enough, i think) > > >> > > >>Someone who has experience like me, how did you manage this problem? > > >> > > >>---------------------------------------------------------- > > >>ERROR:Portability:3 - This Xilinx application has run > > >>out of memory or has encountered a memory conflict. > > >>Current memory usage is 2044740 kb. Memory problems > > >>may require a simple increase in available system > > >>memory, or possibly a fix to the software or a special > > >>workaround. To troubleshoot or remedy the problem, > > >>first: Try increasing your system's RAM. > > >>Alternatively, you may try increasing your system's > > >>virtual memory or swap space. If this does not fix > > >>the problem, please try the following: Search the > > >>Answers Database at support.xilinx.com to locate > > >>information on this error message. If neither of the > > >>above resources produces an available solution, please > > >>use Web Support to open a case with Xilinx Technical > > >>Support off of support.xilinx.com. As it is likely > > >>that this may be an unforeseen problem, please be > > >>prepared to submit relevant design files if necessary. > > >> > > >>make: *** [implementation/microblaze_0_wrapper.ngc] > > >>Error 19 > > >>--------------------------------------------------------- > > >> > > >>thx > > >> > > >>regards > > > > > > >Article: 78158
Can anyone tell me what the minimum external hardware requirements are to run embedded Linux on a V2P PPC? How much (DDR/) SDRAM? 32 or 16 bits wide? How much Flash? Serial or parallel interface? Any other required I/O? Probably a serial port as a minimum, I'd imagine. Also, here's a weird one. Can two PPC's share the same SDRAM and Flash resources? My guess is that they could (with additional logic implemented in the FPGA) although it would proabably be convoluted. Thanks, -MartinArticle: 78159
I cant have 16/20 in the first, the output from a DCM must be 24 MHz or greater. I found another one that works: first DCM 32/25 second DCM: 21/25 and a last division by 14 <--- i make this with a rotating 7 bit shift register Thats it for now, thank you all :-) "Peter Alfke" <peter@xilinx.com> skrev i meddelandet news:1106677337.615112.100760@c13g2000cwb.googlegroups.com... > I suggest a better distribution: > first DCM: 16/5 > second DCM: 24/25 > final divider by 40 > or 16/20 followed by 24/25 followed by divide by 10. > > Peter Alfke >Article: 78160
Hal Murray wrote: > >I sense confusion here... > > > >It appears to me that you are mixing up the address space of > >your microblaze design and the address space of the computer > >on which you are compiling your target design. > > > >Unfortunately, the error message is referring to the latter and not the > >former. The computer on which you are compiling the design has run > >out of memory. Try increasing your computer's memory if possible. > >Some platforms have different memory limits. (Example: > >WinXP usually reserves 1GB for OS and 2GB for applications.) > > Well, I'm confused too. Why does a compiler need so much memory? > > All sorts of systems get compiled on boxes with much less memory than > 2GB. (My NetBSD/Arm box can compile it's kernel in 32 MB.) I'm sorry that I used the word "compile" in this context. :) By "compile" I mean "running the FPGA design through the ISE tools." ISE is running out of memory on his FPGA design. Either XST, NetGen, NgdBuild or some other tool in ISE is running out of memory. It is not clear to me from his post which tool it might be. -Davis MooreArticle: 78161
Pliers wrote: > Hi, I have an Optical encoder on a system. I want to double / > triple..... etc the incoming pulses. > > I want to include an ADPLL in a Altera FPGA, Currently the design is in > verilog. Does anybody have any code and an example how to use it. > > The Freq of the Altera is 20Mhz > The max freq of the encoder is 25Khz > The max Freq of output is 30Khz > > Please Help. > > Pliers > With such a massive ratio between system freq and encoder freq there is no need for a PLL. Just sample the encoder input using the system clock and add in pulses as desired.Article: 78162
> > My local professional supplier (RS) still sell the PLCC68 68HC000 but > in > > tubes of 18. > > Maybe it isn't obsolete as I thought? > > Works out about =A311 each for the 16 MHz, or =A36 for the 8 MHz chips. > > Digikey sells the things for about $12 in quantities of 1. Are you in > the US? I just noticed the =A3. ;) Anyway, if you only want one I might be able to help you out... I ordered 3 of them.Article: 78163
Martin wrote: > Can anyone tell me what the minimum external hardware requirements are to > run embedded Linux on a V2P PPC? How much (DDR/) SDRAM? 32 or 16 bits > wide? How much Flash? Serial or parallel interface? Any other required > I/O? Probably a serial port as a minimum, I'd imagine. > I would suggest starting out with someone else's board first, unless you have a whole lot of free time on your hands. I used the Avnet 2VP20 board, and it seems to work reasonably well, and is also reasonably priced. It comes with a complete Linux development environment. For what it is worth, it is using a 16MB Flash, a 32MB SDRAM, and a 2MB SRAM (Linux doesn't use the SRAM), all 32 bits wide. And it comes with both ethernet and serial interfaces, both of which work under Linux. -- My real email is akamail.com@dclark (or something like that).Article: 78164
Hi,
I'm a student of electronical engineering and developed a FPGA-board
recently (http://www-user.rhrk.uni-kl.de/~alles/fpga/). The board so far
works fine and atm I'm playing with the MicroBlaze processor a bit. But
I have a big problem to get the external SRAM (pipelined ZBT) working. I
use the opb_emc core v1.10b and configured it to the best of my
knowledge. I wrote a small C-routine (running C programs works
fine)which looks like this:
int i;
int *ptr = (int *)XPAR_GENERIC_EXTERNAL_MEMORY_MEM0_BASEADDR;
for(i=0; i <= 100; i++) {
*ptr = i*4;
ptr++;
}
I verified that the routine uses a 'sw' by disassembling the ELF-file.
Now I used ChipScope and recorded all signals related to controlling the
SRAM and to my surprise the emc-core only reads the addresses and
doesn't write them. At no time in the C-source code I read the
addresses. The core drives OE and RNW active. Can anyone explain this
behaviour to me?
Thanks a lot,
Matthias Alles
Article: 78165Symon wrote: > In that case, if the output of the 16 bit multiply is result(15 downto 0), > your output should be result(15 downto 8) incremented if result(7) is a '1'. > Truncation is usually bad; rounding is much nicer! > Cheers, Syms. > "SD" <sourabh.dhir@gmail.com> wrote in message > news:1106605358.458339.77730@c13g2000cwb.googlegroups.com... > > I plan to have it "unsigned". > > Truncation simply adds a DC offset to the signal which is not a problem if you're bandpass or highpass filtering just downstream. Although rounding gets rid of the DC offset it will add an additional adder operator with associated carry-chain resulting in increased propagation delay and LE resource utilization in your datapath. This may have an impact if your design is tight on resources or high speed. -PaulArticle: 78166
Peter Alfke wrote: > We call them ES because some long-term reliability qualification tests > have not yet been completed. And a little later... > But any idea that ES parts are flakey, not completely tested, or > unreliable is dead WRONG. Hmm... First you say that "some" ... tests have not yet been completed, and then you say "not completely tested ... is dead WRONG". I hate to quibble, but you ain't having it both ways... :-) -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 78167
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> schrieb im Newsbeitrag news:ct66gl$bgl1@xco-news.xilinx.com... > > The Freq of the Altera is 20Mhz > > The max freq of the encoder is 25Khz > > The max Freq of output is 30Khz > > > > Please Help. > > > > Pliers > > > With such a massive ratio between system freq and encoder freq there is > no need for a PLL. Just sample the encoder input using the system clock > and add in pulses as desired. ;-)) then it would be still a ADPLL. But the goal ist to have the pulses spaced as equal as possible. This reqires a ADPLL. But after all, even a ADPLL is "just" a clever FSM. Regards FalkArticle: 78168
Hey guys, I am trying to install ISE 6.3i on a Gentoo distribution. I tried Fedora and couldn't get it to work either, so I'm sticking with Gentoo since I know its workings better. Anyways, when I try to install I get: isengard cdrom # ./setup -bash: ./setup: /bin/sh: bad interpreter: Permission denied I can kind of get around this by doing: isengard cdrom # bash ./setup ./setup: line 169: /mnt/cdrom/xilsetup: Permission denied ************ setup done! *************** But it returns in about 1/2 a second, so I know it's not really doing anything. It looks as if there are problems with the file permissions...but: isengard cdrom # ls -al total 5270 drwxr-xr-x 6 20230 902 2048 Dec 31 1969 . drwxr-xr-x 9 root root 240 Jan 22 11:20 .. drwxr-xr-x 3 20230 902 2048 Jul 21 2004 bin drwxr-xr-x 2 20230 902 2048 Jul 21 2004 data drwxr-xr-x 2 20230 902 6144 Jul 21 2004 idata -rwxr-xr-x 1 20230 902 3643 Jul 21 2004 setup drwxr-xr-x 4 20230 902 2048 Jul 21 2004 usenglish -rwxr-xr-x 1 20230 902 3545396 Jul 21 2004 xilsetup -rwxr-xr-x 1 20230 902 1828068 Jul 21 2004 xilxinfo -rwxr-xr-x 1 20230 902 3093 Jul 21 2004 xinfo looks like everyone has execute and read permissions. any ideas? -- brian szmyd brian.szmyd@gmail.comArticle: 78169
<scheidt@gmail.com> wrote in message news:1106686456.746751.6840@f14g2000cwb.googlegroups.com... > > Although rounding gets rid of the DC offset it will add an additional > adder operator with associated carry-chain resulting in increased > propagation delay and LE resource utilization in your datapath. This > may have an impact if your design is tight on resources or high speed. > -Paul > ...although often you can implement the additional adder by using the 'carry in' of a downstream adder. Cheers, Syms.Article: 78170
On Tue, 25 Jan 2005 14:41:32 -0700, Neiko wrote: > Hey guys, > > I am trying to install ISE 6.3i on a Gentoo distribution. I tried > Fedora and couldn't get it to work either, so I'm sticking with Gentoo > since I know its workings better. Anyways, when I try to install I get: > > isengard cdrom # ./setup > -bash: ./setup: /bin/sh: bad interpreter: Permission denied > > I can kind of get around this by doing: > > isengard cdrom # bash ./setup > ./setup: line 169: /mnt/cdrom/xilsetup: Permission denied > Have you set the LD_ASSUME_KERNEL env variable to 2.4.7? setenv LD_ASSUME_KERNEL 2.4.7 I'm running 6.3i on several distributions, Fedora Core 3 AMD64, Mandrake 10.1, and Whitebox 3.0 (RHEL 3.0), works fine on all of them.Article: 78171
Tobias, There is a goal that we must reach to call the product 'production' in terms of test coverage. So, let us say that ES might be 99.997% covered, but the goal is 99.998% (these are not the actual numbers, but are representative of the differences we are talking about). Austin Tobias Weingartner wrote: > Peter Alfke wrote: > >>We call them ES because some long-term reliability qualification tests >>have not yet been completed. > > > And a little later... > > >>But any idea that ES parts are flakey, not completely tested, or >>unreliable is dead WRONG. > > > Hmm... > > First you say that "some" ... tests have not yet been completed, and > then you say "not completely tested ... is dead WRONG". I hate to > quibble, but you ain't having it both ways... :-) >Article: 78172
Phil Tomson wrote:
>In article <b93cv0p2kvkjrfra1ajdl0vujs8apukntl@4ax.com>,
>Jonathan Bromley <jonathan.bromley@doulos.com> wrote:
>
>
>>On 24 Jan 2005 09:57:37 GMT, ptkwt@aracnet.com (Phil Tomson) wrote:
>>
>>
>>
>>
>>>I'm working on a program which will generate some VHDL or Verilog code
>>>to do some arithmetic operations. The code generated should be able to be
>>>synthesized into various FPGA families (an option to the code generating
>>>program). The function is something along the lines of:
>>>
>>> threshold= -15.0 #typically between -20.0 and -10.0 depending on problem
>>> X = vector of numbers in the range of -infinity to 0.0
>>> Y = vector of numbers in the range of -n to +n
>>> accumulator = 0
>>> foreach x in X, each y in Y
>>> if x > threshold #typically -20.0 to -10.0 depending on the problem
>>> accumulator += y*exp(x)
>>> end
>>> end
>>> answer = accumulator + bias
>>>
>>>
>>The lower limit of X sounds a little difficult to synthesise :-)
>>
>>
>
>
>
>
Rather than a straight lut for the exp function, you treat z more like
floating point and use a barrel shift
along with a LUT. First convert to base 2. e^x = 2^(x/ln(2)) by
multiplying x by the constant
1/ln(2). The product generally has an integer and fractional portion:
y= i + f. 2^(i+f)= (2^i)*(2^f)
That presents a solution then: Use a look-up table to find 2^f. The
table size is now bounded by the
precision you require in the significand. Then use a barrel shifter to
shift the result of the look up by
the number of bits indicated by the integer portion. Your circuit then,
is a constant multiply to convert
to base 2, a look-up table addressed by the fractional bits out of the
multiplier, and a barrel shift that
shifts the results of the look-up by the integer bits out of the
multiplier. You'll of course need a delay
on the integer portion to match the latency of the lookup-table.
Hope this helps you to see a solution.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 78173
Nicolas Matringe wrote:
> Moti a écrit :
>
>> Hi all,
>> My problem is more of a VHDL problem but...
>> I need to create the following pyramid alike design.
>>
>> in my declarative part i need to declare the following signals :
>>
> [...]
>
>>
>> It seems to be a job for a "generate loop" but I dont know how can I
>> declare N signals...?
>> Any suggestions for a nice and elegant way for creating such a
>> structure.
>
>
> Hi
> As far as I can see, you can't declare n signals in a concise &
> elegant way unless you declare an array (which will be twice bigger
> than what you need but should be optimized by the synthesis tool)
> I don't think "generate" is what you need.
> I would write:
> ...
> in_signal : in std_logic_vector(n-1 downto 0);
> out_signal : out std_logic_vector(n-1 downto 0);
> ...
> type bidim_array is array (n-1 downto 0, n-1 downto 0) of std_logic;
> signal reg : bidim_array;
> ...
> process (rst, clk)
> if rst = '1' then
> reg (others => others => '0'); -- not sure of the syntax here
> elsif rising_edge(clk) then
> for i in 0 to n-1 loop
> reg(i, 0) <= in_signal(i);
> if i > 0 then
> for j in 1 to i loop
> reg(i, j) <= reg(i-1, j-1);
> end loop;
> end if;
> out_signal(i) <= reg(i, i);
> end loop;
> end if;
> end process;
A possibility is to do it with a recursive call to a component, one call
for each level of the
pyramid. Your code needs an end condition in it to terminate the
recersive calls. A long
while back, I did some adder trees this way, and it broke some of the
tools (notably
Synplify). I am pretty sure the bug that caused it to break is now
fixed, although I have
not checked it in some time.
In otherwords, you use a generate on one level to generate the logic for
that level and an
instantiaton of that same component to generate the next level. The
terminating condition
instantiates a different terminating component or just avoids the call.
I'd have to dig out
some of my old code that does this.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 78174I had the same problem when I tried to run the installers from the cd. Then I copied the content of the CDs on my hard disk and the problem disappeared. I succesfully installed ISE 6.3i on a ubuntu distrib and on a gentoo distrib. General Schvantzkoph wrote: > On Tue, 25 Jan 2005 14:41:32 -0700, Neiko wrote: > > >>Hey guys, >> >>I am trying to install ISE 6.3i on a Gentoo distribution. I tried >>Fedora and couldn't get it to work either, so I'm sticking with Gentoo >>since I know its workings better. Anyways, when I try to install I get: >> >>isengard cdrom # ./setup >>-bash: ./setup: /bin/sh: bad interpreter: Permission denied >> >>I can kind of get around this by doing: >> >>isengard cdrom # bash ./setup >>./setup: line 169: /mnt/cdrom/xilsetup: Permission denied >> > > > Have you set the LD_ASSUME_KERNEL env variable to 2.4.7? > > setenv LD_ASSUME_KERNEL 2.4.7 > > I'm running 6.3i on several distributions, Fedora Core 3 AMD64, Mandrake > 10.1, and Whitebox 3.0 (RHEL 3.0), works fine on all of them. > >
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