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Brad Smallridge wrote:
> However. After generating Place and Route files, I ran the same
> waveform testbed, same vectors, and got 0 outputs. No setup
> warnings. What is wrong, or how do I find out what is wrong?
I don't use unisim, so I don't really know,
but you might start by removing the array initialization
code. There is no reason I know of to init fifo ram,
just the pointer registers.
Also consider inferring a block ram for the array:
http://groups-beta.google.com/groups?q=vhdl+fifo+ptr_type
Good luck
-- Mike Treseler
Article: 79076>Hal, I understand at the purpose behind synchronizing the reset. I am >curious to find out what goes on inside the flip-flop that does not >cause it go metastable when the d input does not change but the reset >changes. I'm far from a wizard on the insides of FFs. To get metastability, you need something like a runt pulse. You get that when 2 inputs to a gate are changing at about the same time. The simple example is an OR gate. Suppose one input turns off and another turns on a bit later. That will leave a short hole where neither input is turning the output on. If the "bit later" is long enough, you get a clean negative pulse. If it's short enough (maybe negative) you get a clean output with no changes. In between you get runt pulses. (This is easy to setup in the lab.) If the D input isn't changing, you can still get a runt pulse when the clock and the reset signal change at about the same time. That happens if reset is holding the FF in one state and the D input will change it to the other state on the next clock after reset goes away. If the D input will produce the same state as reset you don't have any problems. Most data sheets have setup/hold times for both asynchronous and synchronous resets. In the context of this discussion, an asynchronous reset is safe if you can verify that it meets the setup and hold times. That's possible if it comes from a FF clocked by the same clock. I don't know if the tools support this. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 79077
Everything is fine If the asynchronous CLEAR is being used as a synchronous input that conveniently overrides everything on the D input, and it meets the set-up and (usually 0) hold-time requirements. It's when you really have a non-synchronous CLEAR signal coming from a different clock domain or having obscure delay, then you can run into these possibly metastable situations. Metastability requires a runt pulse to initiate it, but then also a feedback circuit ( i.e. latch) that can hold the runt signal active for an indeterminate time. Luckily, in modern CMOS that time is seldom more than a few nanoseconds, but the length is non-deterministic, described only in statistical terms. XAPP094 and my postings on the TechXcusives on the Xilinx website provide more details. Peter Alfke, Xilinx ApplicationsArticle: 79078
We have finished our PPT slides and polished the presentation. It will be tutorial and technical in nature, but will also not shy away from competitive issues. I will play host, and Matt Klein will give the presentation. No accent, and hopefully no audio problems... My previous posting indicated the wrong time, it's really at 11:00 am Pacific Time this coming Tuesday, Feb 15. Hope you can join us for this and the subsequent seminars in this series. Peter Alfke, Xilinx ApplicationsArticle: 79079
Antti Lukats wrote: > Hm I already have a project for you... a bit-serial implementation of ARM > processor - it is doable, it would be working full ARM useable on small > FPGAs, sure it would run about 40 times slower than parallel ARM, but hehe a > 1MHz effective clock ARM core that is smaller than MicroBlaze or NIOS-IIe ? To the original poster: Be careful - ARM protect their IP very agressively - it's their primary revenue stream. Even student projects have been shut down, or at least removed from public access, after pressure from the legal heavies. I'm not saying it's a good thing, but that's how it is. I would think very, very carefully before taking Antti's advice on this particular project. Probably a great project from a technical perspective, but you'll also learn a lot more about legal harassment than you might prefer... Regards, JohnArticle: 79080
Like everyone say, 100MHz is trivial. If you had to go much faster there are many clever ways (depending on how you can compromise). Here are two O(1) counters: 1. Linear feedback shift register. Of course, when you really need the count the conversion back is expensive. 2. Carry-save addition. Maintain the count y as x1-x2, where x1 and x2 are two n-bit integers. To increase y, assign (in parallel) x1 <= x2 ^ ~x1; x2 <= (x2 | ~x1) << 1; This time the conversion back is cheap & trivial. For how and why this works, see page 32 of Knuth's MMIX introduction: http://www-cs-faculty.standford.edu/~knuth/mmix-doc.ps.gz I think I've seen Peter pull some really clever counter tricks (though more FPGA specific). Tommy Uwe Bonnes wrote: > Preben <64bitNOspamNO@mailme.dk> wrote: > >>Hi everyone, > > >>I would like to count very fast (100MHz) using an 19-bit counter in >>spartan 3 - any ideas how to make such a fast counter! >>One idea is to use the Chinese Remainder Theorem to count, but that >>make's a "hit-rate" of only 60% or so, if the timing is restricted. > > > Spartan 3, 100MHz and ... fast? I think you are kidding. Did you try to > implement the counter? I guess it will run much faster > > Bye >Article: 79081
"Tommy Thorn" <foobar@nowhere.void> wrote in message news:GdTPd.6680$m31.81473@typhoon.sonic.net... > > This time the conversion back is cheap & trivial. For how and why this > works, see page 32 of Knuth's MMIX introduction: > http://www-cs-faculty.standford.edu/~knuth/mmix-doc.ps.gz > I got a 401 on that.Article: 79082
Tommy Thorn wrote: > Like everyone say, 100MHz is trivial. If you had to go much faster there > are many clever ways (depending on how you can compromise). Here are > two O(1) counters: > > 1. Linear feedback shift register. Of course, when you really need the > count the conversion back is expensive. > > 2. Carry-save addition. Maintain the count y as x1-x2, where x1 and x2 > are two n-bit integers. To increase y, assign (in parallel) > > x1 <= x2 ^ ~x1; > x2 <= (x2 | ~x1) << 1; > > This time the conversion back is cheap & trivial. For how and why this > works, see page 32 of Knuth's MMIX introduction: > http://www-cs-faculty.standford.edu/~knuth/mmix-doc.ps.gz Transcriping URL's by hand and mispelling, grief: http://www-cs-faculty.stanford.edu/~knuth/mmix-doc.ps.gz Sorry. TommyArticle: 79083
Antti,
I am interested in your solution to the problem of using SATA on
V2Pro. I still don't understand how the receive takes place. Did you
use an external ckt to detect the OOB ? If not, how did you achieve
the cancellation of the repeated noise patterns ?
It would be great help if you could share the files on the
openchip server again.
Thanks
Ajith
"Antti Lukats" <antti@openchip.org> wrote in message news:<cucjbe$1c8$01$1@news.t-online.com>...
> "sg" <sgodey@gmail.com> schrieb im Newsbeitrag
> news:1107939047.041185.187330@f14g2000cwb.googlegroups.com...
> > Hi Antti,
> >
> > Can you share those tricks with the group?
>
> I think I have done that sooome time ago, but I had to reformat the HD on
> openchip server so the files are not accessible.
>
> basically there are 2 possibilities
> 1) small external circuitry, requires 1 regular IO pin from FPGA this is
> Xilinx solution, please contact Xilinx for details.
> 2) my solution, OK to use for development at least, no external hardware,
> tested with real V2Pro and real SATA chip
>
> so my trick is that use 2 MGT RX from one and TX from the other. and using
> POWERDOWN to turn of the transmitter as the powerdon on-off delay are not
> equal the SATA OOB transmit timing has the pre-adjusted to get the required
> chirp timing in the output stream. In the receive section there a specially
> developed for MGT squelch detector, thats a bit magic too as the MGT
> receiver when not seing proper inpout (eg during SATA OOB) has weird repeat
> noise pattern (repeating over 4 bits) this has to cancelled in order to
> properly and reliably detect the incomign OOB
>
> detailed enough?
>
> Antti
Article: 79084I am trying to understand the working of the multiplexed seven seg. displays on the xilinx spartan 3 board.the manual does not give me detailed info. I am trying to write a simple program where I switch a switch to the on position and it should display "0012" on the displays. Any suggestions please? thanksArticle: 79085
I really have not tried it yet, because I have not got my EDK6_3i eval CD yet, but there is a file I believe I downloaded from Xilinx : Spartan3_starter_PROM_source.zip There is a SRAM_boot/src directory where there are some C files that access the 7 segment display. -Newman . "fpgawizz" <bhaskarstays@yahoo.com> wrote in message news:d7b5335c6f1940cb248a6bbc7c1d7759@localhost.talkaboutelectronicequipment.com... >I am trying to understand the working of the multiplexed seven seg. > displays on the xilinx spartan 3 board.the manual does not give me > detailed info. I am trying to write a simple program where I switch a > switch to the on position and it should display "0012" on the displays. > Any suggestions please? > > thanks >Article: 79086
On Sun, 13 Feb 2005 18:02:25 -0800, "Pete Fraser" <pfraser@covad.net> wrote: > >"Tommy Thorn" <foobar@nowhere.void> wrote in message >news:GdTPd.6680$m31.81473@typhoon.sonic.net... > >> >> This time the conversion back is cheap & trivial. For how and why this >> works, see page 32 of Knuth's MMIX introduction: >> http://www-cs-faculty.standford.edu/~knuth/mmix-doc.ps.gz >> > >I got a 401 on that. > Just remove the extra "d" in stanford. I am curious how it got there though. I can't imagine anyone actually typing that url.Article: 79087
Can someone comment on how to display unique numbers on the seven segment display on the Xilinx spartan 3 kit? Since they have multiplexed data inputs, I need to use some kind of a clock and keep updating them constantly. Is tehre any examples out there in VHDL that I can look at to try out? thanks -VJArticle: 79088
Hi, There should be no problem with this. Just add two bram blocks and connected MicroBlaze1 and MicroBlaze2 instruction LMB buses to the first bram's two ports. Then do the same for the data LMB buses for the second bram block. This can all be done in Xilinx Platform Studio (XPS). Göran Bilski Elinore wrote: > hello > > I want to map two microblaes into FPGA. Problem is that I do not aware > that it is possible to use one LMB and one dual port BRAM for two > microblazes so that two microblazes share memory address space. Does > anyone have this experience ? >Article: 79089
On 11 Feb 2005 17:31:07 -0800, "fpgabuilder" <fpgabuilder-news@yahoo.com> wrote:
>Thanks folks.
>
>Hal, I understand at the purpose behind synchronizing the reset. I am
>curious to find out what goes on inside the flip-flop that does not
>cause it go metastable when the d input does not change but the reset
>changes.
>
>Thanks.
For a thorough discussion on metastables, you may find this entry
in the FAQ useful:
http://www.fpga-faq.com/FAQ_Pages/0017_Tell_me_about_metastables.htm
As to the details of what's going on in a flip-flop, I did a quick search
in the Patent data base. Here is a TinyURL to the result:
http://tinyurl.com/5cbgy
The first hit: 6,819,156 shows a D flop, no async reset
6,501,315 shows lots of transistor level detail, no async reset
5,410,194 shows some higher level views of how a simple D flop
with some extra logic implements other flops such as
T and JK, as well as sync and async load.
You may want to explore. Use keywords like "flip flop", asynchronous, CMOS
Philip Freidin
===================
Philip Freidin
philip.freidin@fpga-faq.com
Host for WWW.FPGA-FAQ.COM
Article: 79090Maybe you've got one of those fancy new layout keyboards, but on my QWERTY version D is next to F. Perhaps the perp pressed two adjacent keys at the same time when they meant to press just oner. Not exactly CSI is it? ;-) Cheers, Syms. "mk" <kal*@dspia.*comdelete> wrote in message news:92f011hp912jnbn8lo06sq1tu4sapga197@4ax.com... > Just remove the extra "d" in stanford. I am curious how it got there > though. I can't imagine anyone actually typing that url. >Article: 79091
Hi Murray thanks for your response, though your suggestion is interesting but my intention is different...it follows 1. I want to profile and optimize the on-chip system not the board -level. 2. One would suspect the PCI protocol to be different from on-chip protocols. 3. Furthermore, I prefer to modify the IP modules itself in later to optimze them. more or less I can achieve better optimzation in future. thats why I want to have High speed ports(USB 2.0, Firewire, Gigabyte ethernet) personlatiy modules. I know as such it is not available anywhere thats why am planning to build an extension board. If any one has done atleast part of similar work...your suggestions are admired. thanksArticle: 79092
fpgawizz wrote: > Can someone comment on how to display unique numbers on the seven segment > display on the Xilinx spartan 3 kit? Since they have multiplexed data > inputs, I need to use some kind of a clock and keep updating them > constantly. Is tehre any examples out there in VHDL that I can look at to > try out? Take a look at the demo that comes with the Spartan 3 board. http://www.digilentinc.com/Data/Products/S3BOARD/S3BOARD-demo.zip -- Juha Turunen (turunen(at)iki.fi) elpuri@IRC | The problem with the global Torikatu 5A4, 53100 Lappeenranta, Finland | village are all the global GSM: 040-7092525, http://iki.fi/turunen/ | village idiots.Article: 79093
Hi, You need to multiplex the data you want to display. In your example you want to display "0012" so you first swith on led that correspond to "0" and send to an3 "0" to swith on the first digit and 1 to an2/1/0 after you switch off an3 on put on an2 and send "0" then off an2 , on an1 and send "1" and finally off an1 on an0 and send "2" an other thing to take care is the frequency you refresh the digit segment it should not be to fast , I don't know precisely the freq but i think than 10KHz should be ok if you don't do that all digit will be light on. You can take example on this countdown that i have made and tested on the digilent board spartan3 http://kclo4.free.fr/FPGA/countdown.zip In top horloge.vhd you should find all what you need to display 0 to 9, A, B, C, D, E, F number on a 7 segment and if you only want to display "0012" juste drive: dizaine_minute <= "0000";--display 0 unite_minute <= "0000"; --display 0 dizaine_seconde <= "0001"; --display 1 unite_seconde <= "0010"; --display 2 and of course comment the other instantation of dizaine_minute.... Regards Alexis "newman5382" <newman5382@yahoo.com> a écrit dans le message de news: yxWPd.70356$JF2.53044@tornado.tampabay.rr.com... >I really have not tried it yet, because I have not got my EDK6_3i eval CD >yet, but there is a file I believe I downloaded from Xilinx : > Spartan3_starter_PROM_source.zip > > There is a SRAM_boot/src directory where there are some C files that > access the 7 segment display. > > -Newman > . > "fpgawizz" <bhaskarstays@yahoo.com> wrote in message > news:d7b5335c6f1940cb248a6bbc7c1d7759@localhost.talkaboutelectronicequipment.com... >>I am trying to understand the working of the multiplexed seven seg. >> displays on the xilinx spartan 3 board.the manual does not give me >> detailed info. I am trying to write a simple program where I switch a >> switch to the on position and it should display "0012" on the displays. >> Any suggestions please? >> >> thanks >> > >Article: 79094
PS: the design is for a 50 MHz clock "KCL" <kclo4_NO_SPAM_@free.fr> a écrit dans le message de news: 421086c4$0$810$8fcfb975@news.wanadoo.fr... > Hi, > > You need to multiplex the data you want to display. > In your example you want to display "0012" > so you first swith on led that correspond to "0" and send to an3 "0" to > swith on the first digit and 1 to an2/1/0 > after you switch off an3 on put on an2 and send "0" > then off an2 , on an1 and send "1" > and finally off an1 on an0 and send "2" > > an other thing to take care is the frequency you refresh the digit segment > it should not be to fast , I don't know precisely the freq but i think > than 10KHz should be ok if you don't do that all digit will be light on. > > You can take example on this countdown that i have made and tested on the > digilent board spartan3 > > http://kclo4.free.fr/FPGA/countdown.zip > > In top horloge.vhd you should find all what you need to display 0 to 9, > A, B, C, D, E, F number on a 7 segment > and if you only want to display "0012" juste drive: > > dizaine_minute <= "0000";--display 0 > unite_minute <= "0000"; --display 0 > dizaine_seconde <= "0001"; --display 1 > unite_seconde <= "0010"; --display 2 > > and of course comment the other instantation of dizaine_minute.... > > Regards > > Alexis > > > "newman5382" <newman5382@yahoo.com> a écrit dans le message de news: > yxWPd.70356$JF2.53044@tornado.tampabay.rr.com... >>I really have not tried it yet, because I have not got my EDK6_3i eval CD >>yet, but there is a file I believe I downloaded from Xilinx : >> Spartan3_starter_PROM_source.zip >> >> There is a SRAM_boot/src directory where there are some C files that >> access the 7 segment display. >> >> -Newman >> . >> "fpgawizz" <bhaskarstays@yahoo.com> wrote in message >> news:d7b5335c6f1940cb248a6bbc7c1d7759@localhost.talkaboutelectronicequipment.com... >>>I am trying to understand the working of the multiplexed seven seg. >>> displays on the xilinx spartan 3 board.the manual does not give me >>> detailed info. I am trying to write a simple program where I switch a >>> switch to the on position and it should display "0012" on the displays. >>> Any suggestions please? >>> >>> thanks >>> >> >> > >Article: 79095
"Ajith" <ajith.cj@gmail.com> schrieb im Newsbeitrag news:151d7972.0502132022.5f8dcacb@posting.google.com... > Antti, > I am interested in your solution to the problem of using SATA on > V2Pro. I still don't understand how the receive takes place. Did you > use an external ckt to detect the OOB ? If not, how did you achieve > the cancellation of the repeated noise patterns ? OOB detect is sure possible without external circuitry basically COMMADETECT should assert on the chirps but we did see actual capture of OOB chirps where the COMMADETECT was not always asserted , the digital squelch solution was still working its the basic problem of detecting silence (eg open input of MGT) from non silence. open MGT input is not silence and not constant on the MGT RXDATA pins ! so some decision logic is required our work was internal was proof of concept mostly, succesful though to show that the MGT OOB is doable and does work with real SATA silicon > It would be great help if you could share the files on the > openchip server again. those files have actually never been publicly available, published was only chipscope capture around the OOB sequence, AnttiArticle: 79096
Hi Subroto, Sorry for the delay, look at the bottom. "Subroto Datta" <sdatta@altera.com> wrote in message news:1108160336.097087.219950@o13g2000cwo.googlegroups.com... > > > Hi Christos, > > We tested the altaccumulate megafunction with a size of 34 bits and > with all other settings as default, the problem mentioned was not > encountered. Would it be possible to email me the settings that were > chosen in the Megawizard that were no-default? That would help us > reproduce the problem. > > - Subroto Datta > Altera Corp. > settings: data input 35 bits result output 36 bits leave the rest as default and should give the error.. Now that I was trying to reproduce the error I found something else: I opened the altaccumulate and produced one accumulator with all default settings (8bit input/output etc..) then I double-clicked the symbol and the megawizard opens again to change settings. then I ask for 33 input, 34 output and the rest as is. When it finishes it asks to overwrite the old files, I click OK, then gives: "Symbol altaccumulate0 has changed? Do you want to update it?", I click "yes" "Selected symbol or block" I click "yes" and now I get the strange message: "Can't find the block symbol altaccumulate0 -- if the file exists it is not located in the Altera-provided or user-defined libraries." , I click "ok" the symbol does not get updated but if I double click and thus re-open the megawizard of this symbol then I find my settings to have been updated. -------------------------------- what I need for my design is an accumulator with: - 35 bit signed number input - 40 bit result - clken --------------------------------- thanks in advance, Subroto, you can mail me directly if you need more info at: christos dot zamantzas at cern dot chArticle: 79097
I want to do exactly what you do. but i'm stuck to the netlist problem. I use the wb2opb from ascic.ws and now i want to use some opencore ip to plug to my microblaze. so if you can send to this ng what you have done to make it work i'll apreciated regards Jonathan "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> a écrit dans le message de news: 420fb7ae$0$22479$ba620e4c@news.skynet.be... > Hello, > > I'm trying since yesterday to interconnect the opencore mac to a > microblaze design. > After several problems solved, I'm stuck. > > The "Generate netlist now works fine" but When I try to "Generate > bitstream", > I have three errors from NgdBuild : > > > ERROR:NgdBuild:604 - logical block 'wb2opb_0/wb2opb_0' with type 'wb2opb' > could > not be resolved. A Pin name mispelling can cause this, a missing edif or > ngc > file, or the mispelling of a type name. Symbol 'wb2opb' is not supported > in target > 'spartan 3'. > ERROR:NgdBuild:604 - logical block 'opb2wb_0/opb2wb_0' with type 'opb2wb' > could > not be resolved. A Pin name mispelling can cause this, a missing edif or > ngc > file, or the mispelling of a type name. Symbol 'opb2wb' is not supported > in target > 'spartan 3'. > ERROR:NgdBuild:604 - logical block 'wb_ethermac_0/wb_ethermac_0/maccore' > with > type 'eth_top' could not be resolved. A Pin name mispelling can cause > this, a > missing edif or ngc file, or the mispelling of a type name. Symbol > 'eth_top' is > not supported in target 'spartan 3'. > > > For the wb_ethermac core, I've created a file that includes the eth_top of > the > ethernet mac core on opencore and present the interface to the outside > world. > I've done this as a ISE project then I synthetized it to have a .ngc file > (because > I have both VHDL & Verilog there) then I created an IP from this netfile > and my vhdl top file. > > Any one has a clue on what to do ? Has anyone make this work ? (I'm using > ISE/EDK 6.3) > > > Thanks, > > SylvainArticle: 79098
Yes, in this case there is no reason to initialize the BRAM, however, I don't think that that is the reason the place and route simulation is failing. I will try later today to replace the init 0s with init 1s, and also without inits. You say you don't use unisim which seems to be the xilinx primitive library. What are you using and why?Article: 79099
hi It is good be feasible. I found that in XPS wizard we can set maximaly 64 KB for BRAM. Subsequent question is about the size. Can we make it bigger, for example 128KB or 256 KB ? Thankyou again
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