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Messages from 100475

Article: 100475
Subject: LDPC
From: "shereen.ahmed" <shereen.ahmed@gmail.com>
Date: 10 Apr 2006 06:21:37 -0700
Links: << >>  << T >>  << A >>
Dear

Any one have a resource explain in detail the Viterbi algorithm for
linear block codes


Article: 100476
Subject: Re: LDPC
From: "Antti" <Antti.Lukats@xilant.com>
Date: 10 Apr 2006 06:23:57 -0700
Links: << >>  << T >>  << A >>
sure !!!

www.google.com

"LDPC tutorial"

ENTER
then click on first hit!

Antti


Article: 100477
Subject: Re: xilinx DCM Timing warning
From: "Prakash" <prakash.na@gmail.com>
Date: 10 Apr 2006 06:26:47 -0700
Links: << >>  << T >>  << A >>
thanks, thats the catch.


Article: 100478
Subject: Re: unused pins
From: "motty" <mottoblatto@yahoo.com>
Date: 10 Apr 2006 06:34:11 -0700
Links: << >>  << T >>  << A >>
You can always build it and see.  Use the floorplanner tool to see what
external pins are there.  The EDK will apparently place and route all
signals in its external port list (that makes sense).  I doubt the ISE
will route anything that is not being used.


Article: 100479
Subject: Re: unused pins
From: "Prakash" <prakash.na@gmail.com>
Date: 10 Apr 2006 06:37:17 -0700
Links: << >>  << T >>  << A >>
What I thought of unused pins is to make some state, but while
assigning package pins in ISE, in PACE, I couldnt assign nets to pins I
need. I could see only banks(bank0,1,,) not AJ15/AC4.... .  How to
assign nets to pins graphically rather UCF file.
Where Iam wrong,
Prakash


Article: 100480
Subject: Re: 8:1 MUX implementaion in XILINX and ALTERA
From: Kolja Sulimma <news@sulimma.de>
Date: Mon, 10 Apr 2006 15:40:11 +0200
Links: << >>  << T >>  << A >>
Ben Jones schrieb:
>>One more doubt i had if the depth of the multiplexer increases can the
>>LUT' s be shared.
> 
> 
> I'm not sure what you mean by that. I *think* the answer is no.

Maybe he means the width. There are indeed some optimizations that you
can do for wider muxes.
If you have an N-Bit wide M-to-1 Mux, there is a certain N for each M at
which it becomes benefitial to use first stage that outputs 0 or the
input value depending on the select value and that reduce these with an
OR-tree or the carry chain. Muxes reduce at a rate of 2-to-1 per LUT
while OR reduces at a rate of 4-to-1.

Also note that a multiplier or a BRAM can implement a MUX.

Kolja Sulimma

Article: 100481
Subject: Register Map coding style
From: "gretzteam" <david.lamb@gmail.com>
Date: 10 Apr 2006 07:13:08 -0700
Links: << >>  << T >>  << A >>
Hi,
What is the best way to code a register map in a SOC? We have something
like 15 different cores that all have a bunch of modes and flags that
are accessible through the i2c and spi port. Should you bring all those
register in a central module and use a simple read/write bus from the
i2c module? Or should you keep them in their respective module and use
a global read/write bus (then i guess you need one data bus per module
unless you tristate on chip).

Any other idea? I'm just wondering what people do in general.
Thanks,
Dave


Article: 100482
Subject: location constraint doubt
From: "Prakash" <prakash.na@gmail.com>
Date: 10 Apr 2006 07:20:47 -0700
Links: << >>  << T >>  << A >>
In one of the ucf file I could see these. I could understand the logic
element dll0 is constrained to be placed at DCM_X2Y1. I could see there
are more such DCM_X#Y#. How can I associate for my chip, means how can
I select the # for my chip. Also here dll0/1 is constrained two times.
Is it to make absolute/relative paths of them so that approprite
software can take.

INST "clkgen0_v_dll0" LOC = DCM_X2Y1;
INST "clkgen0_v_dll1" LOC = DCM_X1Y1;
INST "clkgen0/xc2v.v/dll0" LOC = DCM_X2Y1;
INST "clkgen0/xc2v.v/sd0.dll1" LOC = DCM_X1Y1;

Prakash


Article: 100483
Subject: ROM resource sharing
From: "mikel" <mikel262@gmail.com>
Date: 10 Apr 2006 07:25:57 -0700
Links: << >>  << T >>  << A >>
Hello

How to implement on-chip ROM memory resource sharing in FPGA? I
implemented discrete cosine transform core using parallel distributed
arithmetic approach, in which hardware multipliers are substituted by
precomputed MAC results stored in LUT/ROM. Single ROM instance is 64x14
bits. Problem is that the ROM must be replicated many times to enable
high throughput (replicated 9 times for first DCT stage and replicated
11 times for 2nd stage after transposition). This ends up having more
than 25kbits of ROM memory in the core, which is pretty big. I know
there are dual port memories with dual read port capability, but this
will 'only' halve resources needed. Any better ideas?

Michal


Article: 100484
Subject: Re: How to handle the high fanout
From: Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de>
Date: Mon, 10 Apr 2006 16:30:02 +0200
Links: << >>  << T >>  << A >>
hitsx@hit.edu.cn wrote:


> I implement the design using xilinx device, and one net has high
> fanout,

=> The synthesis tool gives you a hint, that using a (manually inferred) 
buffer may be not a bad idea. What buffers are available strongly 
depends on the target architecture. Sometimes the synthesis tool will 
infer such buffers automatically, if needed.

> so I duplicate the register, but it does not work, the net
> fanout remains the same.
...
> process(clk)
> begin
> if clk'event and clk = '1' then
>     regenr <= regen;
>     regenr2 <= regen;
> end if;
> 
> but the timing analyzer still reports that regenr2 has the same fanout
> as the regenr did.

regenr and regenr2 are equal for the synthesis tool.


> I am confused and I wonder whether there was some settings that should
> be modified in ISE, or I should add some constraints in UCF file to
> achieve this?

If you have a synchronous design everything should be done 
automatically, because the synthesis tool estimates the delay of the 
high-fanout net, infers the appropriate logic and reports the resulting 
clock frequency. Because of this high-fanout net the frequency may not 
be very high. (So the warning is a hint for you to search for the reason 
for the low frequency.)

Constraining the clock is the most important thing you need to do.

Ralf

Article: 100485
Subject: Re: FSL to VHDL interface
From: "Dale" <dale.prather@gmail.com>
Date: 10 Apr 2006 07:45:23 -0700
Links: << >>  << T >>  << A >>
For anyone facing the same problem, here is a nice document to clear up
a little of the confusion.  The file psf_rm.pdf which describes MPD,
MHS, MSS etc....  syntax and usage guide can be found in this
directory:   %XILINX_EDK%\doc directory.


Article: 100486
Subject: Re: xilinx JTAG
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Mon, 10 Apr 2006 15:56:10 +0100
Links: << >>  << T >>  << A >>
Prakash wrote:
> Thanks, I think that , since Iam trying to program by USB Jtag, the
> warning I got is harmless and in my case its correctly assigned
> (startupclk=jtagclk).
> I didnt get an answer for, whether I need to integrate JTAG controller
> in logic, assign the TMS, TCK...pins or controller is hard coded, and
> no need to concern in my logic (probably second is right).
yes, it's a hard block, for configuration you dont't have to do anything 
it will be there for you,
  however you can hook it to your design, if you wish, to 
triger/debug/scan different parts of your logic.

Aurash
>  
> Prakash
> 

Article: 100487
Subject: Re: ROM resource sharing
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 10 Apr 2006 15:46:28 GMT
Links: << >>  << T >>  << A >>
You have 20 different addresses for the 20 replications, correct?
Which FPGA family are you using?

"mikel" <mikel262@gmail.com> wrote in message 
news:1144679157.026889.187140@t31g2000cwb.googlegroups.com...
> Hello
>
> How to implement on-chip ROM memory resource sharing in FPGA? I
> implemented discrete cosine transform core using parallel distributed
> arithmetic approach, in which hardware multipliers are substituted by
> precomputed MAC results stored in LUT/ROM. Single ROM instance is 64x14
> bits. Problem is that the ROM must be replicated many times to enable
> high throughput (replicated 9 times for first DCT stage and replicated
> 11 times for 2nd stage after transposition). This ends up having more
> than 25kbits of ROM memory in the core, which is pretty big. I know
> there are dual port memories with dual read port capability, but this
> will 'only' halve resources needed. Any better ideas?
>
> Michal 



Article: 100488
Subject: Re: location constraint doubt
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 10 Apr 2006 16:07:36 GMT
Links: << >>  << T >>  << A >>
The only thing special about the locations of the DCMs is what clock input 
pins they are near or what partial or global clock buffers they drive.  Your 
design will often have physical constraints for pin placement which, in 
turn, drives where the logic will typically be placed.  The ins and outs of 
the DCMs in your design are best physically associated with the input pin 
and driven logic.  The device has a specific number of resources with 
explicit XY locations; you can leave it to the tool to find a decent 
solution (no LOC constraints) or make the decision based on your knowledge 
of the design.

Sometimes it's helpful to run the design without DCM LOC constraints, see if 
the results are acceptable, then copy the DCM locations for that place & 
route run into your constraints.

"Prakash" <prakash.na@gmail.com> wrote in message 
news:1144678847.133938.255900@i40g2000cwc.googlegroups.com...
> In one of the ucf file I could see these. I could understand the logic
> element dll0 is constrained to be placed at DCM_X2Y1. I could see there
> are more such DCM_X#Y#. How can I associate for my chip, means how can
> I select the # for my chip. Also here dll0/1 is constrained two times.
> Is it to make absolute/relative paths of them so that approprite
> software can take.
>
> INST "clkgen0_v_dll0" LOC = DCM_X2Y1;
> INST "clkgen0_v_dll1" LOC = DCM_X1Y1;
> INST "clkgen0/xc2v.v/dll0" LOC = DCM_X2Y1;
> INST "clkgen0/xc2v.v/sd0.dll1" LOC = DCM_X1Y1;
>
> Prakash
> 



Article: 100489
Subject: code
From: "shereen.ahmed" <shereen.ahmed@gmail.com>
Date: 10 Apr 2006 10:34:17 -0700
Links: << >>  << T >>  << A >>
Dear all

First thanks for all give me help

Second

How check independence between row and column in low parity check
matrix?

What is the advantage of use all one code word in codes?

What is the advantage of Richardson method encoding of LDPC (other than
low complexity?


Article: 100490
Subject: Very basic question
From: "Fizzy" <fpgalearner@gmail.com>
Date: 10 Apr 2006 10:40:48 -0700
Links: << >>  << T >>  << A >>
Hi,

If i have a design based on system generator and i do not have any
clock input to that do i still need clock input when i would be putting
that logic on FPGA. I know its very very nive and basic question but
need to remove some questions about clocking in FPGA. Why do we need
clock on FPGA when our design does not have any clock input.

Thanks


Article: 100491
Subject: Atmel FPSLIC
From: Adam Megacz <megacz@cs.berkeley.edu>
Date: Mon, 10 Apr 2006 10:44:14 -0700
Links: << >>  << T >>  << A >>

jetmarc@hotmail.com writes:
> Another problem I encountered was that the PAR wasn't reliable.  I
> frequently got bad bitstreams when the device utilization was high.
> The problem was probably related to the fact that the PAR tools don't
> address short paths (hold violations).

Marc, could you elaborate on this?  Typically hold violations are the
result of a path being too *long* (and, as a result, the signal has not
propagated and held by the time the clock edge arrives).

Have Atmel's tools PARed your designs in such a way that some paths
were too long for the clock rate you requested?


> I suggest you should try to implement a few real-world problems on the
> FPSLIC to learn about all the issues, before you do the compiler.

I'd be quite interested in any other wisdom you can share with us
about the FPSLIC.

  - a



Article: 100492
Subject: NTSC video capture
From: "Matt Fornero" <mfornero@gmail.com>
Date: 10 Apr 2006 11:01:42 -0700
Links: << >>  << T >>  << A >>
Hello,

I'm attempting to implement a hardware filter on an incoming video
signal (either S-video or composite) using a Xilinx V2Pro and a VDEC1
daughterboard from Digilent.

I'm attempting to test my HDL implementation, but can't seem to find a
way of simulating the video stream itself. Based on what I've read the
video will be in the formats found in ITU656 and ITU601 (NTSC). What
I'd like to do is have a file containing a digital stream in this
format, and use it in a testbench to verify my design.

The problem here is that I cannot seem to find either some method to
convert video or image files into such a stream, or an existing stream
for testing purposes. While I could (and am) write such a conversion
script myself, there is the risk that I'm misundestanding the format,
and will be testing my HDL module against an invalid data stream.


Article: 100493
Subject: Re: Very basic question
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 10 Apr 2006 18:04:27 GMT
Links: << >>  << T >>  << A >>
"Fizzy" <fpgalearner@gmail.com> wrote in message 
news:1144690848.814144.204880@t31g2000cwb.googlegroups.com...
...
> Why do we need
> clock on FPGA when our design does not have any clock input[?]

Most FPGAs step through several processes in sequence rather than being a 
simple multiple-input multiple-output combinatorial circuit.

When registers are used, they are often coordinated to be "in step" with 
each other so if two values change at roughly the same time, they are made 
to absolutely change at the same time or absolutely not change at the same 
time.

Another problem with some combinatorial logic is the glitch.  If you change 
one and only one input, you may get a glitch on a signal that ordinarily 
wouldn't change.  A change on one input can often have several paths that it 
takes to affect one output; if these paths have different delays, one path 
can invert the output before the other path "corrects" the output back to 
the original logic level.

It's rare that an FPGA design implements logic that doesn't need a sequence 
of steps - sequential logic - to produce a result.  If your design only 
needs results at 1 MHz update rates, you can accomplish much in that 1000 ns 
time period.  Most designs want to work on a higher data throughput which 
requires "pipelining" through many steps to divide the processing into many 
stages of several nanoseconds each rather than 100s of nanosecods for a full 
operation. 



Article: 100494
Subject: Re: asynchronous FIFO design
From: Brian Philofsky <brian.philofsky@no_xilinx_spam.com>
Date: Mon, 10 Apr 2006 12:09:54 -0600
Links: << >>  << T >>  << A >>

The code you have provided will use LUT RAMs when targeting Xilinx 
architectures as the asynchronous read does not allow BlockRAM 
inference.  If you desire BlockRAM, you should change the reading of the 
memory array to be synchronous (including synchronous reset if desired 
although for the depth you are using though (32-bits) LUT RAMs are 
probably not necessarily a bad thing.  At first glance, I see one issue 
with your code.  You have within an always block with a reset the 
writing to the RAM.  If you do not separate out this code into an always 
block without a reset, you could have synthesis - simulation mismatch. 
I suggest changing the following:

always @(negedge vd_rst_n or posedge clk_vd)
begin
     if(~vd_rst_n) begin
         wptr <=5'b0;
     end else begin
         if(datain_en) begin
            mem[wptr] <= datain;
            wptr      <= wptr + 1;
         end
     end
end

To:

always @(negedge vd_rst_n or posedge clk_vd)
    if(~vd_rst_n) begin
        wptr <=5'b0;
     else if (datain_en)
        wptr <= wptr + 1;

always @(posedge clk_vd)
    if(datain_en) begin
       mem[wptr] <= datain;

There are other things that can be done to make this slightly more 
efficient as well.  If you get rid of the reset on any shift register 
code like this:

always @(negedge cp_rst_n or posedge clk_cp)
begin
     if(~cp_rst_n) begin
         pkt_end_cp <= 4'b0;
     end else begin
         pkt_end_cp <= { pkt_end_cp[2:0], pkt_end};
     end
end

To:

always @(posedge clk_cp)
     pkt_end_cp <= { pkt_end_cp[2:0], pkt_end};

You would have opportunities to infer SRLs and thus save some resources. 
  In this particular case, it would not be a big difference but in 
others it may make a bigger difference.  There are also cases where 
changing to a synchronous reset from an asynchronous reset can also 
improve area and performance.  For this piece of code, again, probably 
would not see much but is still a good general suggestion.  I would 
suggest though to keep the reset asynchronous for the boundary crossing 
logic since that  should probably be considered asynchronous any ways.

--  Brian


kelvins wrote:
> As I have a problem in asynchronous FIFO design.
> My case is described as below,
> 
> I want to design a FIFO as write in clock VD domain, and read in clock
> CP domain.
> And there is a signal (VD domain) informs 32-bytes is completed write
> to FIFO, then
> can be read out in clock CP domain, and guarantee there is not any data
> coming in
> the read out phase.
> 
> The RTL code is below, It's passed in simulation phase. My problem is
> can it
> pass the synthesis phase? Will it have any issue? Thanks.
> 

<Snip>

Article: 100495
Subject: Re: NTSC video capture
From: "Anonymous" <someone@microsoft.com>
Date: Mon, 10 Apr 2006 18:24:43 GMT
Links: << >>  << T >>  << A >>
Try:
http://www.kd7lmo.net/ground_gnuradio_ota.html

about half way down there is an ntsc test pattern signal. The format (I
believe) is 8 msps complex in 16-bit I an Q samples.

If that's no good you can ask around the gnu radio message board to see if
someone will record some OTA samples for you.
-Clark

"Matt Fornero" <mfornero@gmail.com> wrote in message
news:1144692102.473040.6790@j33g2000cwa.googlegroups.com...
> Hello,
>
> I'm attempting to implement a hardware filter on an incoming video
> signal (either S-video or composite) using a Xilinx V2Pro and a VDEC1
> daughterboard from Digilent.
>
> I'm attempting to test my HDL implementation, but can't seem to find a
> way of simulating the video stream itself. Based on what I've read the
> video will be in the formats found in ITU656 and ITU601 (NTSC). What
> I'd like to do is have a file containing a digital stream in this
> format, and use it in a testbench to verify my design.
>
> The problem here is that I cannot seem to find either some method to
> convert video or image files into such a stream, or an existing stream
> for testing purposes. While I could (and am) write such a conversion
> script myself, there is the risk that I'm misundestanding the format,
> and will be testing my HDL module against an invalid data stream.
>



Article: 100496
Subject: Distributed Arithmetic
From: "nimayshah" <nimayshah@gmail.com>
Date: 10 Apr 2006 11:31:09 -0700
Links: << >>  << T >>  << A >>
Hello everybody, am new to the group and have a question. Right now i
am undergoing final semester training where my project is " Design and
Implementation of IP Core for Generic FIR Filter using distributed
arithmetic". I've already made the code, simulated it and tested it on
xilinx virtex xcv 1000. The results agree with those of the DA MATLAB
module i've designed. I've compared the synthesis reports of my core
with that of xilinx coregen DA FIR V9.0. The area usage is pretty much
the same but the frequency is almost half. Also a stark difference in
the synthesis report is that my core's lut synthesizes into a Block RAM
and the Xilinx core uses nothing like that.
So my questions are:
1. What does the core use for storing LUT contents?
2. What can i do for speed optimization?
Please send in your replies as time is running out real fast.
Regards,
Nimay Shah


Article: 100497
Subject: Re: Distributed Arithmetic
From: "nimayshah" <nimayshah@gmail.com>
Date: 10 Apr 2006 11:33:27 -0700
Links: << >>  << T >>  << A >>
Also i forgot to inform, the HDL used is Verilog and the synthesis tool
used is XST. Could the frequency problem be due to the fact that i am
using both the clock edges for different processes?


Article: 100498
Subject: Re: C-Compiler for free VHDL controller core ?
From: "Ulf Samuelsson" <ulf@a-t-m-e-l.com>
Date: Mon, 10 Apr 2006 20:35:10 +0200
Links: << >>  << T >>  << A >>
"Peter Winkler" <idontwant@totell.com> skrev i meddelandet
news:1ndi32lhgriblsukneeh81cifdf8gnqac2@4ax.com...
> Thanks for your suggestions ! I think I will have a look at these two:
>
>>* Pico(Paco)Blaze
>>* AVR
>
> I very much like AVR controllers, so maybe it is a good idea to
> look at this core. And there is also WinAVR. I hope I can get
> it to run on my XC3S200.
>
> Don't you think it is somewhat strange, that there are so few
> options for a soft prozessor for hobby stuff ? Is it so much work
> to design a soft core ? Not sure, but looking at the AVR core
> from opencores, it seems development was stopped in 2003
> and only a limited number of I/O lines are available. However,
> I am very glad that it exists at all ... ;)
>
> P


You may want to check Atmels Patent portfolio.
Have heard claims that it is impossible to replicate the core without 
violating some patents.
Don't know if anyone would bother about hobbyist use of the OpenCore 
version.
You can still download the core which is a positive sign, but I really do 
not know.

-- 
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may not be shared by my employer Atmel Nordic AB
.




Article: 100499
Subject: Re: asynchronous FIFO design
From: "Peter Alfke" <peter@xilinx.com>
Date: 10 Apr 2006 11:35:20 -0700
Links: << >>  << T >>  << A >>
If data comes in 8-bit parallel, and 32 bytes deep, then you can use
SRL16 shift registers for storage.
So you need to cascade two SRL16 per parallel bit, which makes it a
total of 16 LUTs.
Then, considering the low clock rate, you can design a clock-gating
controller that carefully switches between the two clock domains.
(see TechXclusives: "Six Easy Pieces" for glitch-free clock
multiplexing).
Total: less than 3 CLBs @ 8 LUTs per CLB..
Peter Alfke, Xilinx Applications




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