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> >I would like to know if there is any other way to implement a >bidirectional bus that does not use the IOBs ? > Although internal tristate busses are not unusual in ASICs (though some vendors have deprecated them at some periods because of the bad effects of floating signals inside ICs), they are not really compatible with FPGA technology. Just don't do it! Please! There's lots of routing resource in V4 FPGAs, so a conventional crosspoint bus structure should work fine. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147101
> >Do you know anywhere where i can find information about how to access the >compact, because i never used a FPGA and i don't know how to access a >remote device. > http://www.google.com/search?q=compact+flash+interface&ie=utf-8&oe=utf-8 Are you going to code in Verilog or VHDL? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147102
bluds <vtescandell@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: (snip, I wrote) >>One of the modes of CF looks exactly like an IDE disk driver. >>A CF to IDE converter can be made with pretty much no logic. >>I believe there is also a mode that looks like a RAM. > What do you refer when you talk about modes?? You can use CF cards in different ways. It seems that newer ones even have an SATA mode. > Do you know anywhere where i can find information about how to access the > compact, because i never used a FPGA and i don't know how to access a > remote device. http://www.compactflash.org/ Newer versions of the standard seem to cost $100.00, though it says that students can get a copy free. I thought that older versions were available free, but I don't see that now. I believe that you can get some information from CF card manufacturers, too. -- glenArticle: 147103
This is what you're looking for: http://www.conekt.net/fpgaoptim.htmlArticle: 147104
On Apr 14, 5:18=A0pm, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >I would like to know if there is any other way to implement a > >bidirectional bus that does not use the IOBs ? > > Although internal tristate busses are not unusual in ASICs (though some > vendors have deprecated them at some periods because of the bad effects o= f > floating signals inside ICs), they are not really compatible with FPGA > technology. Just don't do it! Please! > > There's lots of routing resource in V4 FPGAs, so a conventional crosspoin= t > bus structure should work fine. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com So does this mean that it is possible to have bidirectional buses inside the FPGA without using the tristate logic from the IOBs?Article: 147105
>On Apr 14, 5:18=A0pm, "RCIngham" ><robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >> >I would like to know if there is any other way to implement a >> >bidirectional bus that does not use the IOBs ? >> >> Although internal tristate busses are not unusual in ASICs (though some >> vendors have deprecated them at some periods because of the bad effects o= >f >> floating signals inside ICs), they are not really compatible with FPGA >> technology. Just don't do it! Please! >> >> There's lots of routing resource in V4 FPGAs, so a conventional crosspoin= >t >> bus structure should work fine. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >So does this mean that it is possible to have bidirectional buses >inside the FPGA without using the tristate logic from the IOBs? Separate buses for each direction. The Wishbone Bus is a good example of this: www.opencores.org/downloads/wbspec_b3.pdf --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147106
Manmohan <mmmmec@gmail.com> wrote: (snip) > So does this mean that it is possible to have bidirectional buses > inside the FPGA without using the tristate logic from the IOBs? The IOBs would only work if the bus was external. You can design with internal tristate, as far as I know, with most tools, but the implementation is more like a MUX going into one bus, and then to all inputs driven by the bus. If I did it, it would be AND gates with one input for the signal and the other for the enable. Then OR all the AND gate outputs together, and send that to all inputs reading from the bus. I don't know if that is how it is implemented, but it could be done that way. You can also do it yourself. -- glenArticle: 147107
On 4/14/2010 12:43 AM, Manmohan wrote: > > I would like to know if there is any other way to implement a > bidirectional bus that does not use the IOBs ? > > > Thanks and Regards > > Manmohan Virtex 4 doesn't have internal tri-stated signals. Do it another way. HTH, Syms.Article: 147108
On Apr 14, 8:45=A0am, David Brown <da...@westcontrol.removethisbit.com> wrote: > I am also unconvinced of the value of Verilog or VHDL functional > simulation (timing simulation is another matter, of course), if the code > you have written is not in Verilog or VHDL in the first place. =A0If your > code is written in MyHDL, and the MyHDL conversion to Verilog/VHDL is > accurate, then you can do all your functional testing entirely within > Python and MyHDL. =A0cosimulation is only relevant when you have parts > that are not written in MyHDL (and cannot easily be modelled in MyHDL). In my experience (which again is limited), there are many engineers who are happy writing synthesisable code in VHDL. They may find MyHDL useful for to generate type/conversion packages (it would be nice to have a union function to convert a record type to a vector and vica- versa) but want to continue doing the majority of coding in raw VHDL. I personally believe this comprises the majority of VHDL engineers (otherwise takeup of tools like MyHDL would be far higher). For this group having an easy way to interface to the simulator using a language other than VHDL is the sweetspot which might persuade them to try a different design flow. MyHDL is almost ready to fill that space...Article: 147109
>> >>Do you know anywhere where i can find information about how to access the >>compact, because i never used a FPGA and i don't know how to access a >>remote device. >> > >http://www.google.com/search?q=compact+flash+interface&ie=utf-8&oe=utf-8 > >Are you going to code in Verilog or VHDL? > > >--------------------------------------- >Posted through http://www.FPGARelated.com > I'm going to code it using Verilog --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147110
On Apr 14, 7:33=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Manmohan <mmm...@gmail.com> wrote: > > (snip) > > > So does this mean that it is possible to have bidirectional buses > > inside the FPGA without using the tristate logic from the IOBs? > > The IOBs would only work if the bus was external. > > You can design with internal tristate, as far as I know, > with most tools, but the implementation is more like a MUX > going into one bus, and then to all inputs driven by the bus. > > If I did it, it would be AND gates with one input for the > signal and the other for the enable. =A0Then OR all the AND gate > outputs together, and send that to all inputs reading from the bus. > > I don't know if that is how it is implemented, but it could > be done that way. =A0You can also do it yourself. > > -- glen Actually the AND / OR approach is used in the processor buses for both MicroBlaze and Power PC. i.e. the enable line AND's with the data so un "driven" lines are zero and the sources are all ORed together. If you code tristate buses and allow XST to translate them into LUT's, you'll more likely end up with MUXes. By the way, internal tristates were still available through the original Virtex series (Virtex and Virtex E) and Spartan 2. However, as others mentioned, internal tristates are gone from newer devices. Regards, GaborArticle: 147111
On Apr 14, 6:23=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > bluds <vtescandell@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > > (snip, I wrote) > > >>One of the modes of CF looks exactly like an IDE disk driver. > >>A CF to IDE converter can be made with pretty much no logic. > >>I believe there is also a mode that looks like a RAM. > > What do you refer when you talk about modes?? > > You can use CF cards in different ways. =A0It seems that newer > ones even have an SATA mode. =A0 > > > Do you know anywhere where i can find information about how to access t= he > > compact, because i never used a FPGA and i don't know how to access a > > remote device. > > http://www.compactflash.org/ > > Newer versions of the standard seem to cost $100.00, though > it says that students can get a copy free. =A0I thought that > older versions were available free, but I don't see that now. > > I believe that you can get some information from CF card > manufacturers, too. > > -- glen Most of the modes are selected by strapping resistors. Make sure your hardware is wired to support the mode you want to use. Memory mode would be simplest, but the IDE mode often allows faster access, at least for writing large blocks of memory. When you say "the Compact Flash" do you mean one on an existing board? Or is this a new hardware design? Regards GaborArticle: 147112
>On Apr 14, 6:23=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: >> bluds <vtescandell@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >> >> (snip, I wrote) >> >> >>One of the modes of CF looks exactly like an IDE disk driver. >> >>A CF to IDE converter can be made with pretty much no logic. >> >>I believe there is also a mode that looks like a RAM. >> > What do you refer when you talk about modes?? >> >> You can use CF cards in different ways. =A0It seems that newer >> ones even have an SATA mode. =A0 >> >> > Do you know anywhere where i can find information about how to access t= >he >> > compact, because i never used a FPGA and i don't know how to access a >> > remote device. >> >> http://www.compactflash.org/ >> >> Newer versions of the standard seem to cost $100.00, though >> it says that students can get a copy free. =A0I thought that >> older versions were available free, but I don't see that now. >> >> I believe that you can get some information from CF card >> manufacturers, too. >> >> -- glen > >Most of the modes are selected by strapping resistors. Make >sure your hardware is wired to support the mode you want to use. >Memory mode would be simplest, but the IDE mode often allows >faster access, at least for writing large blocks of memory. > >When you say "the Compact Flash" do you mean one on an existing >board? Or is this a new hardware design? > >Regards >Gabor > I just bought the xilinx XUPV5-LX110T board, which mainly is a Xilinx ML505 with a more powerful virtex 5 FPGA. It is possible to connect to this board a compact flash, this compact can be used to load designs to the FPGA. My objective is to use the compact flash as my hard this. This is going to be a special hard disk, because i don't need it has any format. I only need to read the bits that are stored there. The problem is have is that i don't know how can I access the compact from the FPGA. I have never used FPGA's, so i have no idea how external devices can be accessed. Somebody told me that, as the compact cannot be read bitwise (i think he told me that is read blockwise) i thought about reading the whole content from it and copy it to memory, and from there read it as i want. The idea is to feed the design with this information. My main problem, is that i'm a newbie with FPGA and i don't have any idea how can i do this. I tried to find examples, or information about how to manage all this but i didn't succeed. All the information that anybody can provide is really welcome :D Thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147113
On 4/14/2010 1:08 PM, Symon wrote: > On 4/14/2010 12:43 AM, Manmohan wrote: >> >> I would like to know if there is any other way to implement a >> bidirectional bus that does not use the IOBs ? >> >> >> Thanks and Regards >> >> Manmohan > > Virtex 4 doesn't have internal tri-stated signals. Do it another way. > > HTH, Syms. http://groups.google.com/group/comp.arch.fpga/msg/d520d67ab735e3cc?hl=enArticle: 147114
Philip Pemberton <usenet09@philpem.me.uk> wrote: > Hi, > It would seem the Lattice Mico32 support forum has gone dead (no posts/ > replies since early February), so I'm asking this here in the hope > there's an lm32 guru somewhere out there... It seem that the most (open) work around LM32 takes place with the Milkymist Project: http://www.milkymist.org/ -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 147115
MyHDL is a promising language, but at this point, it is just that: promising. I can't go to my director and tell him I'm going to use a non- commercially-supported language/toolset (VHDL/Verilog RTL converter at this point) that is at version 0.6 for his next project, and expect to still have respect, or even a job afterwards. I suspect the vast majority of non-academic HDL professionals are in exactly the same boat. Call me back when it does synthesizable fixed/floating point and has direct support from at least one major synthesis vendor. Sorry, converting to VHDL/Verilog RTL to use with anyone's tool does not cut it, unless the vendor supports the conversion process too. AndyArticle: 147116
>MyHDL is a promising language, but at this point, it is just that: >promising. > >I can't go to my director and tell him I'm going to use a non- >commercially-supported language/toolset (VHDL/Verilog RTL converter at >this point) that is at version 0.6 for his next project, and expect to >still have respect, or even a job afterwards. I suspect the vast >majority of non-academic HDL professionals are in exactly the same >boat. > >Call me back when it does synthesizable fixed/floating point and has >direct support from at least one major synthesis vendor. Sorry, >converting to VHDL/Verilog RTL to use with anyone's tool does not cut >it, unless the vendor supports the conversion process too. > >Andy > Well, you will never get that call because that isn't the point/goal of MyHDL. But given this argument you would not be interested in using Python in your flow (or any script language except TCL), whether it be for build scripts, testbenches, generation of constants, etc. I think the goal of MyHDL is to replace a bunch of tools in the developers toobox with a unified tool, in this case a programming language. Many developers find themselves doing many tasks in a scripting languages, be it Python, TCL, etc. With Python and MyHDL all this can be done in a single language, hopefully improving efficiency. MyHDL adds *RTL* to Python. The Python-RTL (MyHDL) is converted to Verilog/VHDL. There is no need or desire for direct support by a synthesis vendor. And MyHDL doesn't try to do higher level synthesis. Higher level-synthesis tools can be developed on top of MyHDL if desired. MyHDL has a focused goal which is to add *RTL* to Python, IMO makes it more attactive. I agree, any tool and/or method is easier to adopt if it has a track record. But I think the track record you are looking for might be a little misdirected (ie some large EDA company adopting). The goal of a company should be to increase efficiency and ROI. Tools like Python/MyHDL (and other languages) provide this. We outlined some of the possible risks and risk mitigation methods. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 147117
On Apr 13, 6:42=A0pm, "bluds" <vtescandell@n_o_s_p_a_m.gmail.com> wrote: > Hi, > > I'm going to use the compact flash as a store unit. It wouldn't have any > filesystem format. I will copy raw binary data to it starting from the > first sector. > > Then the objective is to read this data from the compact and then copy it > to the fpga memory in order to use it to feed my design. > > Can somebody give me some references about how should i implement the > compact flash controller. I'm new with FPGA and i don't have too much > idea. > > Thanks a lot > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com The easiest way is to use the compact flash card's True IDE mode, which is more or less identical to ATA. You should be able to get the CF card spec here: http://www.google.ca/search?hl=3Den&rls=3Dcom.microsoft%3A*&q=3Dcompact+fla= sh+specification+filetype%3Apdf&meta=3D&aq=3Df&aqi=3D&aql=3D&oq=3D&gs_rfai= =3D The meat of it is in the ATA spec: http://www.t13.org/Documents/UploadedDocuments/project/d1410r3b-ATA-ATAPI-6= .pdf Follow the ATA spec and build your software up through the layers described in the spec. Start with getting the card through initialization, being able to talk to the registers, then implement the ATA commands you need. Stick to PIO mode and get that workign first; odds are you'll find that's plenty fast for what you need. If you decide you need FAT, that's another layer and another spec. CF/ATA is easier to do than you might at first guess from looking at the spec, just don't get carried away with how much of the spec you implement. Just get what you need working. If CF isn't necessary, SD cards have a SPI mode that's a bit easier to work with. Cheers, ChrisArticle: 147118
Un bel giorno Andy Peters digiṭ: > No, internal tristates have vanished from Brand X FPGAs after the > XC4000 series. Actually I routinely use the resolved signals (i.e. std_logic_vector with '1', '0' and 'Z' states) for internal shared buses, and they work fine for every FPGA I've tried. Am I doing it wrong? -- emboliaschizoide.splinder.comArticle: 147119
Chris Maryan <kmaryan@gmail.com> wrote: (snip) > The easiest way is to use the compact flash card's True IDE mode, > which is more or less identical to ATA. > You should be able to get the CF card spec here: > http://www.google.ca/search?hl=en&rls=com.microsoft%3A*&q=compact+flash+specification+filetype%3Apdf&meta=&aq=f&aqi=&aql=&oq=&gs_rfai= > The meat of it is in the ATA spec: > http://www.t13.org/Documents/UploadedDocuments/project/d1410r3b-ATA-ATAPI-6.pdf > Follow the ATA spec and build your software up through the layers > described in the spec. Start with getting the card through > initialization, being able to talk to the registers, then implement > the ATA commands you need. Stick to PIO mode and get that workign > first; odds are you'll find that's plenty fast for what you need. If > you decide you need FAT, that's another layer and another spec. In addition, CF has the 8 bit transfer mode that was originally part of IDE/ATA but somehow forgotten along the way. Somewhat easier for some systems than 16 bit mode. -- glenArticle: 147120
On 4/14/2010 11:10 AM, dalai lamah wrote: > Un bel giorno Andy Peters digiṭ: > >> No, internal tristates have vanished from Brand X FPGAs after the >> XC4000 series. > > Actually I routinely use the resolved signals (i.e. std_logic_vector with > '1', '0' and 'Z' states) for internal shared buses, and they work fine for > every FPGA I've tried. Am I doing it wrong? > You routinely write code _asking_ for resolved signals. What you get is the synthesizer turning them into unidirectional logic with a large number of ands, ors, and muxes. The hardware itself physically cannot support tristate buses. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 147121
On Apr 11, 1:46=A0am, Anssi Saari <a...@sci.fi> wrote: > d_s_klein <d_s_kl...@yahoo.com> writes: > > It's part of Altera's 'check for updates'. > > > Just install rpm and be done with it; that's what I did. > > Isn't it easier to just symlink rpm to /bin/true? That would depend on the return code the calling application (Quartus) was expecting. Having 'rpm' loaded on a Linux system is not evil. RK (Who is slightly annoyed by the OP's belligerent attitude and lack of etiquette.)Article: 147122
On Apr 14, 3:31=A0pm, "bluds" <vtescandell@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >On Apr 14, 6:23=3DA0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrot= e: > >> bluds <vtescandell@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > > >> (snip, I wrote) > > >> >>One of the modes of CF looks exactly like an IDE disk driver. > >> >>A CF to IDE converter can be made with pretty much no logic. > >> >>I believe there is also a mode that looks like a RAM. > >> > What do you refer when you talk about modes?? > > >> You can use CF cards in different ways. =3DA0It seems that newer > >> ones even have an SATA mode. =3DA0 > > >> > Do you know anywhere where i can find information about how to acces= s > t=3D > >he > >> > compact, because i never used a FPGA and i don't know how to access = a > >> > remote device. > > >>http://www.compactflash.org/ > > >> Newer versions of the standard seem to cost $100.00, though > >> it says that students can get a copy free. =3DA0I thought that > >> older versions were available free, but I don't see that now. > > >> I believe that you can get some information from CF card > >> manufacturers, too. > > >> -- glen > > >Most of the modes are selected by strapping resistors. =A0Make > >sure your hardware is wired to support the mode you want to use. > >Memory mode would be simplest, but the IDE mode often allows > >faster access, at least for writing large blocks of memory. > > >When you say "the Compact Flash" do you mean one on an existing > >board? =A0Or is this a new hardware design? > > >Regards > >Gabor > > I just bought the xilinx XUPV5-LX110T board, which mainly is a Xilinx ML5= 05 > with a more powerful virtex 5 FPGA. > > It is possible to connect to this board a compact flash, this compact can > be used to load designs to the FPGA. > > My objective is to use the compact flash as my hard this. This is going t= o > be a special hard disk, because i don't need it has any format. I only ne= ed > to read the bits that are stored there. > > The problem is have is that i don't know how can I access the compact fro= m > the FPGA. I have never used FPGA's, so i have no idea how external device= s > can be accessed. > > Somebody told me that, as the compact cannot be read bitwise (i think he > told me that is read blockwise) i thought about reading the whole content > from it and copy it to memory, and from there read it as i want. > > The idea is to feed the design with this information. > > My main problem, is that i'm a newbie with FPGA and i don't have any idea > how can i do this. I tried to find examples, or information about how to > manage all this but i didn't succeed. > > All the information that anybody can provide is really welcome :D > > Thanks =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I'm afraid that you won't be able to use the CompactFlash card in "raw" mode. On the board you mentionned, the CF card is connected to the FPGA via a System ACE chip, which expects a FAT16-formatted card (see the user guide). Cheers, Guy.Article: 147123
glen herrmannsfeldt wrote: > In addition, CF has the 8 bit transfer mode that was originally > part of IDE/ATA but somehow forgotten along the way. Somewhat > easier for some systems than 16 bit mode. I'll have to check but even though I have seen interfaces using a 8-bit datapath (8255-based), this works only for commands. For data blocks, it wastes the higher byte of each transfer so you 512-byte sectors shrink to 256-byte chunks. Now, if you find a counter-example, i'll be glad :-) regards, > -- glen yg -- http://ygdes.com / http://yasep.orgArticle: 147124
whygee <yg@yg.yg> wrote: > glen herrmannsfeldt wrote: >> In addition, CF has the 8 bit transfer mode that was originally >> part of IDE/ATA but somehow forgotten along the way. Somewhat >> easier for some systems than 16 bit mode. > I'll have to check but even though I have seen interfaces > using a 8-bit datapath (8255-based), this works only for commands. > For data blocks, it wastes the higher byte of each transfer > so you 512-byte sectors shrink to 256-byte chunks. > Now, if you find a counter-example, i'll be glad :-) As I understand it, CF has both 8 and 16 bit modes, so you don't need an extra latch, or to waste half the data block. That is, it has the mode that IDE disks were supposed to have, but almost none implement. -- glen
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