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logjam wrote: > So I will try this on monday: > -Shave PLD about 1/8" > -place flat on a hot plate, around 130*C > -Drip nitric acid on it until the silicon is visible ... > If all else fails, I'm getting a 100MHz 18 channel 128k+ sample logic > analyzer...so... ;) Well, even if you get a visual reading of the bits, I would still want to verify it by frobbing pins. However, rather than a logic analyzer, why not simply hook it fully up to an FPGA? There are plenty < $500 boards out there that would be up for the job. That would give you all the functionality of the LA with the additional ability to incrementally build up and verify the reengineered model, all within the same framework. Just an idea, TommyArticle: 78051
>I'm not using it for an UART. It's used for an ADS1251 AD-converter to get >an exact sampling frequency of 4800 Hz. What do you mean by "exact"? How good is the crystal you are starting with? 24 MHz divided by 5000 gives a nice clean 4800 HZ. Why go through 1.8432 MHz? Another way to look at things... To go from 1.8432 to 4800 Hz, you divide by 384 To go from 24 MHz to 4800 Hz, you divide by 5000 The factors of 384 are: 2 2 2 2 2 2 2 3 The factors of 5000 are: 2 2 2 5 5 5 5 You are going to have troubles going through 1.8432 on the way from 24 MHz to 4800 Hz. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 78052
Hello, Where can I find the physical dimensions and details of FPGAs like Spartan2E xc2s100E? Thanks PhaniArticle: 78053
tangirala@gmail.com wrote: > Hello, > > Where can I find the physical dimensions and details of FPGAs like > Spartan2E xc2s100E? Howdy Phani, Xilinx has broken the most useful information out of their datasheets and now place it in "user guides." It isn't necessarily bad, but it can make it tough to try to find where something is described (or worse, find ALL the scattered pieces of information on a particular topic). You are looking for the user guide entitled Device Packaging and Thermal Characteristics, which is located here: http://support.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-19222 Have fun, MarcArticle: 78054
Hello, I have a doubt regarding the dimensions of Xilinx FPGAs. I am using Spartan2E FPGA PQ208 package. Where can I find the dimension details of this FPGA? And also, does the dimensions of the final package differ depending on the number of gates in FPGA. I mean to ask, does the physical dimensions of Spartan2E xc2s200E are greater than that of Spartan2E xc2s150E. Or, does the dimensions depend on the type of package like PQ208, or FT256 etc.,? Any help is greatly appreciated. Thanks a lot.Article: 78055
Hi Fayette, Fayette wrote: > ERROR:MDT - File not found in any repository > 'quadrature/hdl/vhdl/shift.vhd' > > This error is repeated for all the files in the ip, but they exist in > the > repository. I tried setting the repository directory, but that doesn't > change anything. This is probably very simple, but please help. Do you have a file shift.vhd in your hdl/vhdl subdir? platgen is certainly expecting one! It might be an error in your .PAO file - pcores/mycore/data/mycore.pao It tells platgen, and thus xst, which vhdl files to analyse when synthesising your peripheral. Regards, JohnArticle: 78056
Hal Murray wrote: >>I'm not using it for an UART. It's used for an ADS1251 AD-converter to get >>an exact sampling frequency of 4800 Hz. > > > What do you mean by "exact"? How good is the crystal you are > starting with? > > 24 MHz divided by 5000 gives a nice clean 4800 HZ. > Why go through 1.8432 MHz? I'd guess the ADS1251 starts with that ? So there are a couple of choices a) Divide by 13, and accept the slight sample error, but zero jitter, or b) divide by 625/48 as someone else suggested. However, rather than implement split adders as counters, this can also be done with a much simpler swallow counter : for 47/48 times divide by 13, and for 1/48 times, divide by 14. Result is 625 clocks in, for 48 out. Freq average is exact, but has slight edge jitter on the /14 cases -jgArticle: 78057
On 21 Jan 2005 11:58:30 -0800, "Gabor" <gabor@alacron.com> wrote: >I generally convert the HEX file to straight binary with a simple >C program before storing it in the uProcessor's ROM. You may also compress the image. I've used gzip for this in the past. The uP will have to decompress the image as it programs the FPGA. This will increase the time taken to configure, but the space savings may be worthwhile. Regards, AllanArticle: 78058
thanks, I got it now. and where can I find some reference designs? or some examples?Article: 78059
On Mon, 24 Jan 2005 17:49:18 +1300, Jim Granville <no.spam@designtools.co.nz> wrote: > > >Hal Murray wrote: > >>>I'm not using it for an UART. It's used for an ADS1251 AD-converter to get >>>an exact sampling frequency of 4800 Hz. >> >> >> What do you mean by "exact"? How good is the crystal you are >> starting with? >> >> 24 MHz divided by 5000 gives a nice clean 4800 HZ. >> Why go through 1.8432 MHz? > >I'd guess the ADS1251 starts with that ? > >So there are a couple of choices > >a) Divide by 13, and accept the slight sample error, but zero jitter, >or >b) divide by 625/48 as someone else suggested. > >However, rather than implement split adders as counters, this can also >be done with a much simpler swallow counter : > >for 47/48 times divide by 13, and for 1/48 times, divide by 14. > >Result is 625 clocks in, for 48 out. >Freq average is exact, but has slight edge jitter on the /14 cases ... even simpler to use a script that writes the HDL for you. (This way, there is no chance of making an error.) http://fractional-divider.tripod.com/ BTW, "slight edge jitter" is 41ns p-p. Regards, AllanArticle: 78060
Well, One thing out of many thing on this report, they didn't enable the barrel shifter on MicroBlaze which makes a big difference in performance benchmarks. Göran Luc wrote: > In any case, you would expect that the MicroBlaze would perform better > on a Xilinx device. Can one of the Xilinx Apps Guys comment why an > open core CPU has a better performance than MicroBlaze? > > Thanks, > > Luc > > On 19 Jan 2005 02:29:02 -0800, "jiri_gaisler" <jiri@gaisler.com> > wrote: > > >>A master thesis comparing the LEON2, Microblaze and Openrisc-1200 >>processors has been carried out by two students from the Chalmers >>University in Sweden. The final report is now available online at: >> >>http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf >>. >> >>Jiri Gaisler >> >>Gaisler Research > >Article: 78061
Doom, Thanks for your reply. Following my post I did a bit of reading and covered the chapter on exceptions and interrupts which suggested that it was possible due to the bits which are lefted enabled in the MSR depending on wether it is a crit or non-crit irpt. Your response confirmed this so I am now confident about implementing it. Just goes to show though that you can get better answers on these boards than the so called 'help' on the Xilinx website. Thanks VoxArticle: 78062
> I'm not sure how you know that bandpassFilter and differentiatorFilter > are inherited rather than contained by BluetoothReceiver. The > initializer list syntax is valid for both data members and base classes > when used in a constructor. > > I suspect it is used here for data members because "bandpassFilter" is > used (and not "BandpassFilter") suggesting a member, not a class. Of > course the only way to be sure is to see the declarations of these > identifiers. Hi Peter, Your reasoning sounds better than mine! I should've looked more closely since I use that naming convention myself! Cheers, KenArticle: 78063
"cedric" <clehobey@orange.fr> wrote in message news:9d5f771f.0501211130.6faec764@posting.google.com... > hi, > I'm working with ISE6.3.03i > I want to run my design at 160MHZ. So I put this contraints on my .ucf > file : > Clk = 6.25ns > Offset in = 6.25 ns; > Offset out = 6.25 ns > In my place end route report, I have 'All constraints are met". But > when I run my design wih ModelSim some Hold and Setup error occur. So > I watch the timing report (Post Place And Route). I have something > like that : > > setup hold > ARST 4.683 3.136 > ENI -0.455 3.489 > SRST 3.786 3.514 > WRCFG 1.424 4.196 > .... ... ... > > Why setup or hold could be negative? > > How could I have a better control to my design? > > thanks Hi, See my reply in thread "Problems in timing simulations" from the 16th Jan for a potential solution.... Cheers, KenArticle: 78064
I've done a lot of control unit (state machine) type designs in the past,
but not much in the DSP, arithmetic realm.
I'm working on a program which will generate some VHDL or Verilog code
to do some arithmetic operations. The code generated should be able to be
synthesized into various FPGA families (an option to the code generating
program). The function is something along the lines of:
threshold= -15.0 #typically between -20.0 and -10.0 depending on problem
X = vector of numbers in the range of -infinity to 0.0
Y = vector of numbers in the range of -n to +n
accumulator = 0
foreach x in X, each y in Y
if x > threshold #typically -20.0 to -10.0 depending on the problem
accumulator += y*exp(x)
end
end
answer = accumulator + bias
Currently I've got a lookup table for the exp(x) function which works fine
for this application since the values of x will always be negative and we
canb disregard values of x which are less than some threshold (since for
our purposes the result is essentially 0). I'm simulating the lookup
table using a case statement in a programming language called Ruby. I can
then replace the exp() function with the lookup table version in the code
and compare results. So far the lookup table seems very manageable - 64
entries seems to work just fine. I need to do a bit more research, but it
seems like 256 entries or less should work for the majority of problems.
Now I need to start migrating more towards a hardware implementation. So
I need some way to represent the values from the exp() function in binary.
I'm looking for advice on how to scale these numbers. I'm currently
thinking that given 8 bits (though the number of bits will probably be
variable depending on the application and the size of the FPGA) I have a
range of 0 to 255, so exp(0) (which is 1.0, of course) could be
represented by 255 and exp(threshold) could be represented by 0. Then
multiply this integer (between 0 and 255) by the y value which is itself
scaled, and add (or subtract, depending on the sign) the result to/from
the accumulator. At this point, I suspect that I would need to disregard
some number of LSBs in the accumulator (because the x values were
essentially scaled up to be greater than 0).
Am I on the right track?
Phil
Article: 78065Hi Fayette, try the following importing sequence, it might work for you: create your peripheral in the create import peripheral wizard right after the peripheral creation !!! do the following : open the wizard again select import exsiting peripheral click next.. in the repository or project - select "to an exsiting project" and set your xps project root (probably system.xmp) , click next.. in the core and version window write the name of your peripheral, click next.. in the source files window select hdl sources files , click next.. in the hdl sources files set check out the followings: a) "use data (mpd)" - and browse to your mpd file (under data folder in the repository) b) in the "how to locate your hdl files" - set "use an xst project file" and browse to the prj file (under the \projnav\ root in your repository). continue the importing until it is finished. open your xps project use the add/edit core to add the peripheral (I assume that you know how to do it - first add it then set it as either Master or slave on the bus, then generate address for it and then setup its ports if needed) I hope that it will work for you, if not please send more details (peripheral description etc.) Reagrds, Moti.Article: 78066
I made a mistake in the follwoing line: b) in the "how to locate your hdl files" - set "use an xst project file" and browse to the prj file (under the \projnav\ root in your repository). the .prj file should be under the peripheral_name \devl\synthesis\ in your repository Moti.Article: 78067
On 22 Jan 2005 17:51:50 -0800, Peter Alfke wrote: > It sounds like you have a (physically) working design. Why bother with > a power simulation? > Just measure the current, multiply by the supply voltage, and you have > the real power! First of all thanks for the answer. The decision of using a software approach is due to the fact that I've to estimate the power consumption of the FPGA only(not of all of the board, that's to say I've to ignore the consumption of the SRAM, all of the LEDs, the RS-232 driver and any other device around which isn't the FPGA itself) and that the measuring equipment that I've at university isn't refined enough to allow the measurement of an SMD. kl31nArticle: 78068
tangirala@gmail.com wrote: > Hello, > > I have a doubt regarding the dimensions of Xilinx FPGAs. I am using > Spartan2E FPGA PQ208 package. Where can I find the dimension details of > this FPGA? Howdy Phani, Have you tried clicking on the link I provided? http://support.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-19222 If you scroll down to the user guide entitled "Device Packaging and Thermal Characteristics" and open it up, you'll find the dimensions starting on page 12. > And also, does the dimensions of the final package differ > depending on the number of gates in FPGA. I mean to ask, does the > physical dimensions of Spartan2E xc2s200E are greater than that of > Spartan2E xc2s150E. Or, does the dimensions depend on the type of > package like PQ208, or FT256 etc.,? > Any help is greatly appreciated. This is a slightly different question, but the answer is the same. The above document provides only one set of dimensions per package. Hence the package is a constant size, regardless if the die inside the package is a xc2s100e or an xc2s400e, or anything inbetween. I hope this wasn't homework. MarcArticle: 78069
We designed an own IP, which performs some specific ALU operations. We have added it to the FSL interface of the microblaze core. Everything worked properly, but now I have extended the ALU with a root and cubic operation. When I now try to run the synthesis in EDK I get an fatal error with no further information Error Message: --------------------------------------- Generating synthesis project file ... Running XST synthesis ... INFO:MDT - The following instances are synthesized with XST. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized. A batch file, synthesis.sh, has been created that allows you to synthesize those instances in your specified synthesis tool of choice. fsl_ff3_0_wrapper (fsl_ff3_0) - C:\FF3_Arithmetic\FF3_ALU\system.mhs:133 - Running XST synthesis FATAL_ERROR:MDT:Portability/export/Port_Main.h:127:1.53 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com make: *** [implementation/microblaze_0_wrapper.ngc] Error 1 Done. As I said everything was working properly until I added two new HDL files to my IP module. The compilation and simulation looks fine of these files so there shouldnt be anything wrong with them. I used Mentor Graphics Precision RTL Synthesis and there my whole module was synthesised without any error messages. I also added this two files to my .pao file. I use EDK 6.2.03i. Anyone encountered a similar problem and has some advice what could be wrong? Unfortunately I cant find anything on the Xilinx Homepage for this kind or error Best Regards PhilippArticle: 78070
The XPower results are dependant on the toggling information coverage
from your VCD file, which is dependant on other factors like your
software running on the Microblaze processor and/or external events
(like interrupts, network packets etc.) . To give you a simple example
you can have a counter/timer in your Microblaze system but your software
doesn't enable the counter/timer (is not running) so it will not take
much power (as if it was running) try to write a test software which
enables all the peripherals in your system (dummy functions) to force a
better coverage in your VCD file.
But the mother of "accuracy" still remain the lab measurement as Peter
stated, you can "ignore" the peripherals power (sram, leds) by measuring
the current for the Vccint only (assuming that 1.2V, Vccint goes only on
your device under test) but you need to insert your amp-meter by cutting
the Vccint track (some boards are provided with a jumper for this
purpose, to insert an amp-meter)
Aurash
kl31n wrote:
>I'm having some problems in simulating the power consumption of a design I
>worked on for university. I'm using Xilinx EDK 6.3, Xilinx ISE 6.3,
>Modeltech Modelsim 6.0 SE and a Spartan 3 Starter Kit.
>
>The design uses just the MicroBlaze and the controller for the SRAM on the
>board, it synthetizes without problems and it does what it should do, but
>I'm having troubles in making the results of XPower 'accurate'.
>
>Here is how I proceed:
>
>1) creating a timing simulation from Platform Studio,
>2) running ModelSim from Platform Studio
>3) typing the following
>
>do system.do
>vsim -sdftyp system.sdf system
>vcd file system.vcd
>vcd add system/*
>run 2usquit -f
>
>4) importing the generated .vcd file together with the desing .ncd file and
>the physical constraints .pcf file in XPower.
>
>After that XPower tells me that only 88% of the signals have been set and
>only 67% of the signals toggle and that the results are 'inaccurate'.
>
>I would like to have at least 'reasonable' results, is anybody able to give
>me a hint on how to improve the accuracy? Am I omitting something?
>
>Thanks in advance for any advice.
>
>kl31n
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 78071Hi, Try to simulate a little more than 2 us. In the first 2 us after reset not much is toggled. Göran kl31n wrote: > I'm having some problems in simulating the power consumption of a design I > worked on for university. I'm using Xilinx EDK 6.3, Xilinx ISE 6.3, > Modeltech Modelsim 6.0 SE and a Spartan 3 Starter Kit. > > The design uses just the MicroBlaze and the controller for the SRAM on the > board, it synthetizes without problems and it does what it should do, but > I'm having troubles in making the results of XPower 'accurate'. > > Here is how I proceed: > > 1) creating a timing simulation from Platform Studio, > 2) running ModelSim from Platform Studio > 3) typing the following > > do system.do > vsim -sdftyp system.sdf system > vcd file system.vcd > vcd add system/* > run 2usquit -f > > 4) importing the generated .vcd file together with the desing .ncd file and > the physical constraints .pcf file in XPower. > > After that XPower tells me that only 88% of the signals have been set and > only 67% of the signals toggle and that the results are 'inaccurate'. > > I would like to have at least 'reasonable' results, is anybody able to give > me a hint on how to improve the accuracy? Am I omitting something? > > Thanks in advance for any advice. > > kl31nArticle: 78072
Sounds like you have a design that would translate to FPGA easily. There is some support for gated clocks in more recent Xilinx families but if your design is only one clock why not simply not let the synthesiser make sub-clock nets. For a limited number of clock divisions you could use the DCMs in the FPGA to do the division. I don't know if your synthesiser could do that automatically as most don't. If a DCM is used then the Xilinx timing tools can check automatically that registers in different "related" clock domains meet setup and hold. If you generate sub-divisions of clocks using logic then relative phase timing will vary with every time you build. You can limit the variance by constraits but still not advised. It is generally far better to use one clock with clock enables than have splintered clock trees. There may be some logic size impact although Xilinx FPGA flip-flops have a native, separate, flip-flop clock enable which has no direct impact on local LUT logic unlike some competing vendors that share LUT inputs with clock enables. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "gretzteam" <david.lamb@gmail.com> wrote in message news:1106322963.665960.109510@c13g2000cwb.googlegroups.com... > OK I understand that you can take the output of Design Compiler and > feed it through the xilinx tool given I write a library that gives an > FPGA equivalent for each gates. I suppose this would work if the design > is only a bunch of gates with only one clock domain. > > Our design has only one clock domain (everything is coded in verilog > with 'enable' line going to every flip flop). However, there is this > step in Design Compiler where you tell it to add 'gated clocks'. As far > as I know, this removes the 'enable' lines and actually clock the flip > flops with divided version of the master clock. It makes sure that the > clock boundaries crossing are ok. How would the xilinx tool handle a > netlist of gates that has all those clock gating circuit? > > Thanks, > David > > > John Adair wrote: > > If you have a netlist which I am guessing is mainly ANDs, ORs or even > > technology specific elements. You can model each gate/element to an > > equivalent in the FPGA. We do this kind of thing for clients from > time to > > time. More often the biggest issues come in ASIC designs that use a > lot of > > clocks and have a lot clock boundary crossing. When you get into this > type > > of design you need to be careful of how it will work in the FPGA. It > isn't > > impossible but care is needed in designs with large numbers of > clocks. As a > > side point it is worth looking at Virtex4 for this kind prototyping > of as > > the family has features aimed at designs with lots of clocks and even > clock > > boundary crossing assistance. > > > > If at all possible when starting a new design try structure the > design to be > > friendly to both types of target. If do it early enough is can be a > painless > > process and does not cost ASIC resource if done properly. > > > > John Adair > > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 > Development > > Board. > > http://www.enterpoint.co.uk > > > > > > "gretzteam" <david.lamb@gmail.com> wrote in message > > news:1106241119.166667.167990@z14g2000cwz.googlegroups.com... > > > Hi, > > > We are currently using virtexIIpro and virtex4 fpga to prototype a > dsp > > > processor. All the code is synthesizable verilog and we are using > > > Xilinx ISE to do synthesis and place and route. Everything works > fine > > > and the processor runs at full speed (50Mhz). However, this is only > > > good for functionnal verification on the bench. The ASIC flow and > the > > > FPGA flow are very different so the actual gates in the FPGA are > > > different than what will be on the ASIC. For example, we can't use > the > > > FPGA to verify the test vectors and scan chains that the test > engineer > > > is working on. > > > > > > Is it possible to prototype the EXACT same gates that will be in > the > > > ASIC? We use Synopsys Design Compiler to generate the ASIC gates. > > > Basically is there a way to take the gates generated by Design > > > Compiler, and map them in the FPGA? We don't really care if this > runs > > > slower, but it would allow the test engineer to start working on > all > > > the test vectors before we receive silicon. > > > > > > Thank you very much, > > > David > > > >Article: 78073
Hi I need some input regarding following queries related to SRAM memory chip voltage stressing tests. I will appreciate any kind of help and will get in personal contact with anyone who is intersted and has any clue about my queries. Thanks a lot for help Sincere Regards kartik in case you need to contact me for more details number is 979-676-0438 Memory chip testing for stressed and unstressed chips terms used Stressed: Suppling voltage higher than normal operating voltage, to Vcc and Vss pins of SRAM for certain time duration,which is below chip failure time for that voltage. 1. If I am subjecting Vcc and Vss of SRAM memory chip to higher voltage compared to its normal operating voltage range of 4.5-5.5 V then what is the damage to chip? what change can i observe in chip functioning due to that stressing, will it be in heating rate or temperature difference for stressed and unstressed chips ? 2. After stressing the chips separately if I replace the chips back on the board and run a code on the board then----Does heating rate pattern be same for stressed and unstressed chip? Does the unstressed and stressed chips vary in their intial chip temperature and final chip temperature obtained under normal use ? 3. I know chip fails if I keep on stressing it, for eg the SRAM I am using fails in 1 hour at voltage stress of 8V. But if I stress it for say 50 minutes, then would this chip be some how different from the normal chip (unstressed one) or its the other way that the failure state of memory ICs is either 1 or 0 so either they are functioning normally or they fail and there is nothing in between that ? 4. Will there be differnce in heating rate or temperatue range of the new chips and the chips that i have been using running other experiment for while ( both unstressed )?Article: 78074
Dear Mr. Datta, thank you for your quick reply. In fact your suggestion (set unused pins to input tristate) solved the problem. At least for our own design, not for the nios II. But that is not of importance to us right now. So thanks again, Sebastian Schmidt > Hi Sebastian, > The first two things to try in this this situation are: > > 1) Ensure all unused pins are "Inputs tri-stated" > 2) Use a USBB instead of BB > > If these do not work, let me know and I will have a support person > contact you for more details. > > Hope this helps, > Subroto Datta > Altera Corp. > > Sebastian Schmidt wrote: >> Hi. >> >> A colleague and me are having problems getting the SignalTap II Logic > >> Analyzer from Quartus II running on our Stratix device. >> We compiled a NIOS example-design and programmed it to the device. We > know >> the example is working because we loaded a little C-program to the > NIOS >> which resulted in correct output. We also tried to use Signaltap with > a >> self-created simple design but this also didn't work. >> We tried to use the SignalTap II Logic Analyzer in two ways: >> 1) We opened the Signaltap II Logic Analyzer from the Tools menu in >> Quartus. There we added the nodes we tried to analyze. We enabled >> SignalTap II Logic Analyzer in the project's settings and chose the >> created stp-file there. We followed the instructions we got from the > >> program which told us to compile the design and then to program the >> device. After programming the device, SignalTap still told us to > program >> the device. In the documention it says that "Ready to acquire" should > be >> the next message but we still get "Program the device to continue". > When >> we try to ignore the message and acquire data anyway we get a JTAG >> communication error. >> 2) The second way was to create an instance of a SignalTap II Logic >> Analyzer using the MegaWizard Plug-In Manager and added it to the > design. >> We connected the inputs (clock, data, trigger), then we created a > stp-file >> using the menu item as described in the documentation. This way we >> encountered the same problems as before. >> >> We don't know what we are doing wrong, can anybody help us getting > the >> SignalTap II Logic Analyzer running? >> >> Thanks. >
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