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Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm acceleration (e.g. arithmetic, cryptography, etc.), does it make sense to think both FPGA and ASIC when writing HDL library code? And, about pipelining combinational logic, what maximum gate-delay granularity would be good (for fmax) on FPGAs? I am guessing a 2-gate delay maximum granularity before introducing a register does not pay off. And, would similar considerations and a 2-gate delay pipelining be best for ASICs, too? (Essentially, I am trying to find guidelines to write reusable HDL, but at the moment I am not even sure that such a thing in fact makes sense.) Thanks very much in advance for any insight, JulioArticle: 160376
> In particular for algorithm acceleration (e.g. arithmetic, cryptography, > etc.), does it make sense to think both FPGA and ASIC when writing HDL > library code? I've been making cores to target both ASICs and FPGAs and it's difficult to= make it completely portable. For one thing, the ASIC clocks (for me) is t= wice as fast so I have to double the bus widths for the ASIC cores. The pa= th delay in an FPGA can be 80% route time, but in the ASIC it's mostly logi= c delay. I also have to use specific FPGA primitives which don't exist in = the ASIC. One section I constructed out of instantiated DSP48s for the Xil= inx, but for the ASIC, I just wrote behavioral code and it synthesizes as a= sea of flipflops. (This was a routing-intensive block so it was much easi= er on the ASIC.) Portable, parameterizable code is something to strive for, but it's still o= nly somewhat possible with today's tools, and you're going to have to make = changes for every target, so you don't want to expend too much effort on it= .Article: 160377
On Wednesday, January 3, 2018 at 1:48:22 AM UTC+1, Kevin Neilson wrote: > > In particular for algorithm acceleration (e.g. arithmetic, cryptography= , > > etc.), does it make sense to think both FPGA and ASIC when writing HDL > > library code? >=20 > I've been making cores to target both ASICs and FPGAs and it's difficult = to make it completely portable. For one thing, the ASIC clocks (for me) is= twice as fast so I have to double the bus widths for the ASIC cores. You mean because the bus itself stays at the same frequency, right? I have just started trying to get my head around clock domain crossing and similar= . If you don't mind me taking the chance: why would you double the bus width in that case, i.e. doesn't that still need a provider that is twice as fast= ? (Sorry, I guess I am just missing the particulars of the job involved.) > The path delay in an FPGA can be 80% route time, but in the ASIC it's mos= tly logic delay. I also have to use specific FPGA primitives which don't e= xist in the ASIC. One section I constructed out of instantiated DSP48s for= the Xilinx, but for the ASIC, I just wrote behavioral code and it synthesi= zes as a sea of flipflops. (This was a routing-intensive block so it was m= uch easier on the ASIC.) >=20 > Portable, parameterizable code is something to strive for, but it's still= only somewhat possible with today's tools, and you're going to have to mak= e changes for every target, so you don't want to expend too much effort on = it. OK, and thanks very much for your feedback, Kevin, appreciated. It's a fine line then... JulioArticle: 160378
http://tinyfpga.com/ The web site does not work 100% as there are some broken links, but all the pages are there. They currently offer three boards, A1/A2 provide two sizes of the Lattice XO2, the 256 and 1200. These two boards are basically just break out boards with nothing else other than decoupling caps and a ferrite bead. The B2 board uses the ICE40LP8K and comes with an SPI flash chip, a 16 MHz clock, PSU chips and a USB programming interface. One thing I noticed is that the TinyFPGA-B2 doesn't have a USB interface chip on it. The USB data pins go directly to the ICE40 chip. To the best of my knowledge there is no USB interface on the ICE40 chip. So I don't get how this boots up the chip. Maybe they have a way of faking out the USB interface with a special driver, but that doesn't sound very plausible to me. Anyone know much about the TinyFPGA boards? -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160379
Den onsdag den 3. januar 2018 kl. 18.55.36 UTC+1 skrev rickman: > http://tinyfpga.com/ > > The web site does not work 100% as there are some broken links, but all the > pages are there. They currently offer three boards, A1/A2 provide two sizes > of the Lattice XO2, the 256 and 1200. These two boards are basically just > break out boards with nothing else other than decoupling caps and a ferrite > bead. The B2 board uses the ICE40LP8K and comes with an SPI flash chip, a > 16 MHz clock, PSU chips and a USB programming interface. > > One thing I noticed is that the TinyFPGA-B2 doesn't have a USB interface > chip on it. The USB data pins go directly to the ICE40 chip. To the best > of my knowledge there is no USB interface on the ICE40 chip. So I don't get > how this boots up the chip. Maybe they have a way of faking out the USB > interface with a special driver, but that doesn't sound very plausible to me. they must boot the fpga from flash, looking at the verilog repository from the bootloader the USB is a softcoreArticle: 160380
lasselangwadtchristensen@gmail.com wrote on 1/3/2018 1:23 PM: > Den onsdag den 3. januar 2018 kl. 18.55.36 UTC+1 skrev rickman: >> http://tinyfpga.com/ >> >> The web site does not work 100% as there are some broken links, but all the >> pages are there. They currently offer three boards, A1/A2 provide two sizes >> of the Lattice XO2, the 256 and 1200. These two boards are basically just >> break out boards with nothing else other than decoupling caps and a ferrite >> bead. The B2 board uses the ICE40LP8K and comes with an SPI flash chip, a >> 16 MHz clock, PSU chips and a USB programming interface. >> >> One thing I noticed is that the TinyFPGA-B2 doesn't have a USB interface >> chip on it. The USB data pins go directly to the ICE40 chip. To the best >> of my knowledge there is no USB interface on the ICE40 chip. So I don't get >> how this boots up the chip. Maybe they have a way of faking out the USB >> interface with a special driver, but that doesn't sound very plausible to me. > > they must boot the fpga from flash, looking at the verilog repository from the bootloader the USB is a softcore I didn't think of that. The ICE40 has a one time programmable configuration memory, but I believe the board has an SPI flash. Can you tell they are booting the SPI flash? Is the Verilog code for the USB interface provided? I guess I can take a look. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160381
rickman wrote on 1/3/2018 3:27 PM: > lasselangwadtchristensen@gmail.com wrote on 1/3/2018 1:23 PM: >> Den onsdag den 3. januar 2018 kl. 18.55.36 UTC+1 skrev rickman: >>> http://tinyfpga.com/ >>> >>> The web site does not work 100% as there are some broken links, but all the >>> pages are there. They currently offer three boards, A1/A2 provide two sizes >>> of the Lattice XO2, the 256 and 1200. These two boards are basically just >>> break out boards with nothing else other than decoupling caps and a ferrite >>> bead. The B2 board uses the ICE40LP8K and comes with an SPI flash chip, a >>> 16 MHz clock, PSU chips and a USB programming interface. >>> >>> One thing I noticed is that the TinyFPGA-B2 doesn't have a USB interface >>> chip on it. The USB data pins go directly to the ICE40 chip. To the best >>> of my knowledge there is no USB interface on the ICE40 chip. So I don't get >>> how this boots up the chip. Maybe they have a way of faking out the USB >>> interface with a special driver, but that doesn't sound very plausible to >>> me. >> >> they must boot the fpga from flash, looking at the verilog repository from >> the bootloader the USB is a softcore > > I didn't think of that. The ICE40 has a one time programmable configuration > memory, but I believe the board has an SPI flash. Can you tell they are > booting the SPI flash? Is the Verilog code for the USB interface provided? > I guess I can take a look. Yep, Verilog for a USB to SPI connection it appears. It's been a while since I dug into the documents for the various boot modes. I can't tell if this allows the device to be booted over the USB port or if it only allows the SPI flash to be programmed and the chip booted from that. The fact that there is a "host presence" timeout which then seems to trigger a boot, I'm guessing the ICE40 boots this program from the non-volatile on-chip memory and then allows the user to control the chip or if no host is attached it boots from the SPI flash. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160382
> You mean because the bus itself stays at the same frequency, right? I ha= ve > just started trying to get my head around clock domain crossing and simil= ar. > If you don't mind me taking the chance: why would you double the bus widt= h > in that case, i.e. doesn't that still need a provider that is twice as fa= st? > (Sorry, I guess I am just missing the particulars of the job involved.) >=20 I got that all backwards. I made a core that was to operate on an FPGA and= when I ported it to the ASIC I doubled the clock speed and halved the bus = width. (Of course I could've used the same clock and bus width but then th= e gate count would be twice as big as it really needed to be.) One might m= ight think that halving the bus width is a simple matter of changing a para= meter, but of course it never works that way in hardware design. Watch out for clock domain crossings!Article: 160383
On Thursday, January 4, 2018 at 8:34:48 PM UTC+1, Kevin Neilson wrote: > Watch out for clock domain crossings! Yep, I am carefully following the reference designs I'm finding around! :) Anyway, I don't see a way to escape the topic even very early in a beginner course: the simplest top level I am writing has at least 2 clock domains, a slow "user" domain for user input and output, and a fast "core" domain for the core logic: and most user inputs I need to bring forward to the core domain, as control signals, likewise I need to bring outputs from the core back out to the user, for display/monitoring: which seems to me a very basic scenario... (Anyway, never mind my beginner's adventures, I understand this is going to take years, but please tell if I am missing something.) JulioArticle: 160384
I'm trying to decide on which to use for a project as the main default that may include a number of freelance people. can you say which of these you actually use (the most) and have the best skills in Verilog systemVerilog SystemC VHDL Other And if possible what type of work you use it for in general I dont need to know why you use a particular one - and to avoid flame wars request you dont explain that. I'm just trying to get a general feel for what people here use regularly. TIA -- john ========================= http://johntech.co.uk =========================Article: 160385
john wrote on 1/10/2018 9:17 AM: > > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. I have always intended to learn Verilog as well as I know VHDL, but I've never found a good text book that covers the gotchas of Verilog. I use VHDL for designing FPGAs. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160386
On 01/10/2018 06:17 AM, john wrote: > > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > VHDL, for both synthesis and testbenching. Some Verilog sneaks into my design when vendor-provided IP cores only come that way, but I'm read-only on it. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 160387
On Wednesday, January 10, 2018 at 6:17:32 AM UTC-8, john wrote: > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > > -- > > john > > ========================= > http://johntech.co.uk > ========================= VHDL for RTL (primarily FPGAs but ASIC in the past). VHDL + OSVVM for testbenches.Article: 160388
I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is still trying to get rid of them. Seems they over estimated the market. I had to pay a higher price to them in 2016 than I paid when they were in production (~$10) but now they are going for around $5-$6 depending on quantity and they still have 65,000. lol I wonder how cheap they would sell the lot? With that many left in inventory, this might be a good chip to design a low priced hobby board from, like the TinyFPGA, but cheaper, although there are boards on eBay using the Altera EP2C5 with half again as many LUTs plus 13 multipliers. The board is only $15 or $18 with a programming cable. -- Rick C Viewed the eclipse at Wintercrest Farms, on the centerline of totality since 1998Article: 160389
On 01/10/2018 07:17 AM, john wrote: > > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > Verilog for FPGAsArticle: 160390
On Wednesday, January 10, 2018 at 6:17:32 AM UTC-8, john wrote: > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > > -- > > john > > ========================= > http://johntech.co.uk > ========================= VHDL, it is a forced requirement for military products. WengArticle: 160391
On Wednesday, January 10, 2018 at 7:33:10 PM UTC+2, Rob Gaddi wrote: > On 01/10/2018 06:17 AM, john wrote: > > > > I'm trying to decide on which to use for a project as the main default that may > > include a number of freelance people. > > > > can you say which of these you actually use (the most) > > and have the best skills in > > > > Verilog > > systemVerilog > > SystemC > > VHDL > > Other > > > > And if possible what type of work you use it for in general > > I dont need to know why you use a particular one - and to avoid > > flame wars request you dont explain that. > > > > I'm just trying to get a general feel for what people here use regularly. > > > > TIA > > > > VHDL, for both synthesis and testbenching. Some Verilog sneaks into my > design when vendor-provided IP cores only come that way, but I'm > read-only on it. > > -- > Rob Gaddi, Highland Technology -- www.highlandtechnology.com > Email address domain is currently out of order. See above to fix. The same here. And I don't believe in things like SystemC.Article: 160392
Hi,
A wive-pipelined circuit has the same logic as its pipeline counterpart exc=
ept that the wive-pipelined circuit has only one stage, a critical path fro=
m the input register passing through a piece of computational logic to the =
output register, and no intermediate registers.
My invention kernel idea is: A designer provides the least information and =
logic code about the critical path, and leave all complex logic designs to =
a synthesizer and a system library that is what an HDL should do.
All coding has 3 steps:
1. Write a Critical Path Component (CPC) with defined interface;
2. Call a Wave-Pipelining Component (WPC) provided by a system library;
3. Call one of 3 link statement to link a CPC instantiation with a paired W=
PC instantiation to specify what your target is.
Here is the all code on a 64*64 bits signed integer multiplier C <=3D A*B.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wave_pipeline_package.all;
-- CPC code for wave-pipelined 64-bit signed integer multiplier C <=3D A*B
-- CPC_1_2 is linked with SMB by link1() / link2() if "wave" is accepted in=
VHDL
-- link1(): generation would fail if the circuit cannot accept 1 data per c=
ycle
-- link2(): generation never fails and the circuit is capable of accepting =
1 data per=20
-- INPUT_CLOCK_NUMBER cycles
entity CPC_1_2 is=20
generic ( =20
input_data_width : positive :=3D 64; -- optional
output_data_width : positive :=3D 128 -- optional
);
port (
CLK : in std_logic;
WE_i : in std_logic; -- '1': write enable to input registers A =
& B=20
Da_i : in signed(input_data_width-1 downto 0); -- input data A
Db_i : in signed(input_data_width-1 downto 0); -- input data B
WE_o_i: in std_logic; -- '1': write enable to output register C
Dc_o : out unsigned(output_data_width -1 downto 0) -- output data =
C
);
end CPC_1_2;
architecture A_CPC_1_2 of CPC_1_2 is
signal Ra : signed(input_data_width-1 downto 0); -- input register A
signal Rb : signed(input_data_width-1 downto 0); -- input register B
signal Rc : signed(output_data_width-1 downto 0); -- output register =
C
signal Cl : signed(output_data_width-1 downto 0); -- combinational lo=
gic
=20
begin
Cl <=3D Ra * Rb; -- combinational logic output, key part =
of CPC
Dc_o <=3D unsigned(Rc); -- output through output register
p_1 : process(CLK)
begin
if Rising_edge(CLK) then
if WE_i =3D '1' then -- WE_i =3D '1' : latch input data
Ra <=3D Da_i;
Rb <=3D Db_i;
end if;
=20
if WE_O_I =3D '1' then -- WE_O_I =3D '1': latch output data
Rc <=3D Cl;
end if;
end if;
end process;
---------------------------------------------------------------------------=
-----
end A_CPC_1_2;
In summary, after HDL adopting my system, writing a wave-pipelined circuit =
is simple as writing a one-cycle logic circuit.
Thank you.
Weng
Article: 160393On 10/01/2018 14:17, john wrote: > > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > Whilst I don't think I am up to commercial work, as the biggest thing I have done is the BabyBaby https://hackaday.com/2016/01/06/babybaby-a-1948-computer-on-an-fpga/ I will say I also only use VHDL. Dave G4UGMArticle: 160394
In article <MPG.34c030a39b84c7ba989753@news.virginmedia.com>, anon@example.com says... > > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. Well that pretty much nails that issue - VHDL it is. Thank you all for the quick and clean replies. -- john ========================= http://johntech.co.uk =========================Article: 160395
Am 11.01.2018 um 14:55 schrieb john: > In article <MPG.34c030a39b84c7ba989753@news.virginmedia.com>, > anon@example.com says... >> >> I'm trying to decide on which to use for a project as the main default that may >> include a number of freelance people. > > > Well that pretty much nails that issue - VHDL it is. > Thank you all for the quick and clean replies. > > For HW development I have only used VHDL so far. I personally do not know any Verilog. Though I have used in a project a couple of years ago SystemC for a hardware simulation system, but I have never encountered anyone using it for actual hardware synthesis. Greetz, SebastianArticle: 160396
> I'm just trying to get a general feel for what people here use regularly. I use Verilog (2005) for synthesis and Verilog/SystemVerilog for sim. I'd = use more SystemVerilog for synthesis but my cores have to work in a lot of = synthesis tools that don't support modern constructs. Currently I'm doing = mostly error correction. The state of synthesis tools is still primitive e= nough that I have to generate a lot of my HDL using Matlab.Article: 160397
rickman wrote: > john wrote on 1/10/2018 9:17 AM: >> >> I'm trying to decide on which to use for a project as the main default >> that may include a number of freelance people. >> I use VHDL, although I can read and do minor work on Verilog. I mostly do motion control interfaces, but have also worked on some data acquisition systems based on VME boards. JonArticle: 160398
john wrote: > In article <MPG.34c030a39b84c7ba989753@news.virginmedia.com>, > anon@example.com says... >> >> I'm trying to decide on which to use for a project as the main default >> that may include a number of freelance people. > > > Well that pretty much nails that issue - VHDL it is. > Thank you all for the quick and clean replies. > > If you are converting algorithms that were first prototyped in c, then Verilog seems a lot closer. But, there are gotchas related to automatic type conversions that can cause grief. The explicit type conversions in VHDL keep you from forgetting where they are being done. JonArticle: 160399
On Wednesday, January 10, 2018 at 8:17:32 AM UTC-6, john wrote: > I'm trying to decide on which to use for a project as the main default that may > include a number of freelance people. > > can you say which of these you actually use (the most) > and have the best skills in > > Verilog > systemVerilog > SystemC > VHDL > Other > > And if possible what type of work you use it for in general > I dont need to know why you use a particular one - and to avoid > flame wars request you dont explain that. > > I'm just trying to get a general feel for what people here use regularly. > > TIA > > -- > > john > > ========================= > http://johntech.co.uk > ========================= Use VHDL as it is required for US military work. There are books with side by side VHDL & Verilog/System Verilog: HDL Programming Fundamentals by Nazeih Botros (VHDL/Verilog) Digital Design & Computer Architecture Harris & Harris (VHDL/SystemVerilog)
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Compare FPGA features and resources
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