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On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote:
> On 13/12/2018 13:45, Weng Tianxiang wrote:
> > Hi,
> >
> > What is the name of the circuit structure that generates a state machine's jumping signals?
> >
> > I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name.
> >
> > What is the correct name?
> >
> > Thank you.
> >
> > Weng
> >
> >
> >
> Transition or next state logic?
>
> Hans
> www.ht-lab.com
Hi,
Sorry, maybe I did not specify my question clearly.
Here is a code example I would ask for answer:
type State_Type is (
S0, S1, ...);
signal WState, WState_NS : State_Type;
...;
a : process(CLK)
begin
if rising_edge(CLK) then
if SINI = '1' then
WState <= S0;
else
WState <= WState_NS;
end if;
end if;
end process;
b : process(all)
begin
case WState is
when S0 =>
if C1 then
WState_NS <= S1;
elsif C2 then
WState_NS <= S2;
else
WState_NS <= S0;
end if;
...;
end case;
end process;
Now a synthesizer must generate a signal S0_C1 as follows
S0_C1 <= not SINI and WState = S0 and C1;
When S0_C1 is asserted, WState will go from S0 to S1.
I call signal S0_C1 a jumping signal for the state machine.
I want to know:
1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit.
2. If there is a systematic circuit structure, what its name is?
3. Do you know how Xilinx or Altera generates a circuit for a state machine?
Thank you.
Weng
Article: 160876In article <d9feef36-d31d-4870-9170-700041248e94@googlegroups.com>, Weng Tianxiang <wtxwtx@gmail.com> wrote: > >Here is a code example I would ask for answer: > >type State_Type is ( > S0, S1, ...); > >signal WState, WState_NS : State_Type; >...; > >a : process(CLK) >begin > if rising_edge(CLK) then > if SINI = '1' then > WState <= S0; > > else > WState <= WState_NS; > end if; > end if; >end process; > >b : process(all) >begin > case WState is > when S0 => > if C1 then > WState_NS <= S1; > > elsif C2 then > WState_NS <= S2; > > else > WState_NS <= S0; > end if; > ...; > end case; >end process; > >Now a synthesizer must generate a signal S0_C1 as follows > >S0_C1 <= not SINI and WState = S0 and C1; > >When S0_C1 is asserted, WState will go from S0 to S1. > >I call signal S0_C1 a jumping signal for the state machine. > >I want to know: >1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > >2. If there is a systematic circuit structure, what its name is? > >3. Do you know how Xilinx or Altera generates a circuit for a state machine? > Are you looking for the terms "Mealy" and "Moore"? A "Mealy" output is a combinational function of the current state, and the current inputs. A "Moore" output is a function of just the current state. One could label the "next state" signals as "Mealy" outputs of the state machine. Xilinx and Altera generates the circuit for a state machine the same way as any other synthesized logic. It infers states as memory or registers, with combinataional logic between them. There's some specialized tools that's sometimes triggered to specific optimize recognized "state machines" - however this is an optimization only (perhaps fault tolerant too). I note that recently most of my state machines are NOT recognized as a state machine by Vivado. I don't really care, as long as it meets timing... Regards, MarkArticle: 160877
On Thursday, December 13, 2018 at 1:27:52 PM UTC-8, gtwrek wrote: > In article <d9feef36-d31d-4870-9170-700041248e94@googlegroups.com>, > Weng Tianxiang <wtxwtx@gmail.com> wrote: > > > >Here is a code example I would ask for answer: > > > >type State_Type is ( > > S0, S1, ...); > > > >signal WState, WState_NS : State_Type; > >...; > > > >a : process(CLK) > >begin > > if rising_edge(CLK) then > > if SINI = '1' then > > WState <= S0; > > > > else > > WState <= WState_NS; > > end if; > > end if; > >end process; > > > >b : process(all) > >begin > > case WState is > > when S0 => > > if C1 then > > WState_NS <= S1; > > > > elsif C2 then > > WState_NS <= S2; > > > > else > > WState_NS <= S0; > > end if; > > ...; > > end case; > >end process; > > > >Now a synthesizer must generate a signal S0_C1 as follows > > > >S0_C1 <= not SINI and WState = S0 and C1; > > > >When S0_C1 is asserted, WState will go from S0 to S1. > > > >I call signal S0_C1 a jumping signal for the state machine. > > > >I want to know: > >1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. > > > >2. If there is a systematic circuit structure, what its name is? > > > >3. Do you know how Xilinx or Altera generates a circuit for a state machine? > > > > Are you looking for the terms "Mealy" and "Moore"? A "Mealy" output is > a combinational function of the current state, and the current inputs. > A "Moore" output is a function of just the current state. One could > label the "next state" signals as "Mealy" outputs of the state machine. > > Xilinx and Altera generates the circuit for a state machine the same way > as any other synthesized logic. It infers states as memory or registers, > with combinataional logic between them. There's some specialized tools > that's sometimes triggered to specific optimize recognized "state > machines" - however this is an optimization only (perhaps fault tolerant > too). I note that recently most of my state machines are NOT recognized > as a state machine by Vivado. I don't really care, as long as it meets > timing... > > Regards, > > Mark Hi Mark, It is not about "Mealy" and "Moore" that is about how to design a state machine. My question is how to generate a state machine in a systematic circuit, including all signals, state outputs and non-state outputs, whether or not how complex a state machine structure is. If there is no systematic circuit structure to fully generate any type of state machines, I would like to invent such circuits and apply for a patent. But in my deep mind I think there should be such systematic circuits and it is not my turn, not my turn, not my turn, not my turn, not my turn, not my turn, to file such a patent. I once read a patent from Altera describing how to generate a circuit for a state machine. At the time when I was reading I found the method was absurd. Now I couldn't find the patent any more. Thank you. WengArticle: 160878
In article <ab41052b-483a-45ff-9000-ca442466d54b@googlegroups.com>, Weng Tianxiang <wtxwtx@gmail.com> wrote: > >It is not about "Mealy" and "Moore" that is about how to design a state machine. > >My question is how to generate a state machine in a systematic circuit, including all signals, state outputs and non-state outputs, whether or not how >complex a state machine structure is. > >If there is no systematic circuit structure to fully generate any type of state machines, I would like to invent such circuits and apply for a patent. Still not clear on what you're thinking about with regard to a "systematic" circuit structure. A tool to generate a "circuit, including all signals, state outputs and non-state outputs" pretty much describes a Synthesis tool. And I'd rhink most of the patents on those things have been filed and granted for a LONG time. I've never really understood the exceptional focus on "state machines" - it's just logic and registers like any other part of the design. Some clever folks decided that under very special circumstances, one could better optimized certain datapaths - and the first "state machine" optimizer was created. But it's just that an optimization tool - one that can be used in a limitted set of circumstances. In today's large designs where random logic is pretty much free, these minor optimizations don't usually interest me. Good luck, MarkArticle: 160879
On Thursday, December 13, 2018 at 2:19:51 PM UTC-8, gtwrek wrote: > In article <ab41052b-483a-45ff-9000-ca442466d54b@googlegroups.com>, > Weng Tianxiang <wtxwtx@gmail.com> wrote: > > > >It is not about "Mealy" and "Moore" that is about how to design a state machine. > > > >My question is how to generate a state machine in a systematic circuit, including all signals, state outputs and non-state outputs, whether or not how > >complex a state machine structure is. > > > >If there is no systematic circuit structure to fully generate any type of state machines, I would like to invent such circuits and apply for a patent. > > Still not clear on what you're thinking about with regard to a > "systematic" circuit structure. > > A tool to generate a "circuit, including all signals, state outputs and > non-state outputs" pretty much describes a Synthesis tool. And I'd > rhink most of the patents on those things have been filed and granted for a > LONG time. > > I've never really understood the exceptional focus on "state machines" - > it's just logic and registers like any other part of the design. Some > clever folks decided that under very special circumstances, one could > better optimized certain datapaths - and the first "state machine" > optimizer was created. But it's just that an optimization tool - one > that can be used in a limitted set of circumstances. In today's > large designs where random logic is pretty much free, these minor > optimizations don't usually interest me. > > Good luck, > > Mark Hi, Now I believe the term "decision tree" is used for generating a state machine. Because at every node in a state machine a decision must be made to determine where to go and what signals's values should be. Thank you. WengArticle: 160880
On Tuesday, December 11, 2018 at 2:13:10 PM UTC-8, Mike Perkins wrote: > On 09/12/2018 01:46, Weng Tianxiang wrote: > > On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: > >> On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: > >>> On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > >>>> I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > >>>> > >>>> Kevin > >>> > >>> Hi Kevin, > >>> > >>> I registered an account in GitHub, and I found I missed and could not find GHDL in any version. > >>> > >>> Could you please give me the website to download GitHub window version? > >>> > >>> Thank you. > >>> > >>> Weng > >> > >> https://github.com/ghdl/ghdl/releases > >> > >> Kevin > > > > Hi Kevin, > > > > Thank you very much !!! > > > > I am not an experienced application user. Here I copied all related download file names from the website you suggested above: > > <snip> > > Why not use the Windows executables? > http://ghdl.free.fr/site/pmwiki.php?n=Main.Download > > > > -- > Mike Perkins > Video Solutions Ltd > www.videosolutions.ltd.uk Hi, Help is needed. I download from https://github.com/ghdl/ghdl/releases Windows X86 (MinGW64), LLVM, 12.7MB, ghdl-0.35-mingw64-llvm.zip I extract all files, that generates 2 bin file as application: ghdl1-llvm and ghdl. I didn't see install.exe. I clicked either of them, no application was running. Thank you. WengArticle: 160881
On 13/12/2018 23:29, Weng Tianxiang wrote: > On Tuesday, December 11, 2018 at 2:13:10 PM UTC-8, Mike Perkins wrote: >> On 09/12/2018 01:46, Weng Tianxiang wrote: >>> On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: >>>> On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: >>>>> On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: >>>>>> I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. >>>>>> >>>>>> Kevin >>>>> >>>>> Hi Kevin, >>>>> >>>>> I registered an account in GitHub, and I found I missed and could not find GHDL in any version. >>>>> >>>>> Could you please give me the website to download GitHub window version? >>>>> >>>>> Thank you. >>>>> >>>>> Weng >>>> >>>> https://github.com/ghdl/ghdl/releases >>>> >>>> Kevin >>> >>> Hi Kevin, >>> >>> Thank you very much !!! >>> >>> I am not an experienced application user. Here I copied all related download file names from the website you suggested above: >> >> <snip> >> >> Why not use the Windows executables? >> http://ghdl.free.fr/site/pmwiki.php?n=Main.Download >> >> >> >> -- >> Mike Perkins >> Video Solutions Ltd >> www.videosolutions.ltd.uk > > Hi, > > Help is needed. > > I download from https://github.com/ghdl/ghdl/releases > Windows X86 (MinGW64), LLVM, 12.7MB, ghdl-0.35-mingw64-llvm.zip > > I extract all files, that generates 2 bin file as application: ghdl1-llvm and ghdl. I didn't see install.exe. I clicked either of them, no application was running. > > Thank you. Did you run the executable linked from the URL in my earlier post? http://ghdl.free.fr/ghdl-installer-0.29.1.exe From: Binary distributions GHDL for Windows Since May 2006, there is a pre-built version of windows. This is a command-line only version, almost like the Linux version. You can download the installer, and execute it to install GHDL. -- Mike Perkins Video Solutions Ltd www.videosolutions.ltd.ukArticle: 160882
Has it occurred to you that no tool gives a hoot about the term 'state mach= ine'? State machine is nothing more than a human label given to a chunk of = code so that a human can have a classification term to use when discussing = it? A tool simply takes a logic description and transforms it into logic ga= tes or lookup tables or whatever the underlying physical implementation. No= concept of a 'state machine'is required for that task. Similarly, there i= s no advantage when performing that transformation as to whether the input = describes a 'state machine' or a 'shift register'. 'Memory array' is a usef= ul classification because recognizing something describing a memory array c= an change how the description gets implemented. 'State machine'... don't th= ink so. KevinArticle: 160883
Forgot to add that your statement "Because at every node in a state machine= a decision must be made to determine where to go and what signals's values= should be" is not at all what is going on... unless you want to say that i= t applies to ALL synthesis operations that transform a human readable logic= description into an implementation. I wouldn't call that a 'decision tree'= , but you may feel differently.=20 KevinArticle: 160884
On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > Hi, > > >=20 > > > What is the name of the circuit structure that generates a state mach= ine's jumping signals? > > >=20 > > > I remember I looked at the circuit structure and wrongly remembered t= he structure name as "decision tree". By looking at Wikipedia, I realize th= at it is a wrong name. > > >=20 > > > What is the correct name? > > >=20 > > > Thank you. > > >=20 > > > Weng > > >=20 > > > =20 > > >=20 > > Transition or next state logic? > >=20 > > Hans > > www.ht-lab.com >=20 > Hi, >=20 > Sorry, maybe I did not specify my question clearly. >=20 > Here is a code example I would ask for answer: >=20 > type State_Type is ( > S0, S1, ...); >=20 > signal WState, WState_NS : State_Type; > ...; >=20 > a : process(CLK) > begin > if rising_edge(CLK) then > if SINI =3D '1' then =09 > WState <=3D S0; >=20 > else > WState <=3D WState_NS; > end if; > end if; > end process; >=20 > b : process(all) > begin > case WState is > when S0 =3D> > if C1 then > WState_NS <=3D S1; >=20 > elsif C2 then > WState_NS <=3D S2; > =09 > else =20 > WState_NS <=3D S0; > end if; > ...; > end case; > end process; >=20 > Now a synthesizer must generate a signal S0_C1 as follows >=20 > S0_C1 <=3D not SINI and WState =3D S0 and C1; >=20 > When S0_C1 is asserted, WState will go from S0 to S1. >=20 > I call signal S0_C1 a jumping signal for the state machine. >=20 > I want to know: > 1. Is there a systematic circuit structure or a systematic method that ca= n generate signal S0_C1 and others. I think it is an oldest circuit. >=20 > 2. If there is a systematic circuit structure, what its name is? >=20 > 3. Do you know how Xilinx or Altera generates a circuit for a state machi= ne? First of all, I don't agree with your hypothesis that signals S0_C1, et. al= . exist at any point in this design. They may, but might not depending on = the details of the state encoding and the optimizations performed. =20 I think what you are failing to consider is that the states, S0, S1, et. al= . are encoded in some manner. The actual logic generated would then depend= on all the input combinations that assert a given bit in the encoded state= values. So if the state variable WState_NS is three bits and uses 00, 01 = and 10 for the state values, the variable WState_NS(0) would have its own e= quation (I'll skip solving that for you) and the variable WState_NS(1) woul= d have another equation which is not likely to be the same. =20 There are likely to be shared logic in the individual bits of the state var= iable, but how likely is it that the software will optimize out the exact s= ignals you hypothesize? =20 Does this make sense?=20 Rick C.=20 Tesla referral code + https://ts.la/richard11209Article: 160885
On Thursday, December 13, 2018 at 5:19:51 PM UTC-5, gtwrek wrote: > In article <ab41052b-483a-45ff-9000-ca442466d54b@googlegroups.com>, > Weng Tianxiang <wtxwtx@gmail.com> wrote: > > > >It is not about "Mealy" and "Moore" that is about how to design a state machine. > > > >My question is how to generate a state machine in a systematic circuit, including all signals, state outputs and non-state outputs, whether or not how > >complex a state machine structure is. > > > >If there is no systematic circuit structure to fully generate any type of state machines, I would like to invent such circuits and apply for a patent. > > Still not clear on what you're thinking about with regard to a > "systematic" circuit structure. > > A tool to generate a "circuit, including all signals, state outputs and > non-state outputs" pretty much describes a Synthesis tool. And I'd > rhink most of the patents on those things have been filed and granted for a > LONG time. > > I've never really understood the exceptional focus on "state machines" - > it's just logic and registers like any other part of the design. Some > clever folks decided that under very special circumstances, one could > better optimized certain datapaths - and the first "state machine" > optimizer was created. But it's just that an optimization tool - one > that can be used in a limitted set of circumstances. In today's > large designs where random logic is pretty much free, these minor > optimizations don't usually interest me. > > Good luck, > > Mark I think Weng is looking for something very abstract and algorithmic. I believe he is expecting state machine design to be more complex than it is. This is well furrowed ground. Weng, you would do better to look elsewhere. Rick C. Tesla referral code -- https://ts.la/richard11209 PS I am posting my referral link because if anyone wants to buy a Tesla and they use my link you will get free supercharging for six months (as of now for sure) and I will get a brownie point toward a wall connector that I'd like.Article: 160886
On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com= wrote: > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > Hi, > > > >=20 > > > > What is the name of the circuit structure that generates a state ma= chine's jumping signals? > > > >=20 > > > > I remember I looked at the circuit structure and wrongly remembered= the structure name as "decision tree". By looking at Wikipedia, I realize = that it is a wrong name. > > > >=20 > > > > What is the correct name? > > > >=20 > > > > Thank you. > > > >=20 > > > > Weng > > > >=20 > > > > =20 > > > >=20 > > > Transition or next state logic? > > >=20 > > > Hans > > > www.ht-lab.com > >=20 > > Hi, > >=20 > > Sorry, maybe I did not specify my question clearly. > >=20 > > Here is a code example I would ask for answer: > >=20 > > type State_Type is ( > > S0, S1, ...); > >=20 > > signal WState, WState_NS : State_Type; > > ...; > >=20 > > a : process(CLK) > > begin > > if rising_edge(CLK) then > > if SINI =3D '1' then =09 > > WState <=3D S0; > >=20 > > else > > WState <=3D WState_NS; > > end if; > > end if; > > end process; > >=20 > > b : process(all) > > begin > > case WState is > > when S0 =3D> > > if C1 then > > WState_NS <=3D S1; > >=20 > > elsif C2 then > > WState_NS <=3D S2; > > =09 > > else =20 > > WState_NS <=3D S0; > > end if; > > ...; > > end case; > > end process; > >=20 > > Now a synthesizer must generate a signal S0_C1 as follows > >=20 > > S0_C1 <=3D not SINI and WState =3D S0 and C1; > >=20 > > When S0_C1 is asserted, WState will go from S0 to S1. > >=20 > > I call signal S0_C1 a jumping signal for the state machine. > >=20 > > I want to know: > > 1. Is there a systematic circuit structure or a systematic method that = can generate signal S0_C1 and others. I think it is an oldest circuit. > >=20 > > 2. If there is a systematic circuit structure, what its name is? > >=20 > > 3. Do you know how Xilinx or Altera generates a circuit for a state mac= hine? >=20 > First of all, I don't agree with your hypothesis that signals S0_C1, et. = al. exist at any point in this design. They may, but might not depending o= n the details of the state encoding and the optimizations performed. =20 >=20 > I think what you are failing to consider is that the states, S0, S1, et. = al. are encoded in some manner. The actual logic generated would then depe= nd on all the input combinations that assert a given bit in the encoded sta= te values. So if the state variable WState_NS is three bits and uses 00, 0= 1 and 10 for the state values, the variable WState_NS(0) would have its own= equation (I'll skip solving that for you) and the variable WState_NS(1) wo= uld have another equation which is not likely to be the same. =20 >=20 > There are likely to be shared logic in the individual bits of the state v= ariable, but how likely is it that the software will optimize out the exact= signals you hypothesize? =20 >=20 > Does this make sense?=20 >=20 > Rick C.=20 >=20 > Tesla referral code + https://ts.la/richard11209 Opps, I should have said if "the state variable WState_NS is two bits" Rick C.Article: 160887
On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com= wrote: > On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.c= om wrote: > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrot= e: > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > Hi, > > > > >=20 > > > > > What is the name of the circuit structure that generates a state = machine's jumping signals? > > > > >=20 > > > > > I remember I looked at the circuit structure and wrongly remember= ed the structure name as "decision tree". By looking at Wikipedia, I realiz= e that it is a wrong name. > > > > >=20 > > > > > What is the correct name? > > > > >=20 > > > > > Thank you. > > > > >=20 > > > > > Weng > > > > >=20 > > > > > =20 > > > > >=20 > > > > Transition or next state logic? > > > >=20 > > > > Hans > > > > www.ht-lab.com > > >=20 > > > Hi, > > >=20 > > > Sorry, maybe I did not specify my question clearly. > > >=20 > > > Here is a code example I would ask for answer: > > >=20 > > > type State_Type is ( > > > S0, S1, ...); > > >=20 > > > signal WState, WState_NS : State_Type; > > > ...; > > >=20 > > > a : process(CLK) > > > begin > > > if rising_edge(CLK) then > > > if SINI =3D '1' then =09 > > > WState <=3D S0; > > >=20 > > > else > > > WState <=3D WState_NS; > > > end if; > > > end if; > > > end process; > > >=20 > > > b : process(all) > > > begin > > > case WState is > > > when S0 =3D> > > > if C1 then > > > WState_NS <=3D S1; > > >=20 > > > elsif C2 then > > > WState_NS <=3D S2; > > > =09 > > > else =20 > > > WState_NS <=3D S0; > > > end if; > > > ...; > > > end case; > > > end process; > > >=20 > > > Now a synthesizer must generate a signal S0_C1 as follows > > >=20 > > > S0_C1 <=3D not SINI and WState =3D S0 and C1; > > >=20 > > > When S0_C1 is asserted, WState will go from S0 to S1. > > >=20 > > > I call signal S0_C1 a jumping signal for the state machine. > > >=20 > > > I want to know: > > > 1. Is there a systematic circuit structure or a systematic method tha= t can generate signal S0_C1 and others. I think it is an oldest circuit. > > >=20 > > > 2. If there is a systematic circuit structure, what its name is? > > >=20 > > > 3. Do you know how Xilinx or Altera generates a circuit for a state m= achine? > >=20 > > First of all, I don't agree with your hypothesis that signals S0_C1, et= . al. exist at any point in this design. They may, but might not depending= on the details of the state encoding and the optimizations performed. =20 > >=20 > > I think what you are failing to consider is that the states, S0, S1, et= . al. are encoded in some manner. The actual logic generated would then de= pend on all the input combinations that assert a given bit in the encoded s= tate values. So if the state variable WState_NS is three bits and uses 00,= 01 and 10 for the state values, the variable WState_NS(0) would have its o= wn equation (I'll skip solving that for you) and the variable WState_NS(1) = would have another equation which is not likely to be the same. =20 > >=20 > > There are likely to be shared logic in the individual bits of the state= variable, but how likely is it that the software will optimize out the exa= ct signals you hypothesize? =20 > >=20 > > Does this make sense?=20 > >=20 > > Rick C.=20 > >=20 > > Tesla referral code + https://ts.la/richard11209 >=20 > Opps, I should have said if "the state variable WState_NS is two bits" >=20 > Rick C. Rick, How a state machine is constructed is not important, the important thing is= : there is A BIT SIGNAL that will make the state machine going from state S= 0 to state S1 on the next cycle when it is asserted on the current cycle ba= sed on the S0_C1 logic which I have given before. S0_C1 logic is A BIT SIGNAL. WengArticle: 160888
On Thursday, December 13, 2018 at 4:14:34 PM UTC-8, Mike Perkins wrote: > On 13/12/2018 23:29, Weng Tianxiang wrote: > > On Tuesday, December 11, 2018 at 2:13:10 PM UTC-8, Mike Perkins wrote: > >> On 09/12/2018 01:46, Weng Tianxiang wrote: > >>> On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: > >>>> On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: > >>>>> On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > >>>>>> I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > >>>>>> > >>>>>> Kevin > >>>>> > >>>>> Hi Kevin, > >>>>> > >>>>> I registered an account in GitHub, and I found I missed and could not find GHDL in any version. > >>>>> > >>>>> Could you please give me the website to download GitHub window version? > >>>>> > >>>>> Thank you. > >>>>> > >>>>> Weng > >>>> > >>>> https://github.com/ghdl/ghdl/releases > >>>> > >>>> Kevin > >>> > >>> Hi Kevin, > >>> > >>> Thank you very much !!! > >>> > >>> I am not an experienced application user. Here I copied all related download file names from the website you suggested above: > >> > >> <snip> > >> > >> Why not use the Windows executables? > >> http://ghdl.free.fr/site/pmwiki.php?n=Main.Download > >> > >> > >> > >> -- > >> Mike Perkins > >> Video Solutions Ltd > >> www.videosolutions.ltd.uk > > > > Hi, > > > > Help is needed. > > > > I download from https://github.com/ghdl/ghdl/releases > > Windows X86 (MinGW64), LLVM, 12.7MB, ghdl-0.35-mingw64-llvm.zip > > > > I extract all files, that generates 2 bin file as application: ghdl1-llvm and ghdl. I didn't see install.exe. I clicked either of them, no application was running. > > > > Thank you. > > Did you run the executable linked from the URL in my earlier post? > http://ghdl.free.fr/ghdl-installer-0.29.1.exe > > From: > Binary distributions > GHDL for Windows > > Since May 2006, there is a pre-built version of windows. This is a > command-line only version, almost like the Linux version. You can > download the installer, and execute it to install GHDL. > > > -- > Mike Perkins > Video Solutions Ltd > www.videosolutions.ltd.uk Hi Mike, I downloaded ghdl-installer-0.29.1, and run it again. A window was popped up, saying: You already have GHDL 0.29.1 installed. Deinstall? What should I do? WengArticle: 160889
On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: >=20 > Rick, > How a state machine is constructed is not important, the important thing = is: there is A BIT SIGNAL that will make the state machine going from state= S0 to state S1 on the next cycle when it is asserted on the current cycle = based on the S0_C1 logic which I have given before. >=20 > S0_C1 logic is A BIT SIGNAL. >=20 > Weng That signal only 'exists' for a one-hot encoded state machine, but not for = any other encoding. Given that logic in an FPGA is implemented inside look= up tables even that signal won't actually exist either when implemented in = such a fashion. Given that you state without basis "the important thing is= : there is A BIT SIGNAL that will make the state machine going from state S= 0 to state S1" and I've shown how that is not the case, then I guess it's n= ot so important after all. You can (and will) choose to dismiss what I've = said because you're not interested in actual logic synthesis but you were t= he one who stated the importance of the existence of this signal, yet I've = shown your statement to be false. Now, it is possible for you to choose to write your source code in a way th= at you do have such a discrete signal. But doing so is your personal style= choice and has no bearing on any more general concepts such as 'state mach= ine' or any bearing on how anyone else would write their own source code fo= r a 'state machine'. As I previously mentioned, the term 'state machine' i= s really only a classification term to allow for human discussion, the term= has no real importance in logic synthesis or design. KevinArticle: 160890
On Thursday, December 13, 2018 at 10:13:09 PM UTC-5, Weng Tianxiang wrote: > On Thursday, December 13, 2018 at 4:14:34 PM UTC-8, Mike Perkins wrote: > > On 13/12/2018 23:29, Weng Tianxiang wrote: > > > On Tuesday, December 11, 2018 at 2:13:10 PM UTC-8, Mike Perkins wrote: > > >> On 09/12/2018 01:46, Weng Tianxiang wrote: > > >>> On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: > > >>>> On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: > > >>>>> On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > > >>>>>> I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > > >>>>>> > > >>>>>> Kevin > > >>>>> > > >>>>> Hi Kevin, > > >>>>> > > >>>>> I registered an account in GitHub, and I found I missed and could not find GHDL in any version. > > >>>>> > > >>>>> Could you please give me the website to download GitHub window version? > > >>>>> > > >>>>> Thank you. > > >>>>> > > >>>>> Weng > > >>>> > > >>>> https://github.com/ghdl/ghdl/releases > > >>>> > > >>>> Kevin > > >>> > > >>> Hi Kevin, > > >>> > > >>> Thank you very much !!! > > >>> > > >>> I am not an experienced application user. Here I copied all related download file names from the website you suggested above: > > >> > > >> <snip> > > >> > > >> Why not use the Windows executables? > > >> http://ghdl.free.fr/site/pmwiki.php?n=Main.Download > > >> > > >> > > >> > > >> -- > > >> Mike Perkins > > >> Video Solutions Ltd > > >> www.videosolutions.ltd.uk > > > > > > Hi, > > > > > > Help is needed. > > > > > > I download from https://github.com/ghdl/ghdl/releases > > > Windows X86 (MinGW64), LLVM, 12.7MB, ghdl-0.35-mingw64-llvm.zip > > > > > > I extract all files, that generates 2 bin file as application: ghdl1-llvm and ghdl. I didn't see install.exe. I clicked either of them, no application was running. > > > > > > Thank you. > > > > Did you run the executable linked from the URL in my earlier post? > > http://ghdl.free.fr/ghdl-installer-0.29.1.exe > > > > From: > > Binary distributions > > GHDL for Windows > > > > Since May 2006, there is a pre-built version of windows. This is a > > command-line only version, almost like the Linux version. You can > > download the installer, and execute it to install GHDL. > > > > > > -- > > Mike Perkins > > Video Solutions Ltd > > www.videosolutions.ltd.uk > > Hi Mike, > > I downloaded ghdl-installer-0.29.1, and run it again. A window was popped up, saying: You already have GHDL 0.29.1 installed. Deinstall? > > What should I do? > > Weng It depends on your goals which I can only speculate about. But here are a few directions you can go based on different assumptions... On the assumption that you installed GHDL for the purposes of running the GHDL program to process some VHDL design, I would normally suggest that you run the GHDL program. But since you seem to require step by step instructions, - Read the documentation for how to run the GHDL program - Explore your hard disk to see where the GHDL program has been stored - Find the location on your hard disk where you have stored your VHDL file(s) - Using your knowledge gained from the previous steps, run the GHDL program on your VHDL files On the assumption that you installed GHDL for the purposes of having someone else do something, then hire someone to do the work. On the assumption that you installed GHDL for no purpose at all I would suggest you uninstall the program to free up the disk space. On the assumption that you installed GHDL for the purposes of filling up your disk, I would suggest you format your hard drive. Good luck! KevinArticle: 160891
On Friday, December 14, 2018 at 4:43:57 AM UTC-8, KJ wrote: > On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote= : > >=20 > > Rick, > > How a state machine is constructed is not important, the important thin= g is: there is A BIT SIGNAL that will make the state machine going from sta= te S0 to state S1 on the next cycle when it is asserted on the current cycl= e based on the S0_C1 logic which I have given before. > >=20 > > S0_C1 logic is A BIT SIGNAL. > >=20 > > Weng >=20 > That signal only 'exists' for a one-hot encoded state machine, but not fo= r any other encoding. Given that logic in an FPGA is implemented inside lo= okup tables even that signal won't actually exist either when implemented i= n such a fashion. Given that you state without basis "the important thing = is: there is A BIT SIGNAL that will make the state machine going from state= S0 to state S1" and I've shown how that is not the case, then I guess it's= not so important after all. You can (and will) choose to dismiss what I'v= e said because you're not interested in actual logic synthesis but you were= the one who stated the importance of the existence of this signal, yet I'v= e shown your statement to be false. >=20 > Now, it is possible for you to choose to write your source code in a way = that you do have such a discrete signal. But doing so is your personal sty= le choice and has no bearing on any more general concepts such as 'state ma= chine' or any bearing on how anyone else would write their own source code = for a 'state machine'. As I previously mentioned, the term 'state machine'= is really only a classification term to allow for human discussion, the te= rm has no real importance in logic synthesis or design. >=20 > Kevin I don't want to start an argument about what I am doing, right or wrong. In= a month or so I will publish something that will shows your following 2 cl= aims are wrong:=20 1. "That signal only 'exists' for a one-hot encoded state machine, but not = for any other encoding. " 2. "As I previously mentioned, the term 'state machine' is really only a cl= assification term to allow for human discussion, the term has no real impor= tance in logic synthesis or design." I will give no reason why it is. WengArticle: 160892
On Friday, December 14, 2018 at 4:55:34 AM UTC-8, KJ wrote: > On Thursday, December 13, 2018 at 10:13:09 PM UTC-5, Weng Tianxiang wrote: > > On Thursday, December 13, 2018 at 4:14:34 PM UTC-8, Mike Perkins wrote: > > > On 13/12/2018 23:29, Weng Tianxiang wrote: > > > > On Tuesday, December 11, 2018 at 2:13:10 PM UTC-8, Mike Perkins wrote: > > > >> On 09/12/2018 01:46, Weng Tianxiang wrote: > > > >>> On Saturday, December 8, 2018 at 8:22:38 AM UTC-8, KJ wrote: > > > >>>> On Friday, December 7, 2018 at 1:27:55 PM UTC-5, Weng Tianxiang wrote: > > > >>>>> On Thursday, December 6, 2018 at 5:33:03 PM UTC-8, KJ wrote: > > > >>>>>> I prefer Modelsim but I did try GHDL. It works under Windows as well, which is what I used. > > > >>>>>> > > > >>>>>> Kevin > > > >>>>> > > > >>>>> Hi Kevin, > > > >>>>> > > > >>>>> I registered an account in GitHub, and I found I missed and could not find GHDL in any version. > > > >>>>> > > > >>>>> Could you please give me the website to download GitHub window version? > > > >>>>> > > > >>>>> Thank you. > > > >>>>> > > > >>>>> Weng > > > >>>> > > > >>>> https://github.com/ghdl/ghdl/releases > > > >>>> > > > >>>> Kevin > > > >>> > > > >>> Hi Kevin, > > > >>> > > > >>> Thank you very much !!! > > > >>> > > > >>> I am not an experienced application user. Here I copied all related download file names from the website you suggested above: > > > >> > > > >> <snip> > > > >> > > > >> Why not use the Windows executables? > > > >> http://ghdl.free.fr/site/pmwiki.php?n=Main.Download > > > >> > > > >> > > > >> > > > >> -- > > > >> Mike Perkins > > > >> Video Solutions Ltd > > > >> www.videosolutions.ltd.uk > > > > > > > > Hi, > > > > > > > > Help is needed. > > > > > > > > I download from https://github.com/ghdl/ghdl/releases > > > > Windows X86 (MinGW64), LLVM, 12.7MB, ghdl-0.35-mingw64-llvm.zip > > > > > > > > I extract all files, that generates 2 bin file as application: ghdl1-llvm and ghdl. I didn't see install.exe. I clicked either of them, no application was running. > > > > > > > > Thank you. > > > > > > Did you run the executable linked from the URL in my earlier post? > > > http://ghdl.free.fr/ghdl-installer-0.29.1.exe > > > > > > From: > > > Binary distributions > > > GHDL for Windows > > > > > > Since May 2006, there is a pre-built version of windows. This is a > > > command-line only version, almost like the Linux version. You can > > > download the installer, and execute it to install GHDL. > > > > > > > > > -- > > > Mike Perkins > > > Video Solutions Ltd > > > www.videosolutions.ltd.uk > > > > Hi Mike, > > > > I downloaded ghdl-installer-0.29.1, and run it again. A window was popped up, saying: You already have GHDL 0.29.1 installed. Deinstall? > > > > What should I do? > > > > Weng > > It depends on your goals which I can only speculate about. But here are a few directions you can go based on different assumptions... > > On the assumption that you installed GHDL for the purposes of running the GHDL program to process some VHDL design, I would normally suggest that you run the GHDL program. But since you seem to require step by step instructions, > - Read the documentation for how to run the GHDL program > - Explore your hard disk to see where the GHDL program has been stored > - Find the location on your hard disk where you have stored your VHDL file(s) > - Using your knowledge gained from the previous steps, run the GHDL program on your VHDL files > > On the assumption that you installed GHDL for the purposes of having someone else do something, then hire someone to do the work. > > On the assumption that you installed GHDL for no purpose at all I would suggest you uninstall the program to free up the disk space. > > On the assumption that you installed GHDL for the purposes of filling up your disk, I would suggest you format your hard drive. > > Good luck! > > Kevin Kevin, I even don't see any text file showing up after my download, not mention "Read the documentation for how to run the GHDL program" No GHDL application start to work, how do I start debugging with it. Mike, Please help. I download from https://github.com/ghdl/ghdl/releases Windows X86 (MinGW64), LLVM, 12.7MB, ghdl-0.35-mingw64-llvm.zip I extract all files, that generates 2 bin file as application: ghdl1-llvm and ghdl. I didn't see install.exe. I clicked either of them, no application was running. I downloaded ghdl-installer-0.29.1, and run it again. A window was popped up, saying: You already have GHDL 0.29.1 installed. Deinstall? What should I do? Thank you. WengArticle: 160893
On Friday, December 14, 2018 at 10:21:00 AM UTC-5, Weng Tianxiang wrote: > Kevin, > > I even don't see any text file showing up after my download, not mention "Read the documentation for how to run the GHDL program" > > No GHDL application start to work, how do I start debugging with it. > Does Google not work for you? Maybe try http://lmgtfy.com/?q=ghdl+tutorial and read from some of the more interesting links that you can find there. KevinArticle: 160894
On Friday, December 14, 2018 at 11:40:09 AM UTC-8, KJ wrote: > On Friday, December 14, 2018 at 10:21:00 AM UTC-5, Weng Tianxiang wrote: > > Kevin, > > > > I even don't see any text file showing up after my download, not mention "Read the documentation for how to run the GHDL program" > > > > No GHDL application start to work, how do I start debugging with it. > > > > Does Google not work for you? Maybe try http://lmgtfy.com/?q=ghdl+tutorial and read from some of the more interesting links that you can find there. > > Kevin Hi Kevin, This method really helps me. Sometimes I really need people's help, this time you really give me help. There are huge information there to teach me how to start GHDL. Of cause I will make contribution to further improve its quality and share my experiences with other people here. Than you. WengArticle: 160895
On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: > On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.c= om wrote: > > On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail= .com wrote: > > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wr= ote: > > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > > Hi, > > > > > >=20 > > > > > > What is the name of the circuit structure that generates a stat= e machine's jumping signals? > > > > > >=20 > > > > > > I remember I looked at the circuit structure and wrongly rememb= ered the structure name as "decision tree". By looking at Wikipedia, I real= ize that it is a wrong name. > > > > > >=20 > > > > > > What is the correct name? > > > > > >=20 > > > > > > Thank you. > > > > > >=20 > > > > > > Weng > > > > > >=20 > > > > > > =20 > > > > > >=20 > > > > > Transition or next state logic? > > > > >=20 > > > > > Hans > > > > > www.ht-lab.com > > > >=20 > > > > Hi, > > > >=20 > > > > Sorry, maybe I did not specify my question clearly. > > > >=20 > > > > Here is a code example I would ask for answer: > > > >=20 > > > > type State_Type is ( > > > > S0, S1, ...); > > > >=20 > > > > signal WState, WState_NS : State_Type; > > > > ...; > > > >=20 > > > > a : process(CLK) > > > > begin > > > > if rising_edge(CLK) then > > > > if SINI =3D '1' then =09 > > > > WState <=3D S0; > > > >=20 > > > > else > > > > WState <=3D WState_NS; > > > > end if; > > > > end if; > > > > end process; > > > >=20 > > > > b : process(all) > > > > begin > > > > case WState is > > > > when S0 =3D> > > > > if C1 then > > > > WState_NS <=3D S1; > > > >=20 > > > > elsif C2 then > > > > WState_NS <=3D S2; > > > > =09 > > > > else =20 > > > > WState_NS <=3D S0; > > > > end if; > > > > ...; > > > > end case; > > > > end process; > > > >=20 > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > >=20 > > > > S0_C1 <=3D not SINI and WState =3D S0 and C1; > > > >=20 > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > >=20 > > > > I call signal S0_C1 a jumping signal for the state machine. > > > >=20 > > > > I want to know: > > > > 1. Is there a systematic circuit structure or a systematic method t= hat can generate signal S0_C1 and others. I think it is an oldest circuit. > > > >=20 > > > > 2. If there is a systematic circuit structure, what its name is? > > > >=20 > > > > 3. Do you know how Xilinx or Altera generates a circuit for a state= machine? > > >=20 > > > First of all, I don't agree with your hypothesis that signals S0_C1, = et. al. exist at any point in this design. They may, but might not dependi= ng on the details of the state encoding and the optimizations performed. = =20 > > >=20 > > > I think what you are failing to consider is that the states, S0, S1, = et. al. are encoded in some manner. The actual logic generated would then = depend on all the input combinations that assert a given bit in the encoded= state values. So if the state variable WState_NS is three bits and uses 0= 0, 01 and 10 for the state values, the variable WState_NS(0) would have its= own equation (I'll skip solving that for you) and the variable WState_NS(1= ) would have another equation which is not likely to be the same. =20 > > >=20 > > > There are likely to be shared logic in the individual bits of the sta= te variable, but how likely is it that the software will optimize out the e= xact signals you hypothesize? =20 > > >=20 > > > Does this make sense?=20 > > >=20 > > > Rick C.=20 > > >=20 > > > Tesla referral code + https://ts.la/richard11209 > >=20 > > Opps, I should have said if "the state variable WState_NS is two bits" > >=20 > > Rick C. >=20 > Rick, > How a state machine is constructed is not important, the important thing = is: there is A BIT SIGNAL that will make the state machine going from state= S0 to state S1 on the next cycle when it is asserted on the current cycle = based on the S0_C1 logic which I have given before. >=20 > S0_C1 logic is A BIT SIGNAL. That is where you fail to understand. Your code does not include the signa= l S0_C1. The structure of the state machine does not dictate such a signal= . You can conceive of this signal in your mind and perform any design task= s using this signal, but that does not mean it is in any way real. Even in= the case of a 1-hot encoded machine this signal will only exist if there a= re no other ways to enter the state S1. =20 So if you only wish to suppose that the signal S0_C1 exists in your theoret= ical analysis, fine. I have found in certain cases decomposition to simila= r basic signals to be useful in specifying state machines in a simple way. = But don't for a minute believe that it exists in any real world implementa= tion or is in any way fundamental to the operation of the state machine. = =20 Of your questions:=20 > I want to know: > 1. Is there a systematic circuit structure or a systematic method that ca= n > generate signal S0_C1 and others. I think it is an oldest circuit. Yes, it is called a state/next-state table and is very simple.=20 > 2. If there is a systematic circuit structure, what its name is? We just call it "logic".=20 > 3. Do you know how Xilinx or Altera generates a circuit for a state machi= ne? Yes, they take the logic you define in your HDL and apply the many types of= decomposition, optimization and synthesis on it that are also used on all = the other logic code you use in the rest of your design. =20 Rick C.=20 Tesla referral code -- https://ts.la/richard11209Article: 160896
On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com w= rote: > On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote= : > > On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail= .com wrote: > > > On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gma= il.com wrote: > > > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang = wrote: > > > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > > > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > > > Hi, > > > > > > >=20 > > > > > > > What is the name of the circuit structure that generates a st= ate machine's jumping signals? > > > > > > >=20 > > > > > > > I remember I looked at the circuit structure and wrongly reme= mbered the structure name as "decision tree". By looking at Wikipedia, I re= alize that it is a wrong name. > > > > > > >=20 > > > > > > > What is the correct name? > > > > > > >=20 > > > > > > > Thank you. > > > > > > >=20 > > > > > > > Weng > > > > > > >=20 > > > > > > > =20 > > > > > > >=20 > > > > > > Transition or next state logic? > > > > > >=20 > > > > > > Hans > > > > > > www.ht-lab.com > > > > >=20 > > > > > Hi, > > > > >=20 > > > > > Sorry, maybe I did not specify my question clearly. > > > > >=20 > > > > > Here is a code example I would ask for answer: > > > > >=20 > > > > > type State_Type is ( > > > > > S0, S1, ...); > > > > >=20 > > > > > signal WState, WState_NS : State_Type; > > > > > ...; > > > > >=20 > > > > > a : process(CLK) > > > > > begin > > > > > if rising_edge(CLK) then > > > > > if SINI =3D '1' then =09 > > > > > WState <=3D S0; > > > > >=20 > > > > > else > > > > > WState <=3D WState_NS; > > > > > end if; > > > > > end if; > > > > > end process; > > > > >=20 > > > > > b : process(all) > > > > > begin > > > > > case WState is > > > > > when S0 =3D> > > > > > if C1 then > > > > > WState_NS <=3D S1; > > > > >=20 > > > > > elsif C2 then > > > > > WState_NS <=3D S2; > > > > > =09 > > > > > else =20 > > > > > WState_NS <=3D S0; > > > > > end if; > > > > > ...; > > > > > end case; > > > > > end process; > > > > >=20 > > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > > >=20 > > > > > S0_C1 <=3D not SINI and WState =3D S0 and C1; > > > > >=20 > > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > > >=20 > > > > > I call signal S0_C1 a jumping signal for the state machine. > > > > >=20 > > > > > I want to know: > > > > > 1. Is there a systematic circuit structure or a systematic method= that can generate signal S0_C1 and others. I think it is an oldest circuit= . > > > > >=20 > > > > > 2. If there is a systematic circuit structure, what its name is? > > > > >=20 > > > > > 3. Do you know how Xilinx or Altera generates a circuit for a sta= te machine? > > > >=20 > > > > First of all, I don't agree with your hypothesis that signals S0_C1= , et. al. exist at any point in this design. They may, but might not depen= ding on the details of the state encoding and the optimizations performed. = =20 > > > >=20 > > > > I think what you are failing to consider is that the states, S0, S1= , et. al. are encoded in some manner. The actual logic generated would the= n depend on all the input combinations that assert a given bit in the encod= ed state values. So if the state variable WState_NS is three bits and uses= 00, 01 and 10 for the state values, the variable WState_NS(0) would have i= ts own equation (I'll skip solving that for you) and the variable WState_NS= (1) would have another equation which is not likely to be the same. =20 > > > >=20 > > > > There are likely to be shared logic in the individual bits of the s= tate variable, but how likely is it that the software will optimize out the= exact signals you hypothesize? =20 > > > >=20 > > > > Does this make sense?=20 > > > >=20 > > > > Rick C.=20 > > > >=20 > > > > Tesla referral code + https://ts.la/richard11209 > > >=20 > > > Opps, I should have said if "the state variable WState_NS is two bits= " > > >=20 > > > Rick C. > >=20 > > Rick, > > How a state machine is constructed is not important, the important thin= g is: there is A BIT SIGNAL that will make the state machine going from sta= te S0 to state S1 on the next cycle when it is asserted on the current cycl= e based on the S0_C1 logic which I have given before. > >=20 > > S0_C1 logic is A BIT SIGNAL. >=20 > That is where you fail to understand. Your code does not include the sig= nal S0_C1. The structure of the state machine does not dictate such a sign= al. You can conceive of this signal in your mind and perform any design ta= sks using this signal, but that does not mean it is in any way real. Even = in the case of a 1-hot encoded machine this signal will only exist if there= are no other ways to enter the state S1. =20 >=20 > So if you only wish to suppose that the signal S0_C1 exists in your theor= etical analysis, fine. I have found in certain cases decomposition to simi= lar basic signals to be useful in specifying state machines in a simple way= . But don't for a minute believe that it exists in any real world implemen= tation or is in any way fundamental to the operation of the state machine. = =20 >=20 > Of your questions:=20 > > I want to know: > > 1. Is there a systematic circuit structure or a systematic method that = can > generate signal S0_C1 and others. I think it is an oldest circuit. >=20 > Yes, it is called a state/next-state table and is very simple.=20 >=20 > > 2. If there is a systematic circuit structure, what its name is? >=20 > We just call it "logic".=20 >=20 > > 3. Do you know how Xilinx or Altera generates a circuit for a state mac= hine? >=20 > Yes, they take the logic you define in your HDL and apply the many types = of decomposition, optimization and synthesis on it that are also used on al= l the other logic code you use in the rest of your design. =20 >=20 > Rick C.=20 >=20 > Tesla referral code -- https://ts.la/richard11209 Hi Rick, I don't want to start an argument about what I am doing, right or wrong. In= a month or so I will publish something that will show your following 2 cla= ims are wrong:=20 1. Even in the case of a 1-hot encoded machine this signal will only exist = if there are no other ways to enter the state S1.=20 2. But don't for a minute believe that it exists in any real world implemen= tation or is in any way fundamental to the operation of the state machine.= =20 Thank you. WengArticle: 160897
On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote: > On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com= wrote: > > On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wro= te: > > > On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gma= il.com wrote: > > > > On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@g= mail.com wrote: > > > > > On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxian= g wrote: > > > > > > On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrot= e: > > > > > > > On 13/12/2018 13:45, Weng Tianxiang wrote: > > > > > > > > Hi, > > > > > > > >=20 > > > > > > > > What is the name of the circuit structure that generates a = state machine's jumping signals? > > > > > > > >=20 > > > > > > > > I remember I looked at the circuit structure and wrongly re= membered the structure name as "decision tree". By looking at Wikipedia, I = realize that it is a wrong name. > > > > > > > >=20 > > > > > > > > What is the correct name? > > > > > > > >=20 > > > > > > > > Thank you. > > > > > > > >=20 > > > > > > > > Weng > > > > > > > >=20 > > > > > > > > =20 > > > > > > > >=20 > > > > > > > Transition or next state logic? > > > > > > >=20 > > > > > > > Hans > > > > > > > www.ht-lab.com > > > > > >=20 > > > > > > Hi, > > > > > >=20 > > > > > > Sorry, maybe I did not specify my question clearly. > > > > > >=20 > > > > > > Here is a code example I would ask for answer: > > > > > >=20 > > > > > > type State_Type is ( > > > > > > S0, S1, ...); > > > > > >=20 > > > > > > signal WState, WState_NS : State_Type; > > > > > > ...; > > > > > >=20 > > > > > > a : process(CLK) > > > > > > begin > > > > > > if rising_edge(CLK) then > > > > > > if SINI =3D '1' then =09 > > > > > > WState <=3D S0; > > > > > >=20 > > > > > > else > > > > > > WState <=3D WState_NS; > > > > > > end if; > > > > > > end if; > > > > > > end process; > > > > > >=20 > > > > > > b : process(all) > > > > > > begin > > > > > > case WState is > > > > > > when S0 =3D> > > > > > > if C1 then > > > > > > WState_NS <=3D S1; > > > > > >=20 > > > > > > elsif C2 then > > > > > > WState_NS <=3D S2; > > > > > > =09 > > > > > > else =20 > > > > > > WState_NS <=3D S0; > > > > > > end if; > > > > > > ...; > > > > > > end case; > > > > > > end process; > > > > > >=20 > > > > > > Now a synthesizer must generate a signal S0_C1 as follows > > > > > >=20 > > > > > > S0_C1 <=3D not SINI and WState =3D S0 and C1; > > > > > >=20 > > > > > > When S0_C1 is asserted, WState will go from S0 to S1. > > > > > >=20 > > > > > > I call signal S0_C1 a jumping signal for the state machine. > > > > > >=20 > > > > > > I want to know: > > > > > > 1. Is there a systematic circuit structure or a systematic meth= od that can generate signal S0_C1 and others. I think it is an oldest circu= it. > > > > > >=20 > > > > > > 2. If there is a systematic circuit structure, what its name is= ? > > > > > >=20 > > > > > > 3. Do you know how Xilinx or Altera generates a circuit for a s= tate machine? > > > > >=20 > > > > > First of all, I don't agree with your hypothesis that signals S0_= C1, et. al. exist at any point in this design. They may, but might not dep= ending on the details of the state encoding and the optimizations performed= . =20 > > > > >=20 > > > > > I think what you are failing to consider is that the states, S0, = S1, et. al. are encoded in some manner. The actual logic generated would t= hen depend on all the input combinations that assert a given bit in the enc= oded state values. So if the state variable WState_NS is three bits and us= es 00, 01 and 10 for the state values, the variable WState_NS(0) would have= its own equation (I'll skip solving that for you) and the variable WState_= NS(1) would have another equation which is not likely to be the same. =20 > > > > >=20 > > > > > There are likely to be shared logic in the individual bits of the= state variable, but how likely is it that the software will optimize out t= he exact signals you hypothesize? =20 > > > > >=20 > > > > > Does this make sense?=20 > > > > >=20 > > > > > Rick C.=20 > > > > >=20 > > > > > Tesla referral code + https://ts.la/richard11209 > > > >=20 > > > > Opps, I should have said if "the state variable WState_NS is two bi= ts" > > > >=20 > > > > Rick C. > > >=20 > > > Rick, > > > How a state machine is constructed is not important, the important th= ing is: there is A BIT SIGNAL that will make the state machine going from s= tate S0 to state S1 on the next cycle when it is asserted on the current cy= cle based on the S0_C1 logic which I have given before. > > >=20 > > > S0_C1 logic is A BIT SIGNAL. > >=20 > > That is where you fail to understand. Your code does not include the s= ignal S0_C1. The structure of the state machine does not dictate such a si= gnal. You can conceive of this signal in your mind and perform any design = tasks using this signal, but that does not mean it is in any way real. Eve= n in the case of a 1-hot encoded machine this signal will only exist if the= re are no other ways to enter the state S1. =20 > >=20 > > So if you only wish to suppose that the signal S0_C1 exists in your the= oretical analysis, fine. I have found in certain cases decomposition to si= milar basic signals to be useful in specifying state machines in a simple w= ay. But don't for a minute believe that it exists in any real world implem= entation or is in any way fundamental to the operation of the state machine= . =20 > >=20 > > Of your questions:=20 > > > I want to know: > > > 1. Is there a systematic circuit structure or a systematic method tha= t can > generate signal S0_C1 and others. I think it is an oldest circuit. > >=20 > > Yes, it is called a state/next-state table and is very simple.=20 > >=20 > > > 2. If there is a systematic circuit structure, what its name is? > >=20 > > We just call it "logic".=20 > >=20 > > > 3. Do you know how Xilinx or Altera generates a circuit for a state m= achine? > >=20 > > Yes, they take the logic you define in your HDL and apply the many type= s of decomposition, optimization and synthesis on it that are also used on = all the other logic code you use in the rest of your design. =20 > >=20 > > Rick C.=20 > >=20 > > Tesla referral code -- https://ts.la/richard11209 >=20 > Hi Rick, > I don't want to start an argument about what I am doing, right or wrong. = In a month or so I will publish something that will show your following 2 c= laims are wrong:=20 >=20 > 1. Even in the case of a 1-hot encoded machine this signal will only exis= t if there are no other ways to enter the state S1.=20 >=20 > 2. But don't for a minute believe that it exists in any real world implem= entation or is in any way fundamental to the operation of the state machine= .=20 No need to argue. Just explain. "The best argument is that which seems me= rely an explanation." - Dale Carnegie I have studied the 1-hot state machine. The only signal required for each = "hot" (state element) is it's next value. That value depends on *all* the = possible transitions into a given state, not just a transition from any one= state into that state which is what your S0_C1 bit signal is. The actual = signal at the input to the state FF is the logical OR of the equivalent sig= nal for transitions from *all* the states that have transitions into this s= tate, including a transition from this state itself... unless the clock ena= ble is also used, sometimes inefficiently. So the input to the FF might be= an OR of S0_C1, S1_C1N, S2_something...=20 Of course, you can write your code that way if you wish (write code, draw d= iagrams, etc). My only point is this has nothing to do with the actual res= ulting signals produced to construct the state machine in an FPGA or other = logic device. The actual input to the state FF is what we call next_state = and is not always equivalent to what you seem to be picturing. What you se= em to be picturing can be used in design, but it may not be a real signal i= n the implementation.=20 Rick C.=20 Tesla referral code -+ https://ts.la/richard11209Article: 160898
On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote: > On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote: >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.com wrote: >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang wrote: >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gmail.com wrote: >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@gmail.com wrote: >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang wrote: >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote: >>>>>>>>> Hi, >>>>>>>>> >>>>>>>>> What is the name of the circuit structure that generates a state machine's jumping signals? >>>>>>>>> >>>>>>>>> I remember I looked at the circuit structure and wrongly remembered the structure name as "decision tree". By looking at Wikipedia, I realize that it is a wrong name. >>>>>>>>> >>>>>>>>> What is the correct name? >>>>>>>>> >>>>>>>>> Thank you. >>>>>>>>> >>>>>>>>> Weng >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>> Transition or next state logic? >>>>>>>> >>>>>>>> Hans >>>>>>>> www.ht-lab.com >>>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> Sorry, maybe I did not specify my question clearly. >>>>>>> >>>>>>> Here is a code example I would ask for answer: >>>>>>> >>>>>>> type State_Type is ( >>>>>>> S0, S1, ...); >>>>>>> >>>>>>> signal WState, WState_NS : State_Type; >>>>>>> ...; >>>>>>> >>>>>>> a : process(CLK) >>>>>>> begin >>>>>>> if rising_edge(CLK) then >>>>>>> if SINI = '1' then >>>>>>> WState <= S0; >>>>>>> >>>>>>> else >>>>>>> WState <= WState_NS; >>>>>>> end if; >>>>>>> end if; >>>>>>> end process; >>>>>>> >>>>>>> b : process(all) >>>>>>> begin >>>>>>> case WState is >>>>>>> when S0 => >>>>>>> if C1 then >>>>>>> WState_NS <= S1; >>>>>>> >>>>>>> elsif C2 then >>>>>>> WState_NS <= S2; >>>>>>> >>>>>>> else >>>>>>> WState_NS <= S0; >>>>>>> end if; >>>>>>> ...; >>>>>>> end case; >>>>>>> end process; >>>>>>> >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows >>>>>>> >>>>>>> S0_C1 <= not SINI and WState = S0 and C1; >>>>>>> >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1. >>>>>>> >>>>>>> I call signal S0_C1 a jumping signal for the state machine. >>>>>>> >>>>>>> I want to know: >>>>>>> 1. Is there a systematic circuit structure or a systematic method that can generate signal S0_C1 and others. I think it is an oldest circuit. >>>>>>> >>>>>>> 2. If there is a systematic circuit structure, what its name is? >>>>>>> >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? >>>>>> >>>>>> First of all, I don't agree with your hypothesis that signals S0_C1, et. al. exist at any point in this design. They may, but might not depending on the details of the state encoding and the optimizations performed. >>>>>> >>>>>> I think what you are failing to consider is that the states, S0, S1, et. al. are encoded in some manner. The actual logic generated would then depend on all the input combinations that assert a given bit in the encoded state values. So if the state variable WState_NS is three bits and uses 00, 01 and 10 for the state values, the variable WState_NS(0) would have its own equation (I'll skip solving that for you) and the variable WState_NS(1) would have another equation which is not likely to be the same. >>>>>> >>>>>> There are likely to be shared logic in the individual bits of the state variable, but how likely is it that the software will optimize out the exact signals you hypothesize? >>>>>> >>>>>> Does this make sense? >>>>>> >>>>>> Rick C. >>>>>> >>>>>> Tesla referral code + https://ts.la/richard11209 >>>>> >>>>> Opps, I should have said if "the state variable WState_NS is two bits" >>>>> >>>>> Rick C. >>>> >>>> Rick, >>>> How a state machine is constructed is not important, the important thing is: there is A BIT SIGNAL that will make the state machine going from state S0 to state S1 on the next cycle when it is asserted on the current cycle based on the S0_C1 logic which I have given before. >>>> >>>> S0_C1 logic is A BIT SIGNAL. >>> >>> That is where you fail to understand. Your code does not include the signal S0_C1. The structure of the state machine does not dictate such a signal. You can conceive of this signal in your mind and perform any design tasks using this signal, but that does not mean it is in any way real. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. >>> >>> So if you only wish to suppose that the signal S0_C1 exists in your theoretical analysis, fine. I have found in certain cases decomposition to similar basic signals to be useful in specifying state machines in a simple way. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. >>> >>> Of your questions: >>>> I want to know: >>>> 1. Is there a systematic circuit structure or a systematic method that can > generate signal S0_C1 and others. I think it is an oldest circuit. >>> >>> Yes, it is called a state/next-state table and is very simple. >>> >>>> 2. If there is a systematic circuit structure, what its name is? >>> >>> We just call it "logic". >>> >>>> 3. Do you know how Xilinx or Altera generates a circuit for a state machine? >>> >>> Yes, they take the logic you define in your HDL and apply the many types of decomposition, optimization and synthesis on it that are also used on all the other logic code you use in the rest of your design. >>> >>> Rick C. >>> >>> Tesla referral code -- https://ts.la/richard11209 >> >> Hi Rick, >> I don't want to start an argument about what I am doing, right or wrong. In a month or so I will publish something that will show your following 2 claims are wrong: >> >> 1. Even in the case of a 1-hot encoded machine this signal will only exist if there are no other ways to enter the state S1. >> >> 2. But don't for a minute believe that it exists in any real world implementation or is in any way fundamental to the operation of the state machine. > > No need to argue. Just explain. "The best argument is that which seems merely an explanation." - Dale Carnegie > > I have studied the 1-hot state machine. The only signal required for each "hot" (state element) is it's next value. That value depends on *all* the possible transitions into a given state, not just a transition from any one state into that state which is what your S0_C1 bit signal is. The actual signal at the input to the state FF is the logical OR of the equivalent signal for transitions from *all* the states that have transitions into this state, including a transition from this state itself... unless the clock enable is also used, sometimes inefficiently. So the input to the FF might be an OR of S0_C1, S1_C1N, S2_something... > > Of course, you can write your code that way if you wish (write code, draw diagrams, etc). My only point is this has nothing to do with the actual resulting signals produced to construct the state machine in an FPGA or other logic device. The actual input to the state FF is what we call next_state and is not always equivalent to what you seem to be picturing. What you seem to be picturing can be used in design, but it may not be a real signal in the implementation. > > Rick C. > > Tesla referral code -+ https://ts.la/richard11209 > In Xilinx can't you looks at the RTL logic generated and see what signals are being produced? DaveArticle: 160899
On Saturday, December 15, 2018 at 3:50:42 AM UTC-5, David Wade wrote: > On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote: > > On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote= : > >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.= com wrote: > >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang w= rote: > >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gm= ail.com wrote: > >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@g= mail.com wrote: > >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang= wrote: > >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote: > >>>>>>>>> Hi, > >>>>>>>>> > >>>>>>>>> What is the name of the circuit structure that generates a stat= e machine's jumping signals? > >>>>>>>>> > >>>>>>>>> I remember I looked at the circuit structure and wrongly rememb= ered the structure name as "decision tree". By looking at Wikipedia, I real= ize that it is a wrong name. > >>>>>>>>> > >>>>>>>>> What is the correct name? > >>>>>>>>> > >>>>>>>>> Thank you. > >>>>>>>>> > >>>>>>>>> Weng > >>>>>>>>> > >>>>>>>>> =20 > >>>>>>>>> > >>>>>>>> Transition or next state logic? > >>>>>>>> > >>>>>>>> Hans > >>>>>>>> www.ht-lab.com > >>>>>>> > >>>>>>> Hi, > >>>>>>> > >>>>>>> Sorry, maybe I did not specify my question clearly. > >>>>>>> > >>>>>>> Here is a code example I would ask for answer: > >>>>>>> > >>>>>>> type State_Type is ( > >>>>>>> S0, S1, ...); > >>>>>>> > >>>>>>> signal WState, WState_NS : State_Type; > >>>>>>> ...; > >>>>>>> > >>>>>>> a : process(CLK) > >>>>>>> begin > >>>>>>> if rising_edge(CLK) then > >>>>>>> if SINI =3D '1' then =09 > >>>>>>> WState <=3D S0; > >>>>>>> > >>>>>>> else > >>>>>>> WState <=3D WState_NS; > >>>>>>> end if; > >>>>>>> end if; > >>>>>>> end process; > >>>>>>> > >>>>>>> b : process(all) > >>>>>>> begin > >>>>>>> case WState is > >>>>>>> when S0 =3D> > >>>>>>> if C1 then > >>>>>>> WState_NS <=3D S1; > >>>>>>> > >>>>>>> elsif C2 then > >>>>>>> WState_NS <=3D S2; > >>>>>>> =09 > >>>>>>> else > >>>>>>> WState_NS <=3D S0; > >>>>>>> end if; > >>>>>>> ...; > >>>>>>> end case; > >>>>>>> end process; > >>>>>>> > >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows > >>>>>>> > >>>>>>> S0_C1 <=3D not SINI and WState =3D S0 and C1; > >>>>>>> > >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1. > >>>>>>> > >>>>>>> I call signal S0_C1 a jumping signal for the state machine. > >>>>>>> > >>>>>>> I want to know: > >>>>>>> 1. Is there a systematic circuit structure or a systematic method= that can generate signal S0_C1 and others. I think it is an oldest circuit= . > >>>>>>> > >>>>>>> 2. If there is a systematic circuit structure, what its name is? > >>>>>>> > >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a sta= te machine? > >>>>>> > >>>>>> First of all, I don't agree with your hypothesis that signals S0_C= 1, et. al. exist at any point in this design. They may, but might not depe= nding on the details of the state encoding and the optimizations performed. > >>>>>> > >>>>>> I think what you are failing to consider is that the states, S0, S= 1, et. al. are encoded in some manner. The actual logic generated would th= en depend on all the input combinations that assert a given bit in the enco= ded state values. So if the state variable WState_NS is three bits and use= s 00, 01 and 10 for the state values, the variable WState_NS(0) would have = its own equation (I'll skip solving that for you) and the variable WState_N= S(1) would have another equation which is not likely to be the same. > >>>>>> > >>>>>> There are likely to be shared logic in the individual bits of the = state variable, but how likely is it that the software will optimize out th= e exact signals you hypothesize? > >>>>>> > >>>>>> Does this make sense? > >>>>>> > >>>>>> Rick C. > >>>>>> > >>>>>> Tesla referral code + https://ts.la/richard11209 > >>>>> > >>>>> Opps, I should have said if "the state variable WState_NS is two bi= ts" > >>>>> > >>>>> Rick C. > >>>> > >>>> Rick, > >>>> How a state machine is constructed is not important, the important t= hing is: there is A BIT SIGNAL that will make the state machine going from = state S0 to state S1 on the next cycle when it is asserted on the current c= ycle based on the S0_C1 logic which I have given before. > >>>> > >>>> S0_C1 logic is A BIT SIGNAL. > >>> > >>> That is where you fail to understand. Your code does not include the= signal S0_C1. The structure of the state machine does not dictate such a = signal. You can conceive of this signal in your mind and perform any desig= n tasks using this signal, but that does not mean it is in any way real. E= ven in the case of a 1-hot encoded machine this signal will only exist if t= here are no other ways to enter the state S1. > >>> > >>> So if you only wish to suppose that the signal S0_C1 exists in your t= heoretical analysis, fine. I have found in certain cases decomposition to = similar basic signals to be useful in specifying state machines in a simple= way. But don't for a minute believe that it exists in any real world impl= ementation or is in any way fundamental to the operation of the state machi= ne. > >>> > >>> Of your questions: > >>>> I want to know: > >>>> 1. Is there a systematic circuit structure or a systematic method th= at can > generate signal S0_C1 and others. I think it is an oldest circuit. > >>> > >>> Yes, it is called a state/next-state table and is very simple. > >>> > >>>> 2. If there is a systematic circuit structure, what its name is? > >>> > >>> We just call it "logic". > >>> > >>>> 3. Do you know how Xilinx or Altera generates a circuit for a state = machine? > >>> > >>> Yes, they take the logic you define in your HDL and apply the many ty= pes of decomposition, optimization and synthesis on it that are also used o= n all the other logic code you use in the rest of your design. > >>> > >>> Rick C. > >>> > >>> Tesla referral code -- https://ts.la/richard11209 > >> > >> Hi Rick, > >> I don't want to start an argument about what I am doing, right or wron= g. In a month or so I will publish something that will show your following = 2 claims are wrong: > >> > >> 1. Even in the case of a 1-hot encoded machine this signal will only e= xist if there are no other ways to enter the state S1. > >> > >> 2. But don't for a minute believe that it exists in any real world imp= lementation or is in any way fundamental to the operation of the state mach= ine. > >=20 > > No need to argue. Just explain. "The best argument is that which seem= s merely an explanation." - Dale Carnegie > >=20 > > I have studied the 1-hot state machine. The only signal required for e= ach "hot" (state element) is it's next value. That value depends on *all* = the possible transitions into a given state, not just a transition from any= one state into that state which is what your S0_C1 bit signal is. The act= ual signal at the input to the state FF is the logical OR of the equivalent= signal for transitions from *all* the states that have transitions into th= is state, including a transition from this state itself... unless the clock= enable is also used, sometimes inefficiently. So the input to the FF migh= t be an OR of S0_C1, S1_C1N, S2_something... > >=20 > > Of course, you can write your code that way if you wish (write code, dr= aw diagrams, etc). My only point is this has nothing to do with the actual= resulting signals produced to construct the state machine in an FPGA or ot= her logic device. The actual input to the state FF is what we call next_st= ate and is not always equivalent to what you seem to be picturing. What yo= u seem to be picturing can be used in design, but it may not be a real sign= al in the implementation. > >=20 > > Rick C. > >=20 > > Tesla referral code -+ https://ts.la/richard11209 > >=20 >=20 > In Xilinx can't you looks at the RTL logic generated and see what=20 > signals are being produced? Sure, go for it. Have you ever done it? There are times when I know what = logic I want in terms of the elements in the FPGA. Trying to get the tool = to produce that logic can actually be hard. I'm not sure if Weng thinks th= e tools will produce exactly what he is thinking or if he is thinking the s= ignals he is talking about are somehow fundamental to the nature of a state= machine. He won't say, likely because he thinks there is something to be = patented there. =20 Yeah, he may get a patent, but it's not like it will be useful. I think he= was the guy who came up with some fantastic idea of how to design wave pip= eline architectures. We tried to explain to him that he appeared to be ove= rsimplifying the matter and that time delay variance must be considered whe= n constructing such designs. =20 He says he'll be back in a couple of months when he has his patent applied = for and he can discuss the details. =20 Rick C.=20 Tesla referral code +- https://ts.la/richard11209 Get 6 months of free supercharging
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