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On Saturday, December 15, 2018 at 12:50:42 AM UTC-8, David Wade wrote: > On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote: > > On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wrote= : > >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmail.= com wrote: > >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang w= rote: > >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@gm= ail.com wrote: > >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...@g= mail.com wrote: > >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxiang= wrote: > >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrote: > >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote: > >>>>>>>>> Hi, > >>>>>>>>> > >>>>>>>>> What is the name of the circuit structure that generates a stat= e machine's jumping signals? > >>>>>>>>> > >>>>>>>>> I remember I looked at the circuit structure and wrongly rememb= ered the structure name as "decision tree". By looking at Wikipedia, I real= ize that it is a wrong name. > >>>>>>>>> > >>>>>>>>> What is the correct name? > >>>>>>>>> > >>>>>>>>> Thank you. > >>>>>>>>> > >>>>>>>>> Weng > >>>>>>>>> > >>>>>>>>> =20 > >>>>>>>>> > >>>>>>>> Transition or next state logic? > >>>>>>>> > >>>>>>>> Hans > >>>>>>>> www.ht-lab.com > >>>>>>> > >>>>>>> Hi, > >>>>>>> > >>>>>>> Sorry, maybe I did not specify my question clearly. > >>>>>>> > >>>>>>> Here is a code example I would ask for answer: > >>>>>>> > >>>>>>> type State_Type is ( > >>>>>>> S0, S1, ...); > >>>>>>> > >>>>>>> signal WState, WState_NS : State_Type; > >>>>>>> ...; > >>>>>>> > >>>>>>> a : process(CLK) > >>>>>>> begin > >>>>>>> if rising_edge(CLK) then > >>>>>>> if SINI =3D '1' then =09 > >>>>>>> WState <=3D S0; > >>>>>>> > >>>>>>> else > >>>>>>> WState <=3D WState_NS; > >>>>>>> end if; > >>>>>>> end if; > >>>>>>> end process; > >>>>>>> > >>>>>>> b : process(all) > >>>>>>> begin > >>>>>>> case WState is > >>>>>>> when S0 =3D> > >>>>>>> if C1 then > >>>>>>> WState_NS <=3D S1; > >>>>>>> > >>>>>>> elsif C2 then > >>>>>>> WState_NS <=3D S2; > >>>>>>> =09 > >>>>>>> else > >>>>>>> WState_NS <=3D S0; > >>>>>>> end if; > >>>>>>> ...; > >>>>>>> end case; > >>>>>>> end process; > >>>>>>> > >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows > >>>>>>> > >>>>>>> S0_C1 <=3D not SINI and WState =3D S0 and C1; > >>>>>>> > >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1. > >>>>>>> > >>>>>>> I call signal S0_C1 a jumping signal for the state machine. > >>>>>>> > >>>>>>> I want to know: > >>>>>>> 1. Is there a systematic circuit structure or a systematic method= that can generate signal S0_C1 and others. I think it is an oldest circuit= . > >>>>>>> > >>>>>>> 2. If there is a systematic circuit structure, what its name is? > >>>>>>> > >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a sta= te machine? > >>>>>> > >>>>>> First of all, I don't agree with your hypothesis that signals S0_C= 1, et. al. exist at any point in this design. They may, but might not depe= nding on the details of the state encoding and the optimizations performed. > >>>>>> > >>>>>> I think what you are failing to consider is that the states, S0, S= 1, et. al. are encoded in some manner. The actual logic generated would th= en depend on all the input combinations that assert a given bit in the enco= ded state values. So if the state variable WState_NS is three bits and use= s 00, 01 and 10 for the state values, the variable WState_NS(0) would have = its own equation (I'll skip solving that for you) and the variable WState_N= S(1) would have another equation which is not likely to be the same. > >>>>>> > >>>>>> There are likely to be shared logic in the individual bits of the = state variable, but how likely is it that the software will optimize out th= e exact signals you hypothesize? > >>>>>> > >>>>>> Does this make sense? > >>>>>> > >>>>>> Rick C. > >>>>>> > >>>>>> Tesla referral code + https://ts.la/richard11209 > >>>>> > >>>>> Opps, I should have said if "the state variable WState_NS is two bi= ts" > >>>>> > >>>>> Rick C. > >>>> > >>>> Rick, > >>>> How a state machine is constructed is not important, the important t= hing is: there is A BIT SIGNAL that will make the state machine going from = state S0 to state S1 on the next cycle when it is asserted on the current c= ycle based on the S0_C1 logic which I have given before. > >>>> > >>>> S0_C1 logic is A BIT SIGNAL. > >>> > >>> That is where you fail to understand. Your code does not include the= signal S0_C1. The structure of the state machine does not dictate such a = signal. You can conceive of this signal in your mind and perform any desig= n tasks using this signal, but that does not mean it is in any way real. E= ven in the case of a 1-hot encoded machine this signal will only exist if t= here are no other ways to enter the state S1. > >>> > >>> So if you only wish to suppose that the signal S0_C1 exists in your t= heoretical analysis, fine. I have found in certain cases decomposition to = similar basic signals to be useful in specifying state machines in a simple= way. But don't for a minute believe that it exists in any real world impl= ementation or is in any way fundamental to the operation of the state machi= ne. > >>> > >>> Of your questions: > >>>> I want to know: > >>>> 1. Is there a systematic circuit structure or a systematic method th= at can > generate signal S0_C1 and others. I think it is an oldest circuit. > >>> > >>> Yes, it is called a state/next-state table and is very simple. > >>> > >>>> 2. If there is a systematic circuit structure, what its name is? > >>> > >>> We just call it "logic". > >>> > >>>> 3. Do you know how Xilinx or Altera generates a circuit for a state = machine? > >>> > >>> Yes, they take the logic you define in your HDL and apply the many ty= pes of decomposition, optimization and synthesis on it that are also used o= n all the other logic code you use in the rest of your design. > >>> > >>> Rick C. > >>> > >>> Tesla referral code -- https://ts.la/richard11209 > >> > >> Hi Rick, > >> I don't want to start an argument about what I am doing, right or wron= g. In a month or so I will publish something that will show your following = 2 claims are wrong: > >> > >> 1. Even in the case of a 1-hot encoded machine this signal will only e= xist if there are no other ways to enter the state S1. > >> > >> 2. But don't for a minute believe that it exists in any real world imp= lementation or is in any way fundamental to the operation of the state mach= ine. > >=20 > > No need to argue. Just explain. "The best argument is that which seem= s merely an explanation." - Dale Carnegie > >=20 > > I have studied the 1-hot state machine. The only signal required for e= ach "hot" (state element) is it's next value. That value depends on *all* = the possible transitions into a given state, not just a transition from any= one state into that state which is what your S0_C1 bit signal is. The act= ual signal at the input to the state FF is the logical OR of the equivalent= signal for transitions from *all* the states that have transitions into th= is state, including a transition from this state itself... unless the clock= enable is also used, sometimes inefficiently. So the input to the FF migh= t be an OR of S0_C1, S1_C1N, S2_something... > >=20 > > Of course, you can write your code that way if you wish (write code, dr= aw diagrams, etc). My only point is this has nothing to do with the actual= resulting signals produced to construct the state machine in an FPGA or ot= her logic device. The actual input to the state FF is what we call next_st= ate and is not always equivalent to what you seem to be picturing. What yo= u seem to be picturing can be used in design, but it may not be a real sign= al in the implementation. > >=20 > > Rick C. > >=20 > > Tesla referral code -+ https://ts.la/richard11209 > >=20 >=20 > In Xilinx can't you looks at the RTL logic generated and see what=20 > signals are being produced? >=20 > Dave Rick, We don't have to argue, follow Dave's advice, take my code, compile it in X= ilinx, look at the generated logic, you would find my S0_C1 signal is there= , whether you have 10 states or 100 states.=20 Very simple thing can be solved by Dave's advice and facts, not by argument= .=20 I have spent a lot of time reading the generated logic! WengArticle: 160901
On Tuesday, December 4, 2018 at 8:46:02 PM UTC-8, Weng Tianxiang wrote: > Hi, > > I downloaded 11.0_modelsim_ase_windows.exe from https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html > > Release Notes For ModelSim Altera 10.1b > > Apr 26 2012 > Copyright 1991-2012 Mentor Graphics Corporation > All rights reserved. > > After installing the software, I cannot run it: Unable to checkout a licence. Modelsim-Altera uses the following environment variables to check the licence (listed in the order of preference) > > 1. MGLS_LICENCE_FILE > 2. LM_LICENCE_FILE. > > I don't know: > 1. How to set the environment variables. > > 2. If the licence file is valid for me to free use? > > Thank you. > > Weng Hi, Here is the latest version of GHDL document published minutes ago: https://media.readthedocs.org/pdf/ghdl/latest/ghdl.pdf GHDL Documentation Release 0.36-dev Tristan Gingold Dec 15, 2018 WengArticle: 160902
On Saturday, December 15, 2018 at 7:43:52 AM UTC-8, Weng Tianxiang wrote: > On Tuesday, December 4, 2018 at 8:46:02 PM UTC-8, Weng Tianxiang wrote: > > Hi, > > > > I downloaded 11.0_modelsim_ase_windows.exe from https://www.intel.com/content/www/us/en/programmable/downloads/software/modelsim/121.html > > > > Release Notes For ModelSim Altera 10.1b > > > > Apr 26 2012 > > Copyright 1991-2012 Mentor Graphics Corporation > > All rights reserved. > > > > After installing the software, I cannot run it: Unable to checkout a licence. Modelsim-Altera uses the following environment variables to check the licence (listed in the order of preference) > > > > 1. MGLS_LICENCE_FILE > > 2. LM_LICENCE_FILE. > > > > I don't know: > > 1. How to set the environment variables. > > > > 2. If the licence file is valid for me to free use? > > > > Thank you. > > > > Weng > > Hi, > > Here is the latest version of GHDL document published minutes ago: > > https://media.readthedocs.org/pdf/ghdl/latest/ghdl.pdf > > GHDL Documentation > > Release 0.36-dev > > Tristan Gingold > > Dec 15, 2018 > > Weng It is the latest INFORMATION of GHDL: The current version of GHDL does not contain any graphical viewer: you cannot see signal waves. You can still check the behavior of your design with a test bench. Moreover, the current version can produce a GHW, VCD or FST files which can be viewed with a waveform viewer, such as GtkWave. GHDL aims at implementing VHDL as defined by IEEE 1076. It supports the 1987, 1993 and 2002 revisions and, partially, the latest, 2008. PSL is also partially supported. Several third party projects are supported: VUnit, OSVVM, cocotb (through the VPI interface), . . . Now I know why GHDL is not populous, the basic reason is it has no waveform viewer! But for a free version, it still has its values: 1. It can be used to correct all VHDL grammar errors, playing the same rule as Modelsim does. 2. It can be used to test a pre-issued product playing the same rule as Modelsim does, but it should be faster than Modelsim PE or SE. 3. At least it provides files to communicate with third party software to view the waveform. I will be comfortable with this method: As an experienced VHDL designer, I spent most of time running Modelsim until an error showed up. The speed is very important factor to get all bugs discovered. WengArticle: 160903
On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote:
> On Saturday, December 15, 2018 at 12:50:42 AM UTC-8, David Wade wrote:
> > On 15/12/2018 07:50, gnuarm.deletethisbit@gmail.com wrote:
> > > On Friday, December 14, 2018 at 11:59:13 PM UTC-5, Weng Tianxiang wro=
te:
> > >> On Friday, December 14, 2018 at 7:30:22 PM UTC-8, gnuarm.del...@gmai=
l.com wrote:
> > >>> On Thursday, December 13, 2018 at 10:06:58 PM UTC-5, Weng Tianxiang=
wrote:
> > >>>> On Thursday, December 13, 2018 at 6:09:09 PM UTC-8, gnuarm.del...@=
gmail.com wrote:
> > >>>>> On Thursday, December 13, 2018 at 9:02:26 PM UTC-5, gnuarm.del...=
@gmail.com wrote:
> > >>>>>> On Thursday, December 13, 2018 at 3:14:03 PM UTC-5, Weng Tianxia=
ng wrote:
> > >>>>>>> On Thursday, December 13, 2018 at 8:06:46 AM UTC-8, HT-Lab wrot=
e:
> > >>>>>>>> On 13/12/2018 13:45, Weng Tianxiang wrote:
> > >>>>>>>>> Hi,
> > >>>>>>>>>
> > >>>>>>>>> What is the name of the circuit structure that generates a st=
ate machine's jumping signals?
> > >>>>>>>>>
> > >>>>>>>>> I remember I looked at the circuit structure and wrongly reme=
mbered the structure name as "decision tree". By looking at Wikipedia, I re=
alize that it is a wrong name.
> > >>>>>>>>>
> > >>>>>>>>> What is the correct name?
> > >>>>>>>>>
> > >>>>>>>>> Thank you.
> > >>>>>>>>>
> > >>>>>>>>> Weng
> > >>>>>>>>>
> > >>>>>>>>> =20
> > >>>>>>>>>
> > >>>>>>>> Transition or next state logic?
> > >>>>>>>>
> > >>>>>>>> Hans
> > >>>>>>>> www.ht-lab.com
> > >>>>>>>
> > >>>>>>> Hi,
> > >>>>>>>
> > >>>>>>> Sorry, maybe I did not specify my question clearly.
> > >>>>>>>
> > >>>>>>> Here is a code example I would ask for answer:
> > >>>>>>>
> > >>>>>>> type State_Type is (
> > >>>>>>> S0, S1, ...);
> > >>>>>>>
> > >>>>>>> signal WState, WState_NS : State_Type;
> > >>>>>>> ...;
> > >>>>>>>
> > >>>>>>> a : process(CLK)
> > >>>>>>> begin
> > >>>>>>> if rising_edge(CLK) then
> > >>>>>>> if SINI =3D '1' then =09
> > >>>>>>> WState <=3D S0;
> > >>>>>>>
> > >>>>>>> else
> > >>>>>>> WState <=3D WState_NS;
> > >>>>>>> end if;
> > >>>>>>> end if;
> > >>>>>>> end process;
> > >>>>>>>
> > >>>>>>> b : process(all)
> > >>>>>>> begin
> > >>>>>>> case WState is
> > >>>>>>> when S0 =3D>
> > >>>>>>> if C1 then
> > >>>>>>> WState_NS <=3D S1;
> > >>>>>>>
> > >>>>>>> elsif C2 then
> > >>>>>>> WState_NS <=3D S2;
> > >>>>>>> =09
> > >>>>>>> else
> > >>>>>>> WState_NS <=3D S0;
> > >>>>>>> end if;
> > >>>>>>> ...;
> > >>>>>>> end case;
> > >>>>>>> end process;
> > >>>>>>>
> > >>>>>>> Now a synthesizer must generate a signal S0_C1 as follows
> > >>>>>>>
> > >>>>>>> S0_C1 <=3D not SINI and WState =3D S0 and C1;
> > >>>>>>>
> > >>>>>>> When S0_C1 is asserted, WState will go from S0 to S1.
> > >>>>>>>
> > >>>>>>> I call signal S0_C1 a jumping signal for the state machine.
> > >>>>>>>
> > >>>>>>> I want to know:
> > >>>>>>> 1. Is there a systematic circuit structure or a systematic meth=
od that can generate signal S0_C1 and others. I think it is an oldest circu=
it.
> > >>>>>>>
> > >>>>>>> 2. If there is a systematic circuit structure, what its name is=
?
> > >>>>>>>
> > >>>>>>> 3. Do you know how Xilinx or Altera generates a circuit for a s=
tate machine?
> > >>>>>>
> > >>>>>> First of all, I don't agree with your hypothesis that signals S0=
_C1, et. al. exist at any point in this design. They may, but might not de=
pending on the details of the state encoding and the optimizations performe=
d.
> > >>>>>>
> > >>>>>> I think what you are failing to consider is that the states, S0,=
S1, et. al. are encoded in some manner. The actual logic generated would =
then depend on all the input combinations that assert a given bit in the en=
coded state values. So if the state variable WState_NS is three bits and u=
ses 00, 01 and 10 for the state values, the variable WState_NS(0) would hav=
e its own equation (I'll skip solving that for you) and the variable WState=
_NS(1) would have another equation which is not likely to be the same.
> > >>>>>>
> > >>>>>> There are likely to be shared logic in the individual bits of th=
e state variable, but how likely is it that the software will optimize out =
the exact signals you hypothesize?
> > >>>>>>
> > >>>>>> Does this make sense?
> > >>>>>>
> > >>>>>> Rick C.
> > >>>>>>
> > >>>>>> Tesla referral code + https://ts.la/richard11209
> > >>>>>
> > >>>>> Opps, I should have said if "the state variable WState_NS is two =
bits"
> > >>>>>
> > >>>>> Rick C.
> > >>>>
> > >>>> Rick,
> > >>>> How a state machine is constructed is not important, the important=
thing is: there is A BIT SIGNAL that will make the state machine going fro=
m state S0 to state S1 on the next cycle when it is asserted on the current=
cycle based on the S0_C1 logic which I have given before.
> > >>>>
> > >>>> S0_C1 logic is A BIT SIGNAL.
> > >>>
> > >>> That is where you fail to understand. Your code does not include t=
he signal S0_C1. The structure of the state machine does not dictate such =
a signal. You can conceive of this signal in your mind and perform any des=
ign tasks using this signal, but that does not mean it is in any way real. =
Even in the case of a 1-hot encoded machine this signal will only exist if=
there are no other ways to enter the state S1.
> > >>>
> > >>> So if you only wish to suppose that the signal S0_C1 exists in your=
theoretical analysis, fine. I have found in certain cases decomposition t=
o similar basic signals to be useful in specifying state machines in a simp=
le way. But don't for a minute believe that it exists in any real world im=
plementation or is in any way fundamental to the operation of the state mac=
hine.
> > >>>
> > >>> Of your questions:
> > >>>> I want to know:
> > >>>> 1. Is there a systematic circuit structure or a systematic method =
that can > generate signal S0_C1 and others. I think it is an oldest circui=
t.
> > >>>
> > >>> Yes, it is called a state/next-state table and is very simple.
> > >>>
> > >>>> 2. If there is a systematic circuit structure, what its name is?
> > >>>
> > >>> We just call it "logic".
> > >>>
> > >>>> 3. Do you know how Xilinx or Altera generates a circuit for a stat=
e machine?
> > >>>
> > >>> Yes, they take the logic you define in your HDL and apply the many =
types of decomposition, optimization and synthesis on it that are also used=
on all the other logic code you use in the rest of your design.
> > >>>
> > >>> Rick C.
> > >>>
> > >>> Tesla referral code -- https://ts.la/richard11209
> > >>
> > >> Hi Rick,
> > >> I don't want to start an argument about what I am doing, right or wr=
ong. In a month or so I will publish something that will show your followin=
g 2 claims are wrong:
> > >>
> > >> 1. Even in the case of a 1-hot encoded machine this signal will only=
exist if there are no other ways to enter the state S1.
> > >>
> > >> 2. But don't for a minute believe that it exists in any real world i=
mplementation or is in any way fundamental to the operation of the state ma=
chine.
> > >=20
> > > No need to argue. Just explain. "The best argument is that which se=
ems merely an explanation." - Dale Carnegie
> > >=20
> > > I have studied the 1-hot state machine. The only signal required for=
each "hot" (state element) is it's next value. That value depends on *all=
* the possible transitions into a given state, not just a transition from a=
ny one state into that state which is what your S0_C1 bit signal is. The a=
ctual signal at the input to the state FF is the logical OR of the equivale=
nt signal for transitions from *all* the states that have transitions into =
this state, including a transition from this state itself... unless the clo=
ck enable is also used, sometimes inefficiently. So the input to the FF mi=
ght be an OR of S0_C1, S1_C1N, S2_something...
> > >=20
> > > Of course, you can write your code that way if you wish (write code, =
draw diagrams, etc). My only point is this has nothing to do with the actu=
al resulting signals produced to construct the state machine in an FPGA or =
other logic device. The actual input to the state FF is what we call next_=
state and is not always equivalent to what you seem to be picturing. What =
you seem to be picturing can be used in design, but it may not be a real si=
gnal in the implementation.
> > >=20
> > > Rick C.
> > >=20
> > > Tesla referral code -+ https://ts.la/richard11209
> > >=20
> >=20
> > In Xilinx can't you looks at the RTL logic generated and see what=20
> > signals are being produced?
> >=20
> > Dave
>=20
> Rick,
>=20
> We don't have to argue, follow Dave's advice, take my code, compile it in=
Xilinx, look at the generated logic, you would find my S0_C1 signal is the=
re, whether you have 10 states or 100 states.=20
>=20
> Very simple thing can be solved by Dave's advice and facts, not by argume=
nt.=20
>=20
> I have spent a lot of time reading the generated logic!
Where would I find your signal? This is your design, your claim. Have you=
synthesized the program (it won't compile as it is not complete).=20
else =20
WState_NS <=3D S0;
end if;
...;
end case;
There is a lot assumed when you typed the "..."
The fact remains that in the general case the only signal that is assured t=
o exist in the implementation is the "next state" signal because it is the =
input to the FF. In certain cases the "next state" signal will be the same=
as your S0_C1 signal, but not in general. It doesn't matter what the tria=
l cases you have analyzed show. You can't prove a general rule by examinin=
g a few specific cases.=20
You keep referring to this as "argument". I don't understand. Is all disc=
ussion with you an argument? =20
Rick C.
Tesla referral code ++ https://ts.la/richard11209
Get 6 months of free supercharging
Article: 160904
On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote:
>=20
> We don't have to argue, follow Dave's advice, take my code, compile it in=
Xilinx, look at the generated logic, you would find my S0_C1 signal is the=
re, whether you have 10 states or 100 states.=20
>=20
Take that same code and compile it in Quartus and you will find no such S0_=
C1 signal. Instead what you will see is a flip flop to hold WState.S0 with=
the 'D' input coming from lookup table logic. The output of the lookup is=
the next state of WState.S0. That lookup table takes as input four signal=
s: C1, Sini, WState.S0 and C2. The lookup table implements the following =
logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic imp=
lemented in the entire post-fit design.
In your earlier code posting you stated: Now a synthesizer must generate a=
signal S0_C1 as follows: S0_C1 <=3D not SINI and WState =3D S0 and C1;=20
Using Quartus, there is no individual signal for the state transition to S0=
from input C1 as you have stated seeing when using Xilinx. If Xilinx gene=
rates such a signal as you say, then it is doing so very inefficiently sinc=
e, in order to generate the final next state input to the flip flop, there =
must be additional logic that you did not mention which will create additio=
nal delay and therefore lower performance. I find it hard to believe that =
a big brand like Xilinx would synthesize something as simple as you posted =
so poorly. If it really does do as you say, then I'm even happier to be a =
user of Quartus rather than Xilinx...but again, I still highly doubt that b=
rand X is that bad.
Quartus offers several netlist views: RTL Viewer, State Machine, post-mapp=
ing, and post-fitting. My description above is based on the post-fitting v=
iew, but none of the other views show a discrete signal to handle the trans=
ition of S0 based on input C1.
> Very simple thing can be solved by Dave's advice and facts, not by argume=
nt.=20
>=20
I agree and I've posted my full set of facts. Perhaps you can be as fully =
descriptive using Xilinx tools.
If what you claim to see from Xilinx is true, you seem to have left out som=
e details. For example, while you say you see a signal "S0_C1 <=3D not SIN=
I and WState =3D S0 and C1;" this cannot be the next state logic since it d=
oes not depend on C2 and clearly your state machine does depend on C2. So =
there is some additional logic that you have not mentioned for some reason.=
Maybe you are discussing something from code that you haven't posted who =
knows? =20
Perhaps you or someone else should run the complete design code that I have=
posted below with Xilinx to either confirm or refute your claim. At least=
that way we all know exactly what code is under discussion.
In any case, what you claim regarding S0_C1 right now is only true for your=
unposted single design when run using Xilinx tools and only when run by yo=
u. That's a very narrow claim. It's already been pointed out in this thre=
ad why your claim will not in general be true for:
- Anything other than one-hot encoded state machine
- Anything other than if the state only depends on one input
- Now this post shows that it is not true with what I believe to be your co=
de when run using a different synthesis tool.
> I have spent a lot of time reading the generated logic!
>=20
That may be true, but if you have spent any time it is not evident, at leas=
t not to me.
Kevin
--- Start of code ---
library ieee;
use ieee.std_logic_1164.all;
entity WengState is
port(
Clk: in std_ulogic;
Sini: in std_ulogic;
C1: in std_ulogic;
C2: in std_ulogic;
Gazouta: out std_ulogic
);
end WengState;
architecture RTL of WengState is
type State_Type is (S0, S1, S2);=20
signal WState, WState_NS : State_Type;=20
begin
Gazouta <=3D '1' when (WState =3D S0) else '0';
a : process(CLK)=20
begin=20
if rising_edge(CLK) then=20
if SINI =3D '1' then =20
WState <=3D S0;=20
else=20
WState <=3D WState_NS;=20
end if;=20
end if;=20
end process;=20
b : process(all)=20
begin=20
WState_NS <=3D WState; -- KJ added
case WState is=20
when S0 =3D>=20
if C1 then=20
WState_NS <=3D S1;=20
elsif C2 then=20
WState_NS <=3D S2;=20
=20
else =20
WState_NS <=3D S0;=20
end if;
when others =3D> null;
end case;=20
end process;
end RTL;
--- End of code ---
Article: 160905On Saturday, December 15, 2018 at 8:49:54 AM UTC-8, KJ wrote: > On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wrote= : > >=20 > > We don't have to argue, follow Dave's advice, take my code, compile it = in Xilinx, look at the generated logic, you would find my S0_C1 signal is t= here, whether you have 10 states or 100 states.=20 > >=20 > Take that same code and compile it in Quartus and you will find no such S= 0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 wi= th the 'D' input coming from lookup table logic. The output of the lookup = is the next state of WState.S0. That lookup table takes as input four sign= als: C1, Sini, WState.S0 and C2. The lookup table implements the followin= g logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic i= mplemented in the entire post-fit design. >=20 > In your earlier code posting you stated: Now a synthesizer must generate= a signal S0_C1 as follows: S0_C1 <=3D not SINI and WState =3D S0 and C1;= =20 >=20 > Using Quartus, there is no individual signal for the state transition to = S0 from input C1 as you have stated seeing when using Xilinx. If Xilinx ge= nerates such a signal as you say, then it is doing so very inefficiently si= nce, in order to generate the final next state input to the flip flop, ther= e must be additional logic that you did not mention which will create addit= ional delay and therefore lower performance. I find it hard to believe tha= t a big brand like Xilinx would synthesize something as simple as you poste= d so poorly. If it really does do as you say, then I'm even happier to be = a user of Quartus rather than Xilinx...but again, I still highly doubt that= brand X is that bad. >=20 > Quartus offers several netlist views: RTL Viewer, State Machine, post-ma= pping, and post-fitting. My description above is based on the post-fitting= view, but none of the other views show a discrete signal to handle the tra= nsition of S0 based on input C1. >=20 > > Very simple thing can be solved by Dave's advice and facts, not by argu= ment.=20 > >=20 > I agree and I've posted my full set of facts. Perhaps you can be as full= y descriptive using Xilinx tools. >=20 > If what you claim to see from Xilinx is true, you seem to have left out s= ome details. For example, while you say you see a signal "S0_C1 <=3D not S= INI and WState =3D S0 and C1;" this cannot be the next state logic since it= does not depend on C2 and clearly your state machine does depend on C2. S= o there is some additional logic that you have not mentioned for some reaso= n. Maybe you are discussing something from code that you haven't posted wh= o knows? =20 >=20 > Perhaps you or someone else should run the complete design code that I ha= ve posted below with Xilinx to either confirm or refute your claim. At lea= st that way we all know exactly what code is under discussion. >=20 > In any case, what you claim regarding S0_C1 right now is only true for yo= ur unposted single design when run using Xilinx tools and only when run by = you. That's a very narrow claim. It's already been pointed out in this th= read why your claim will not in general be true for: > - Anything other than one-hot encoded state machine > - Anything other than if the state only depends on one input > - Now this post shows that it is not true with what I believe to be your = code when run using a different synthesis tool. >=20 > > I have spent a lot of time reading the generated logic! > >=20 > That may be true, but if you have spent any time it is not evident, at le= ast not to me. >=20 > Kevin >=20 > --- Start of code --- > library ieee; > use ieee.std_logic_1164.all; >=20 > entity WengState is > port( > Clk: in std_ulogic; > Sini: in std_ulogic; > C1: in std_ulogic; > C2: in std_ulogic; > Gazouta: out std_ulogic > ); > end WengState; >=20 > architecture RTL of WengState is > type State_Type is (S0, S1, S2);=20 >=20 > signal WState, WState_NS : State_Type;=20 > begin > Gazouta <=3D '1' when (WState =3D S0) else '0'; >=20 > a : process(CLK)=20 > begin=20 > if rising_edge(CLK) then=20 > if SINI =3D '1' then =20 > WState <=3D S0;=20 >=20 > else=20 > WState <=3D WState_NS;=20 > end if;=20 > end if;=20 > end process;=20 >=20 > b : process(all)=20 > begin=20 > WState_NS <=3D WState; -- KJ added > case WState is=20 > when S0 =3D>=20 > if C1 then=20 > WState_NS <=3D S1;=20 >=20 > elsif C2 then=20 > WState_NS <=3D S2;=20 > =20 > else =20 > WState_NS <=3D S0;=20 > end if; > when others =3D> null; > end case;=20 > end process; > end RTL; > --- End of code --- Hi Kevin, Thank you for your testing and you really did a very good experiment: "Take that same code and compile it in Quartus and you will find no such S0= _C1 signal. Instead what you will see is a flip flop to hold WState.S0 wit= h the 'D' input coming from lookup table logic. The output of the lookup i= s the next state of WState.S0. That lookup table takes as input four signa= ls: C1, Sini, WState.S0 and C2. The lookup table implements the following= logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic im= plemented in the entire post-fit design." 1. My signal "S0_C1 <=3D not SINI and WState =3D S0 and C1;" should be next= state for state S1, not for S0!, for state S1, not for S0!, for state S1, not for= S0!=20 But you look at state S0! Please look at state S1 2. Your explanation is wrong.=20 How do you explain LUT4 output for state S0: S0 <=3D not(Sini) and (C1 or C2 or WState.S0);??? Based on your explanation, when not(Sini) and (C1 =3D '1' or C2 =3D '1' or = WState =3D S0), state S0 should be asserted on next cycle???=20 Based on the equation state S0 will be in state S0 forever if your explanat= ion is correct!!@??? 3. To make the testing full, you must add something, for example, to output= not Gazouta <=3D '1' when (WState =3D S0) else '0'; but WState.=20 By optimization State S1 is cut off, because it never plays a rule, generat= ing a logic that must be thoroughly analyzed to understand.=20 Kevin, Thank you. Please continue! I like this type of facts, not words in = argument. WengArticle: 160906
On Saturday, December 15, 2018 at 12:56:36 PM UTC-8, Weng Tianxiang wrote: > On Saturday, December 15, 2018 at 8:49:54 AM UTC-8, KJ wrote: > > On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang wro= te: > > >=20 > > > We don't have to argue, follow Dave's advice, take my code, compile i= t in Xilinx, look at the generated logic, you would find my S0_C1 signal is= there, whether you have 10 states or 100 states.=20 > > >=20 > > Take that same code and compile it in Quartus and you will find no such= S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 = with the 'D' input coming from lookup table logic. The output of the looku= p is the next state of WState.S0. That lookup table takes as input four si= gnals: C1, Sini, WState.S0 and C2. The lookup table implements the follow= ing logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic= implemented in the entire post-fit design. > >=20 > > In your earlier code posting you stated: Now a synthesizer must genera= te a signal S0_C1 as follows: S0_C1 <=3D not SINI and WState =3D S0 and C1= ;=20 > >=20 > > Using Quartus, there is no individual signal for the state transition t= o S0 from input C1 as you have stated seeing when using Xilinx. If Xilinx = generates such a signal as you say, then it is doing so very inefficiently = since, in order to generate the final next state input to the flip flop, th= ere must be additional logic that you did not mention which will create add= itional delay and therefore lower performance. I find it hard to believe t= hat a big brand like Xilinx would synthesize something as simple as you pos= ted so poorly. If it really does do as you say, then I'm even happier to b= e a user of Quartus rather than Xilinx...but again, I still highly doubt th= at brand X is that bad. > >=20 > > Quartus offers several netlist views: RTL Viewer, State Machine, post-= mapping, and post-fitting. My description above is based on the post-fitti= ng view, but none of the other views show a discrete signal to handle the t= ransition of S0 based on input C1. > >=20 > > > Very simple thing can be solved by Dave's advice and facts, not by ar= gument.=20 > > >=20 > > I agree and I've posted my full set of facts. Perhaps you can be as fu= lly descriptive using Xilinx tools. > >=20 > > If what you claim to see from Xilinx is true, you seem to have left out= some details. For example, while you say you see a signal "S0_C1 <=3D not= SINI and WState =3D S0 and C1;" this cannot be the next state logic since = it does not depend on C2 and clearly your state machine does depend on C2. = So there is some additional logic that you have not mentioned for some rea= son. Maybe you are discussing something from code that you haven't posted = who knows? =20 > >=20 > > Perhaps you or someone else should run the complete design code that I = have posted below with Xilinx to either confirm or refute your claim. At l= east that way we all know exactly what code is under discussion. > >=20 > > In any case, what you claim regarding S0_C1 right now is only true for = your unposted single design when run using Xilinx tools and only when run b= y you. That's a very narrow claim. It's already been pointed out in this = thread why your claim will not in general be true for: > > - Anything other than one-hot encoded state machine > > - Anything other than if the state only depends on one input > > - Now this post shows that it is not true with what I believe to be you= r code when run using a different synthesis tool. > >=20 > > > I have spent a lot of time reading the generated logic! > > >=20 > > That may be true, but if you have spent any time it is not evident, at = least not to me. > >=20 > > Kevin > >=20 > > --- Start of code --- > > library ieee; > > use ieee.std_logic_1164.all; > >=20 > > entity WengState is > > port( > > Clk: in std_ulogic; > > Sini: in std_ulogic; > > C1: in std_ulogic; > > C2: in std_ulogic; > > Gazouta: out std_ulogic > > ); > > end WengState; > >=20 > > architecture RTL of WengState is > > type State_Type is (S0, S1, S2);=20 > >=20 > > signal WState, WState_NS : State_Type;=20 > > begin > > Gazouta <=3D '1' when (WState =3D S0) else '0'; > >=20 > > a : process(CLK)=20 > > begin=20 > > if rising_edge(CLK) then=20 > > if SINI =3D '1' then = =20 > > WState <=3D S0;=20 > >=20 > > else=20 > > WState <=3D WState_NS;=20 > > end if;=20 > > end if;=20 > > end process;=20 > >=20 > > b : process(all)=20 > > begin=20 > > WState_NS <=3D WState; -- KJ added > > case WState is=20 > > when S0 =3D>=20 > > if C1 then=20 > > WState_NS <=3D S1;=20 > >=20 > > elsif C2 then=20 > > WState_NS <=3D S2;=20 > > =20 > > else =20 > > WState_NS <=3D S0;=20 > > end if; > > when others =3D> null; > > end case;=20 > > end process; > > end RTL; > > --- End of code --- >=20 > Hi Kevin, >=20 > Thank you for your testing and you really did a very good experiment: >=20 > "Take that same code and compile it in Quartus and you will find no such = S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0 w= ith the 'D' input coming from lookup table logic. The output of the lookup= is the next state of WState.S0. That lookup table takes as input four sig= nals: C1, Sini, WState.S0 and C2. The lookup table implements the followi= ng logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logic = implemented in the entire post-fit design." >=20 > 1. My signal "S0_C1 <=3D not SINI and WState =3D S0 and C1;" should be ne= xt state >=20 > for state S1, not for S0!, for state S1, not for S0!, for state S1, not f= or S0!=20 >=20 > But you look at state S0! Please look at state S1 >=20 > 2. Your explanation is wrong.=20 >=20 > How do you explain LUT4 output for state S0: >=20 > S0 <=3D not(Sini) and (C1 or C2 or WState.S0);??? >=20 > Based on your explanation, when not(Sini) and (C1 =3D '1' or C2 =3D '1' o= r WState =3D S0), state S0 should be asserted on next cycle???=20 >=20 > Based on the equation state S0 will be in state S0 forever if your explan= ation is correct!!@??? >=20 > 3. To make the testing full, you must add something, for example, to outp= ut not Gazouta <=3D '1' when (WState =3D S0) else '0'; but WState.=20 >=20 > By optimization State S1 is cut off, because it never plays a rule, gener= ating a logic that must be thoroughly analyzed to understand.=20 >=20 > Kevin, Thank you. Please continue! I like this type of facts, not words i= n argument. >=20 > Weng Sorry, you must add some logic to have state S1 valid, bot being cut off. O= utput the state machine is not enough to keep state S1 not being cut off. WengArticle: 160907
On Saturday, December 15, 2018 at 4:06:40 PM UTC-5, Weng Tianxiang wrote:
> On Saturday, December 15, 2018 at 12:56:36 PM UTC-8, Weng Tianxiang wrote=
:
> > On Saturday, December 15, 2018 at 8:49:54 AM UTC-8, KJ wrote:
> > > On Saturday, December 15, 2018 at 10:09:13 AM UTC-5, Weng Tianxiang w=
rote:
> > > >=20
> > > > We don't have to argue, follow Dave's advice, take my code, compile=
it in Xilinx, look at the generated logic, you would find my S0_C1 signal =
is there, whether you have 10 states or 100 states.=20
> > > >=20
> > > Take that same code and compile it in Quartus and you will find no su=
ch S0_C1 signal. Instead what you will see is a flip flop to hold WState.S=
0 with the 'D' input coming from lookup table logic. The output of the loo=
kup is the next state of WState.S0. That lookup table takes as input four =
signals: C1, Sini, WState.S0 and C2. The lookup table implements the foll=
owing logic: not(Sini) and (C1 or C2 or WState.S0). There is no other log=
ic implemented in the entire post-fit design.
> > >=20
> > > In your earlier code posting you stated: Now a synthesizer must gene=
rate a signal S0_C1 as follows: S0_C1 <=3D not SINI and WState =3D S0 and =
C1;=20
> > >=20
> > > Using Quartus, there is no individual signal for the state transition=
to S0 from input C1 as you have stated seeing when using Xilinx. If Xilin=
x generates such a signal as you say, then it is doing so very inefficientl=
y since, in order to generate the final next state input to the flip flop, =
there must be additional logic that you did not mention which will create a=
dditional delay and therefore lower performance. I find it hard to believe=
that a big brand like Xilinx would synthesize something as simple as you p=
osted so poorly. If it really does do as you say, then I'm even happier to=
be a user of Quartus rather than Xilinx...but again, I still highly doubt =
that brand X is that bad.
> > >=20
> > > Quartus offers several netlist views: RTL Viewer, State Machine, pos=
t-mapping, and post-fitting. My description above is based on the post-fit=
ting view, but none of the other views show a discrete signal to handle the=
transition of S0 based on input C1.
> > >=20
> > > > Very simple thing can be solved by Dave's advice and facts, not by =
argument.=20
> > > >=20
> > > I agree and I've posted my full set of facts. Perhaps you can be as =
fully descriptive using Xilinx tools.
> > >=20
> > > If what you claim to see from Xilinx is true, you seem to have left o=
ut some details. For example, while you say you see a signal "S0_C1 <=3D n=
ot SINI and WState =3D S0 and C1;" this cannot be the next state logic sinc=
e it does not depend on C2 and clearly your state machine does depend on C2=
. So there is some additional logic that you have not mentioned for some r=
eason. Maybe you are discussing something from code that you haven't poste=
d who knows? =20
> > >=20
> > > Perhaps you or someone else should run the complete design code that =
I have posted below with Xilinx to either confirm or refute your claim. At=
least that way we all know exactly what code is under discussion.
> > >=20
> > > In any case, what you claim regarding S0_C1 right now is only true fo=
r your unposted single design when run using Xilinx tools and only when run=
by you. That's a very narrow claim. It's already been pointed out in thi=
s thread why your claim will not in general be true for:
> > > - Anything other than one-hot encoded state machine
> > > - Anything other than if the state only depends on one input
> > > - Now this post shows that it is not true with what I believe to be y=
our code when run using a different synthesis tool.
> > >=20
> > > > I have spent a lot of time reading the generated logic!
> > > >=20
> > > That may be true, but if you have spent any time it is not evident, a=
t least not to me.
> > >=20
> > > Kevin
> > >=20
> > > --- Start of code ---
> > > library ieee;
> > > use ieee.std_logic_1164.all;
> > >=20
> > > entity WengState is
> > > port(
> > > Clk: in std_ulogic;
> > > Sini: in std_ulogic;
> > > C1: in std_ulogic;
> > > C2: in std_ulogic;
> > > Gazouta: out std_ulogic
> > > );
> > > end WengState;
> > >=20
> > > architecture RTL of WengState is
> > > type State_Type is (S0, S1, S2);=20
> > >=20
> > > signal WState, WState_NS : State_Type;=20
> > > begin
> > > Gazouta <=3D '1' when (WState =3D S0) else '0';
> > >=20
> > > a : process(CLK)=20
> > > begin=20
> > > if rising_edge(CLK) then=20
> > > if SINI =3D '1' then =
=20
> > > WState <=3D S0;=20
> > >=20
> > > else=20
> > > WState <=3D WState_NS;=20
> > > end if;=20
> > > end if;=20
> > > end process;=20
> > >=20
> > > b : process(all)=20
> > > begin=20
> > > WState_NS <=3D WState; -- KJ added
> > > case WState is=20
> > > when S0 =3D>=20
> > > if C1 then=20
> > > WState_NS <=3D S1;=20
> > >=20
> > > elsif C2 then=20
> > > WState_NS <=3D S2;=20
> > > =20
> > > else =20
> > > WState_NS <=3D S0;=20
> > > end if;
> > > when others =3D> null;
> > > end case;=20
> > > end process;
> > > end RTL;
> > > --- End of code ---
> >=20
> > Hi Kevin,
> >=20
> > Thank you for your testing and you really did a very good experiment:
> >=20
> > "Take that same code and compile it in Quartus and you will find no suc=
h S0_C1 signal. Instead what you will see is a flip flop to hold WState.S0=
with the 'D' input coming from lookup table logic. The output of the look=
up is the next state of WState.S0. That lookup table takes as input four s=
ignals: C1, Sini, WState.S0 and C2. The lookup table implements the follo=
wing logic: not(Sini) and (C1 or C2 or WState.S0). There is no other logi=
c implemented in the entire post-fit design."
> >=20
> > 1. My signal "S0_C1 <=3D not SINI and WState =3D S0 and C1;" should be =
next state
> >=20
> > for state S1, not for S0!, for state S1, not for S0!, for state S1, not=
for S0!=20
> >=20
> > But you look at state S0! Please look at state S1
> >=20
> > 2. Your explanation is wrong.=20
> >=20
> > How do you explain LUT4 output for state S0:
> >=20
> > S0 <=3D not(Sini) and (C1 or C2 or WState.S0);???
> >=20
> > Based on your explanation, when not(Sini) and (C1 =3D '1' or C2 =3D '1'=
or WState =3D S0), state S0 should be asserted on next cycle???=20
> >=20
> > Based on the equation state S0 will be in state S0 forever if your expl=
anation is correct!!@???
> >=20
> > 3. To make the testing full, you must add something, for example, to ou=
tput not Gazouta <=3D '1' when (WState =3D S0) else '0'; but WState.=20
> >=20
> > By optimization State S1 is cut off, because it never plays a rule, gen=
erating a logic that must be thoroughly analyzed to understand.=20
> >=20
> > Kevin, Thank you. Please continue! I like this type of facts, not words=
in argument.
> >=20
> > Weng
>=20
> Sorry, you must add some logic to have state S1 valid, bot being cut off.=
Output the state machine is not enough to keep state S1 not being cut off.
>=20
> Weng
I have no idea what "cut off" means. =20
The test done is not of value since it does not implement a useful state ma=
chine and not the one you described earlier. =20
b : process(all)
begin
case WState is
when S0 =3D>
if C1 then
WState_NS <=3D S1;
elsif C2 then
WState_NS <=3D S2;
=20
else =20
WState_NS <=3D S0;
end if;
...;
end case;
end process;
This is your code and the important part is at the end of the case code whe=
re you have "...;". This implies there is other code for the remainder of =
the state machine which must be added for a useful analysis.=20
Your comment above, '1. My signal "S0_C1 <=3D not SINI and WState =3D S0 an=
d C1;" should be next state for state S1' shows you intend your S0_C1 signa=
l to be the next state signal of each bit of the state machine. In that ca=
se the equation will depend on *all* transitions to a given state in a 1-ho=
t machine. =20
If you are actually talking about the next_state equations rather than what=
appeared to be an intermediate signal that may or may not exist in any giv=
en design, what are your questions exactly?=20
Rick C.
Tesla referral code --- https://ts.la/richard11209
Get 6 months of free supercharging
Article: 160908On Saturday, December 15, 2018 at 3:56:36 PM UTC-5, Weng Tianxiang wrote: >=20 > 1. My signal "S0_C1 <=3D not SINI and WState =3D S0 and C1;" should be ne= xt state >=20 > for state S1, not for S0!, for state S1, not for S0!, for state S1, not f= or S0!=20 > Here you undercut everything that you have posted in this thread regarding = your state machine. Here is why: - In your original post with your state machine, the source code showed inp= uts C1 and C2 that would cause a transition from state S0. Now you say "My= signal "S0_C1 <=3D not SINI and WState =3D S0 and C1;" should be next stat= e for state S1...". But if that is now the case then you've clearly shown = that the code you used as the basis for your claim that signal S0_C1 MUST b= e generated from something different than you posted. In particular, I wou= ld wager that you added "elsif C2 then WState_NS <=3D S2; " after the fact = and did not re-compile or re-analyze to see that the change completely unde= rcuts what you were about to claim. Shame on you for posting code that is NOT what you used to support your (fa= lse) claim. As the group has already pointed out, your claim would only be= true for a one-hot encoded, single input state machine which is exactly wh= at you used when writing up your claim. Shame on you for not using the code that I posted to re-analyze for yoursel= f even after I challenged you to do so. Had you done that you could have c= ome to the realizations that I have pointed out here on your own and retrac= ted your false claim "there is A BIT SIGNAL that will make the state machin= e going from state S0 to state S1 on the next cycle when it is asserted on = the current cycle based on the S0_C1 logic" when all that actually gets imp= lemented is the next state logic, nothing else. > But you look at state S0! Please look at state S1 >=20 No reason to, your claim was about S0 and C1. Quartus implemented the inverted state S0. It then inverted that to produc= e the output Gazouta. I had missed the little bubble on the I/O buffer whe= n looking at the netlist viewer. No additional logic was generated to impl= ement since the I/O buffers can automatically generate either polarity. > 2. Your explanation is wrong.=20 >=20 HAHAHAHA...I presented Quartus' results for the synthesis of your state mac= hine. Take that up with Altera/Intel, not me. > How do you explain LUT4 output for state S0: >=20 > S0 <=3D not(Sini) and (C1 or C2 or WState.S0);??? >=20 > Based on your explanation, when not(Sini) and (C1 =3D '1' or C2 =3D '1' o= r WState =3D S0), state S0 should be asserted on next cycle???=20 >=20 > Based on the equation state S0 will be in state S0 forever if your explan= ation is correct!!@??? >=20 See above. Quartus implemented the internal state S0 in the inverted sense= . > 3. To make the testing full, you must add something, for example, to outp= ut not Gazouta <=3D '1' when (WState =3D S0) else '0'; but WState.=20 >=20 No, your state machine design is flawed. You posted some code for a state = machine where only one state S0 is needed. Just because you think states S= 1 and S2 may be needed, does not mean they are. Quartus implemented your d= esign with one state, that's on you. > By optimization State S1 is cut off, because it never plays a rule, gener= ating a logic that must be thoroughly analyzed to understand.=20 >=20 Quartus did analyze that and correctly determined there is no value in stat= e S1 or S2 and optimized them out of the fitted design. Again, you provide= d the state machine, not me. > Kevin, Thank you. Please continue! I like this type of facts, not words i= n argument. >=20 No thanks.Article: 160909
On Saturday, December 15, 2018 at 4:06:40 PM UTC-5, Weng Tianxiang wrote: > Sorry, you must add some logic to have state S1 valid, bot being cut off. Output the state machine is not enough to keep state S1 not being cut off. > Neither state S1 or S2 are not needed in order to implement your state machine that is functionally identical to any other implementation. KevinArticle: 160910
On Saturday, December 15, 2018 at 11:28:47 PM UTC-5, gnuarm.del...@gmail.co= m=20 >=20 > I have no idea what "cut off" means. =20 >=20 Weng is upset that his original three state machine can actually be impleme= nted with a single state. States 'S1' and 'S2' in that sense were cut off = because they were useless. >=20 > If you are actually talking about the next_state equations rather than wh= at appeared to be an intermediate signal that may or may not exist in any g= iven design, what are your questions exactly?=20 >=20 I don't think he has any actual questions. Weng tends to present claims th= at tend to be false but insists they are true. That's his delusion to reso= lve. Weng also tends to post code that is not representative of the code that he= bases his claim upon. That was the case here where he based his claim on = code that did not have the "elsif C2" branch in it. Take that branch out a= nd you have a one-hot encoded single input state machine which has already = been pointed out to him to be the special case where his statement is in so= me sense true. However, the 'S0_C1' signal that he crows about is really j= ust the next state...so what? KevinArticle: 160911
On Sunday, December 16, 2018 at 6:16:40 AM UTC-8, KJ wrote: > On Saturday, December 15, 2018 at 11:28:47 PM UTC-5, gnuarm.del...@gmail.= com=20 > >=20 > > I have no idea what "cut off" means. =20 > >=20 > Weng is upset that his original three state machine can actually be imple= mented with a single state. States 'S1' and 'S2' in that sense were cut of= f because they were useless. >=20 > >=20 > > If you are actually talking about the next_state equations rather than = what appeared to be an intermediate signal that may or may not exist in any= given design, what are your questions exactly?=20 > >=20 > I don't think he has any actual questions. Weng tends to present claims = that tend to be false but insists they are true. That's his delusion to re= solve. >=20 > Weng also tends to post code that is not representative of the code that = he bases his claim upon. That was the case here where he based his claim o= n code that did not have the "elsif C2" branch in it. Take that branch out= and you have a one-hot encoded single input state machine which has alread= y been pointed out to him to be the special case where his statement is in = some sense true. However, the 'S0_C1' signal that he crows about is really= just the next state...so what? >=20 > Kevin I will publish my research result in patent application form in a month or = so, systematically describing a new tool every hardware engineer here will = benefit from my invention, providing more than 10 circuits.=20 I don't see any benefits for continuing debates here. WengArticle: 160912
On Tuesday, April 24, 2018 at 6:32:38 AM UTC-4, azie...@gmail.com wrote: > Dear J=C3=BCrgen, >=20 > sorry for reviving this thread after all these years - but your mentioned= eMail address is invalid meanwhile. > So if you are still listening - did you find the searched disassemblers i= n the last 18 years? > I have found some pieces, so maybe they might be of interest for you too. >=20 > Andreas Hello. I am looking for some disassemblers too. 8051 In particular. Can you= help?Article: 160913
On 16/12/18 21:06, frankcovending@gmail.com wrote: > On Tuesday, April 24, 2018 at 6:32:38 AM UTC-4, azie...@gmail.com wrote: >> Dear Jürgen, >> >> sorry for reviving this thread after all these years - but your mentioned eMail address is invalid meanwhile. >> So if you are still listening - did you find the searched disassemblers in the last 18 years? >> I have found some pieces, so maybe they might be of interest for you too. >> >> Andreas > > Hello. I am looking for some disassemblers too. 8051 In particular. Can you help? > It should not be hard to find an 8051 disassembler with a little google searching. If you want to get help from a Usenet group, please remember that these really are communities - Google Groups is an archive, so searching for old posts and replying to them is not going to get you anywhere. Get a real newsreader client (Thunderbird is fine, and works on all platforms), get a real Usenet server (news.eternal-september.org is a good, free choice), and join the groups that interest you. comp.arch.embedded is probably your best bet here.Article: 160914
I've spent hours searching and kept coming up empty. I've found all of the = manuals and all software through google, but that 8051 compiler just isn't = easy. You are probably right that replying to old emails etc is not going t= o get me far, but it is a resource and I'm going to exhaust all of them. I'= ll look into the resources you have provided.Article: 160915
On 17/12/18 13:40, frankcovending@gmail.com wrote: > I've spent hours searching and kept coming up empty. I've found all > of the manuals and all software through google, but that 8051 > compiler just isn't easy. You are probably right that replying to old > emails etc is not going to get me far, but it is a resource and I'm > going to exhaust all of them. I'll look into the resources you have > provided. > A compiler is entirely different from a disassembler. You said "I am looking for some disassemblers too. 8051 in particular". Now you say you want a compiler. Which is it? There are /lots/ of compiler for the 8051. Many commercial ones, and at least one solid open source one. I don't know about disassemblers for the core, having never needed to use one, but google finds plenty within a few seconds. You need to figure out what tool(s) you are actually looking for - or at least figure out what you want to do with them. You need to figure out whether you are dealing with the core in general, or specific devices, whether you want commercial tools or free ones, and so on. And if you want help from people, you will have to say what you have tried so far and why those tools have been inappropriate. Otherwise no one can help. But as I say, please drop the "Google Groups" interface - it is absolutely terrible for posting to Usenet (though it is okay for searching archives). If you can't use a proper Usenet client, then at least learn to use Google Groups properly - it's default options are contrary to standard Usenet usage. (This is not your fault, it is Google's fault - but it is you, the GG poster, who has to make the effort.) Quote posts correctly, with attribution and appropriate snipping, and split your lines correctly. And then, when you have this figured out, post to comp.arch.embedded - it is the best newsgroup for such tools. (comp.arch.fpga is a fine and helpful group too, but c.a.e. will reach more 8051 users.)Article: 160916
On Monday, December 17, 2018 at 9:31:21 AM UTC-5, David Brown wrote: > On 17/12/18 13:40, wrote: > > I've spent hours searching and kept coming up empty. I've found all > > of the manuals and all software through google, but that 8051 > > compiler just isn't easy. You are probably right that replying to old > > emails etc is not going to get me far, but it is a resource and I'm > > going to exhaust all of them. I'll look into the resources you have > > provided. > >=20 >=20 > A compiler is entirely different from a disassembler. You said "I am > looking for some disassemblers too. 8051 in particular". Now you say > you want a compiler. Which is it? >=20 > There are /lots/ of compiler for the 8051. Many commercial ones, and at > least one solid open source one. I don't know about disassemblers for > the core, having never needed to use one, but google finds plenty within > a few seconds. >=20 > You need to figure out what tool(s) you are actually looking for - or at > least figure out what you want to do with them. You need to figure out > whether you are dealing with the core in general, or specific devices, > whether you want commercial tools or free ones, and so on. >=20 > And if you want help from people, you will have to say what you have > tried so far and why those tools have been inappropriate. Otherwise no > one can help. >=20 > But as I say, please drop the "Google Groups" interface - it is > absolutely terrible for posting to Usenet (though it is okay for > searching archives). If you can't use a proper Usenet client, then at > least learn to use Google Groups properly - it's default options are > contrary to standard Usenet usage. (This is not your fault, it is > Google's fault - but it is you, the GG poster, who has to make the > effort.) Quote posts correctly, with attribution and appropriate > snipping, and split your lines correctly. >=20 > And then, when you have this figured out, post to comp.arch.embedded - > it is the best newsgroup for such tools. (comp.arch.fpga is a fine and > helpful group too, but c.a.e. will reach more 8051 users.) My mistake on my prior reply. I did not intend to say compiler. I meant to = say disassembler. My mistake, human... I get what you're saying about everything being on google, but it's a tool = not the means to an end. I'm trying to get my hands on the 8051 disassemble= r for the pm3585 logic analyzer. I'm trying to learn how to debug the 8051 = using the pm3585.=20 Now I have been out of the electronics/computer field for quite some time a= nd I had shifted my focus to mechanical and civil engineering. I am just ge= tting back into hobby electronics. I am working on some mechatronics projec= t at home in my free time and I'm prototyping with off the shelf controller= s, but my goal is to develop my own controller and I am tempted to use the = 8051 or a Z80. I'm leaning towards the 8051 because the DS89C4XX has everyt= hing I need and I have the components from a sample pack I got almost a dec= ade ago. I have a Z80 as well. =20Article: 160917
On 17/12/2018 16:02, frankcovending@gmail.com wrote: > On Monday, December 17, 2018 at 9:31:21 AM UTC-5, David Brown wrote: >> On 17/12/18 13:40, wrote: >>> I've spent hours searching and kept coming up empty. I've found all >>> of the manuals and all software through google, but that 8051 >>> compiler just isn't easy. You are probably right that replying to old >>> emails etc is not going to get me far, but it is a resource and I'm >>> going to exhaust all of them. I'll look into the resources you have >>> provided. >>> >> >> A compiler is entirely different from a disassembler. You said "I am >> looking for some disassemblers too. 8051 in particular". Now you say >> you want a compiler. Which is it? >> >> There are /lots/ of compiler for the 8051. Many commercial ones, and at >> least one solid open source one. I don't know about disassemblers for >> the core, having never needed to use one, but google finds plenty within >> a few seconds. >> >> You need to figure out what tool(s) you are actually looking for - or at >> least figure out what you want to do with them. You need to figure out >> whether you are dealing with the core in general, or specific devices, >> whether you want commercial tools or free ones, and so on. >> >> And if you want help from people, you will have to say what you have >> tried so far and why those tools have been inappropriate. Otherwise no >> one can help. >> >> But as I say, please drop the "Google Groups" interface - it is >> absolutely terrible for posting to Usenet (though it is okay for >> searching archives). If you can't use a proper Usenet client, then at >> least learn to use Google Groups properly - it's default options are >> contrary to standard Usenet usage. (This is not your fault, it is >> Google's fault - but it is you, the GG poster, who has to make the >> effort.) Quote posts correctly, with attribution and appropriate >> snipping, and split your lines correctly. >> >> And then, when you have this figured out, post to comp.arch.embedded - >> it is the best newsgroup for such tools. (comp.arch.fpga is a fine and >> helpful group too, but c.a.e. will reach more 8051 users.) > > My mistake on my prior reply. I did not intend to say compiler. I > meant to say disassembler. My mistake, human... OK. > > I get what you're saying about everything being on google, but it's a > tool not the means to an end. I'm trying to get my hands on the 8051 > disassembler for the pm3585 logic analyzer. I'm trying to learn how to > debug the 8051 using the pm3585. > Is this for a history project, or a museum? Nobody has used a logic analyser for microcontroller debugging for at least 20 years, probably more. > > Now I have been out of the electronics/computer field for quite some > time and I had shifted my focus to mechanical and civil engineering. I > am just getting back into hobby electronics. I am working on some > mechatronics project at home in my free time and I'm prototyping with > off the shelf controllers, but my goal is to develop my own controller > and I am tempted to use the 8051 or a Z80. I'm leaning towards the 8051 > because the DS89C4XX has everything I need and I have the components > from a sample pack I got almost a decade ago. I have a Z80 as well. > The 8051 is 40 years old, and the architecture was outdated before the first chip was made. There have been some reasonable microcontrollers made around it, despite it's horrendous core. And the Z80 was a fine device 30 years ago. What you are suggesting is like trying to build a car using a steam engine. I can appreciate that there is some nostalgia in this for you, but I really would recommend using newer hardware and software. Probably the best choice for getting started would be an Arduino kit - there are lots of base boards to choose from, lots of add-ons, lots of tutorials and examples, and a reasonable IDE (which is free).Article: 160918
On Monday, December 17, wrote: > > On Monday, December 17, 2018 at 9:31:21 AM UTC-5, David Brown wrote: > >> On 17/12/18 13:40, wrote: > >>> I've spent hours searching and kept coming up empty. I've found all > >>> of the manuals and all software through google, but that 8051 > >>> compiler just isn't easy. You are probably right that replying to old > >>> emails etc is not going to get me far, but it is a resource and I'm > >>> going to exhaust all of them. I'll look into the resources you have > >>> provided. > >>> > >> > >> A compiler is entirely different from a disassembler. You said "I am > >> looking for some disassemblers too. 8051 in particular". Now you say > >> you want a compiler. Which is it? > >> > >> There are /lots/ of compiler for the 8051. Many commercial ones, and at > >> least one solid open source one. I don't know about disassemblers for > >> the core, having never needed to use one, but google finds plenty within > >> a few seconds. > >> > >> You need to figure out what tool(s) you are actually looking for - or at > >> least figure out what you want to do with them. You need to figure out > >> whether you are dealing with the core in general, or specific devices, > >> whether you want commercial tools or free ones, and so on. > >> > >> And if you want help from people, you will have to say what you have > >> tried so far and why those tools have been inappropriate. Otherwise no > >> one can help. > >> > >> But as I say, please drop the "Google Groups" interface - it is > >> absolutely terrible for posting to Usenet (though it is okay for > >> searching archives). If you can't use a proper Usenet client, then at > >> least learn to use Google Groups properly - it's default options are > >> contrary to standard Usenet usage. (This is not your fault, it is > >> Google's fault - but it is you, the GG poster, who has to make the > >> effort.) Quote posts correctly, with attribution and appropriate > >> snipping, and split your lines correctly. > >> > >> And then, when you have this figured out, post to comp.arch.embedded - > >> it is the best newsgroup for such tools. (comp.arch.fpga is a fine and > >> helpful group too, but c.a.e. will reach more 8051 users.) > > > > My mistake on my prior reply. I did not intend to say compiler. I > > meant to say disassembler. My mistake, human... > > OK. > > > > > I get what you're saying about everything being on google, but it's a > > tool not the means to an end. I'm trying to get my hands on the 8051 > > disassembler for the pm3585 logic analyzer. I'm trying to learn how to > > debug the 8051 using the pm3585. > > > > Is this for a history project, or a museum? Nobody has used a logic > analyser for microcontroller debugging for at least 20 years, probably more. > > > > > Now I have been out of the electronics/computer field for quite some > > time and I had shifted my focus to mechanical and civil engineering. I > > am just getting back into hobby electronics. I am working on some > > mechatronics project at home in my free time and I'm prototyping with > > off the shelf controllers, but my goal is to develop my own controller > > and I am tempted to use the 8051 or a Z80. I'm leaning towards the 8051 > > because the DS89C4XX has everything I need and I have the components > > from a sample pack I got almost a decade ago. I have a Z80 as well. > > > > The 8051 is 40 years old, and the architecture was outdated before the > first chip was made. There have been some reasonable microcontrollers > made around it, despite it's horrendous core. And the Z80 was a fine > device 30 years ago. > > What you are suggesting is like trying to build a car using a steam engine. > > I can appreciate that there is some nostalgia in this for you, but I > really would recommend using newer hardware and software. Probably the > best choice for getting started would be an Arduino kit - there are lots > of base boards to choose from, lots of add-ons, lots of tutorials and > examples, and a reasonable IDE (which is free). I see and I do agree. I just happen to have a load of these 8051 chips and other outdated pieces and I would rather put them to use than chuck them. I was eyeballing the arduino uno though. I guess I'll just try to develop and if things get rough I'll just give it the old college try w or w/o disassembler. I'f I am careful I might be able, haha, to get away with a bug free piece. Thanks for your interest in my problemArticle: 160919
Am Freitag, 7. Dezember 2018 00:16:38 UTC+1 schrieb Kevin Neilson: > On Thursday, December 6, 2018 at 4:05:29 PM UTC-7, Kevin Neilson wrote: > > On Thursday, December 6, 2018 at 4:02:25 PM UTC-7, Kevin Neilson wrote: > > > I've searched for this but to no avail. I'd like a function f(D,W), = where D=3Ddepth and W=3Dwidth, which provides an estimate of the gate count= of a lookup ROM implemented in ASIC gates. > > >=20 > > > Yes, I know it's dependent on the contents. However, if half the bit= s are ones and the contents are randomly distributed, a formula should be p= retty accurate. Not so easy as you think as the content of the ROM has a very strong influe= nce on the result. Assume a simple ROM content with 50% '0' and 50% '1' Bit 3210 ------------- Adr 000: 0000 =20 Adr 001: 1010 =20 Adr 010: 1100 =20 Adr 011: 1110 =20 Adr 100: 1000 =20 Adr 101: 1010 =20 Adr 110: 1100 =20 Adr 111: 1111 =20 =20 This is RomData(0)=3D Adr(0) AND Adr(1) AND Adr(3) RomData(1)=3D Adr(0) RomData(2)=3D Adr(1) RomData(3)=3D Adr(0) OR Adr(1) OR ADR(3) Now you can very easy scramble the content slightly to be no longer able to= build that simple terms. In worst case you end up with a full DNF for each Bit.=20 Each bit of datawidth would in worst case need a term in DNF with a number = of clauses equal to the number of bit =3D'1' and each clause in DNF having = addresswidth number of variables. For a ROM of 10 bit address with equal distributed '1' and '0' this means 5= 12 clauses of 10 variables in DNF is your upper limit per databit. This would be 512 AND gates with 10 inputs and one OR gate with 512 inputs. As no ASCI technology has an OR gate with 512 inputs or an AND gate with 10= inputs, you need to build this using a gate tree =3D> 5 AND3 per clause an= d ~300 OR3 for the or-tree. This means something like 2.9k Gates with three= inputs per bit instead of your assumed Depth/2-1 gates. =20 As you see it might still be possible to have a regularity in the formula t= hat can reduce this to a simple gate per data bit, but in general random RO= M data tend to have only low possibilities of term reduction and for larger= depth of RAM you cannot see on first glance if any reduction is possible a= t all. bye ThomasArticle: 160920
On 17/12/2018 22:39, David Brown wrote: > Is this for a history project, or a museum? Nobody has used a logic > analyser for microcontroller debugging for at least 20 years, probably > more. As a matter of fact I did 3 years ago. It was a Xilinx picoBlaze and that was the only way I had to trace the execution. It was fun. NicolasArticle: 160921
On 18/12/18 21:50, Nicolas Matringe wrote: > On 17/12/2018 22:39, David Brown wrote: > >> Is this for a history project, or a museum? Nobody has used a logic >> analyser for microcontroller debugging for at least 20 years, probably >> more. > > As a matter of fact I did 3 years ago. It was a Xilinx picoBlaze and > that was the only way I had to trace the execution. It was fun. > > Nicolas I admit that "nobody" was an exaggeration. But it is has certainly become very rare as a debugging technique. Note that we are not talking about using a logic analyser for monitoring the outputs from a microcontroller in order to find out if the program is running correctly - lots of people do that. (Though they usually use little USB-connected pods and PC software, rather than huge and expensive dedicated machines.) This was about using a logic analyser to trace the entire instruction stream - with a disassembler interpreting the stream. It is something that could be done in the days of external ROM for your code and simple, non-pipelined deterministic cpu cores.Article: 160922
I'll state my reason for using a dedicated machine. I do not like software = based diagnostics. The problem comes when the developer stops updating the = software. Then you need to buy new hardware and software. With a dedicated = stand alone machines even after 20 years it works. To me it is a way to avo= id getting cornered into license fees, obsolescence. I have Micro-Cap from = back in the Dos days on a 5-1/4 floppy... I don't have a machine to run it = but I have it.=20 That's why I like my hardware. I actually own it to rather than paying for = the right to use (like most proprietary software).Article: 160923
Hello, Am Donnerstag, 13. Dezember 2018 14:45:47 UTC+1 schrieb Weng Tianxiang: > What is the name of the circuit structure that generates a state machine'= s jumping signals? transition (function) logic Maybe it would be helpful for you to read=20 en.wikipedia.org/wiki/Finite-state_machine A FSM can be as simple as a counter from 0 to 1 (modulo 2) or can be a comp= lete fpga design. It is often seen that someone claims this term only for "= explicite expressed" FSMs using eg an enumerated type in VHDL, but in gener= al all needed for a FSM is to have at 2+ states, any kind of input (clock a= lone is sufficient) to activate switching between those states (based on a = defined transition function) plus any output that is depending on state alo= ne or state and input.=20 Especially the kind of coding structure used (1 process, 2 process, 3 proce= ss) as well as the question if the states are enumerated type or std_logic_= vectors are not relevant. You can draw a statemachine with bubble diagram which contains a bubble for= each state and an arrow for each transition. In this abstraction you have = a "signal" for each state transition. > type State_Type is ( S0, S1, ...);=20 > signal WState, WState_NS : State_Type;=20 > > a : process(CLK)=20 > begin=20 > if rising_edge(CLK) then=20 > if SINI =3D '1' then =20 > WState <=3D S0;=20 > > else=20 > WState <=3D WState_NS;=20 > end if;=20 > end if;=20 > end process;=20 > > b : process(all)=20 > begin=20 > case WState is=20 > when S0 =3D>=20 > if C1 then=20 > WState_NS <=3D S1;=20 > > elsif C2 then=20 > WState_NS <=3D S2;=20 > =20 > else =20 > WState_NS <=3D S0;=20 > end if;=20 > ...;=20 > end case;=20 > end process;=20 > > Now a synthesizer must generate a signal S0_C1 as follows=20 > > S0_C1 <=3D not SINI and WState =3D S0 and C1;=20 Why? The code is equivalent to=20 process (Clk) if SINI =3D'1' then WState <=3D S0; else=20 case WState isArticle: 160924
Am Donnerstag, 13. Dezember 2018 14:45:47 UTC+1 schrieb Weng Tianxiang:
> What is the correct name?
transition (function) logic=20
Maybe it would be helpful for you to read=20
en.wikipedia.org/wiki/Finite-state_machine=20
A FSM can be as simple as a counter from 0 to 1 (modulo 2) or can be a comp=
lete fpga design. It is often seen that someone claims this term only for "=
explicite expressed" FSMs using eg an enumerated type in VHDL, but in gener=
al all needed for a FSM is to have at 2+ states, any kind of input (clock a=
lone is sufficient) to activate switching between those states (based on a =
defined transition function) plus any output that is depending on state alo=
ne or state and input.=20
Especially the kind of coding structure used (1 process, 2 process, 3 proce=
ss) as well as the question if the states are enumerated type or std_logic_=
vectors are not relevant.=20
You can draw a statemachine with bubble diagram which contains a bubble for=
each state and an arrow for each transition. In this abstraction you have =
a "signal" for each state transition.=20
> type State_Type is ( S0, S1, ...);=20
> signal WState, WState_NS : State_Type;=20
>=20
> a : process(CLK)=20
> begin=20
> if rising_edge(CLK) then=20
> if SINI =3D '1' then =20
> WState <=3D S0;=20
>=20
> else=20
> WState <=3D WState_NS;=20
> end if;=20
> end if;=20
> end process;=20
>=20
> b : process(all)=20
> begin=20
> case WState is=20
> when S0 =3D>=20
> if C1 then=20
> WState_NS <=3D S1;=20
>=20
> elsif C2 then=20
> WState_NS <=3D S2;=20
> =20
> else =20
> WState_NS <=3D S0;=20
> end if;=20
> ...;=20
> end case;=20
> end process;=20
>=20
> Now a synthesizer must generate a signal S0_C1 as follows=20
>=20
> S0_C1 <=3D not SINI and WState =3D S0 and C1;=20
Why?=20
The code is equivalent to=20
process (Clk)=20
if SINI =3D'1' then=20
WState <=3D S0;=20
else=20
case WState is=20
when S0 =3D>
if C1 then
WState_NS <=3D S1; =20
elsif C2 then=20
WState_NS <=3D S2; =20
else =20
WState_NS <=3D S0;=20
end case;
end if;
This equivalent code will not necesseary generate a signal "xx <=3D not SIN=
I and WState =3D S0 and C1" after synthesis. It will have this signal in an=
synthesis intermediate state but after logic optimisation this signal can =
be removed in favor of simplified functionality depending on the complete F=
SM transition logic.
=20
bye Thomas
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