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Den 2019-01-31 kl. 22:57, skrev lasselangwadtchristensen@gmail.com: > torsdag den 31. januar 2019 kl. 17.47.23 UTC+1 skrev gnuarm.del...@gmail.com: >> On Thursday, January 31, 2019 at 6:25:32 AM UTC-5, Theo wrote: >>> A.P.Richelieu <aprichelieu@gmail.com> wrote: >>>> You are trying to convince me to look at Zynq and SoC. >>>> That is what I explicitly said I was not going to do. >>> >>> No, I'm pointing out that your argument on costs doesn't necessarily stack >>> up. >>> >>> The reason why the options are so constrained, and why this doesn't exist as >>> a popular product, is that not many Linux-capable CPUs have an external bus >>> interface or a high bandwidth GPIO interface. Basically you're stuck with >>> PCIe (which ups the FPGA cost a lot) or things with SPI to try and squeeze >>> enough bandwidth out. >>> >>> Things like the OMAP PRUs might do it, but I'm not sure what useful >>> bandwidth you can get at the end of the day (since there's no help with the >>> wire protocol, you have to do it all in software). >>> >>> That leaves the options as roughly: >>> >>> - Zynq/Intel SoC parts (on-chip FPGA) >>> - some Microsemi parts with a hard Cortex M (not Linux capable) >>> - OMAP PRU >>> - I think I saw a single iMX part with an external bus interface, but it was >>> slow >>> - an FPGA with a soft core running Linux (Microblaze, NIOS-II, RISC-V of >>> some kind). These have a myriad of sharp edges, as the >>> core/kernel/drivers/compiler/distro is often not very polished >>> - PCIe >>> - a few parts (eg Cavium ThunderX) which expose the cache coherency protocol >>> externally. You'd be very much on your own here. >>> >>> Another horrible idea: write a NAND flash interface for the FPGA and use >>> that to emulate an external bus interface. You'd have to disentangle >>> whatever cleverness the CPU's NAND controller tries to do, but in principle >>> the bandwidth is there. >>> >>> Basically you've boxed yourself into a corner here, so all these options are >>> not very appealing. >> >> I was thinking about his bandwidth requirement. While you say there aren't many ARMs running Linux with external memory interfaces (which makes me wonder how they build all those Beagle Bones, etc.) > > they "all" have external memory but it is dedicated for DDR RAM, some of them, like the beagle bone also have a general purpose memory interface controller for things like sync and async RAM and FLASH, that's the one you'd want to use for an FPGA, and some do: https://elinux.org/BeagleBoard/BeagleWire > > > That is more like it, unfortunately, it is not a single module, and the Lattice FPGA is not on the accepted list. Might look at it for some homebrew stuff though. AP.Article: 161101
Den 2019-01-31 kl. 16:00, skrev kkoorndyk:
> On Wednesday, January 30, 2019 at 1:21:30 PM UTC-5, A.P.Richelieu wrote:
>> Den 2019-01-30 kl. 18:44, skrev lasselangwadtchristensen@gmail.com:
>>> onsdag den 30. januar 2019 kl. 18.13.34 UTC+1 skrev A.P.Richelieu:
>>>> Is there any ARM + FPGA CPU Module running linux using any of:
>>>>
>>>> * NXP i.MX6/7/...
>>>> * Texas Instrument Sitara AM335x or better
>>>> * Microchip SAMA5
>>>> * Renesas RZ/xxx
>>>>
>>>> It needs to be connected to a low price FPGA, Intel or Xilinx.
>>>>
>>>> * Zynq or Intel SoC solutions need not apply.
>>>>
>>>> Other vendors will be difficult to accept.
>>>>
>>>> =====================
>>>>
>>>> The CPU Module needs at least
>>>> * 128 MB RAM
>>>> * 128 MB Flash.
>>>> Connector will have
>>>> * 100 Mbps Ethernet
>>>> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA)
>>>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps)
>>>> * SD-Card
>>>> * A few custom protocol LVDS channels
>>>> =====================
>>>> The processor has to be connected to an FPGA on a suitable
>>>> interface providing 5-10 MB/second transfer rate.
>>>> The FPGA needs to have 80-100 free I/O, not including the
>>>> interface to the CPU to implement SPIs, UARTs and other custom signals
>>>> =====================
>>>> The CPU should be able to load the FPGA after reset.
>>>> Preferably right after loading the U-Boot (during the BOOTDELAY timer).
>>>> =====================
>>>> Preferably, the processor should be able to access the internals
>>>> of the FPGA like it was on the memory bus.
>>>>
>>>> Putting the FPGA on a 16 bit memory interface will work
>>>>
>>>> Some chip support a transparent mode where you do a memory read/write
>>>> which gets translated to a Quad SPI access, or a NAND flash controller
>>>> access.
>>>>
>>>> I.E:
>>>> You can write to a register over SPI by:
>>>> FPGA_REGISTER = value;
>>>> instead of
>>>>
>>>> spi_packet = {
>>>> .cmd = SPI_WRITE,
>>>> .addr = FPGA_REGISTER,
>>>> .size = sizeof(value),
>>>> .data = &value
>>>> }
>>>> spi_transfer(&spi_packet);
>>>>
>>>>
>>>> We plan to use Yocto for developing Linux, so any Yocto solution
>>>> would be appreciated.
>>>>
>>>> Looking forward to ideas.
>>>>
>>>> AP
>>>
>>> why not Zynq? it has everything you ask for and the same ARM-9 as the NXP
>>>
>>
>> Because it is way too expensive.
>>
>> You can get a better ARM chip for $6-7 in 1k qty.
>> A Cyclone 10 FPGA is $8-9.
>> Can You get a Zynq for $14-16 in 1k volume?
>> Digikey shows one off pricing for the cheapest Zynq to be $46.
>> If they can give 40% discount at 1k, it is still $30 = 2x price.
>>
>>
>> Another thing is that the onboard peripherals generally suck.
>> At least when I looked at them the last time.
>> I do not care to waste my time on why.
>>
>> This means that we have to spend time doing peripherals in the FPGA.
>> They need to be supported by Linux drivers.
>> We do not want to add that development effort.
>>
>> AP
>
> If you're purchasing in the 1000+ qty annually, you should NOT be using Digikey for pricing. That should be a negotiation with your Avent rep. In higher volumes, I've seen pretty significant prices negotiated for our customers.
>
> You mentioned in a more recent response that you use Zynqs in other products, so you might consider trying to design in common parts to increase your total corporate purchase qty of the same part to help negotiate better prices.
>
We know what the Zynq is all about and it has been rejected for this
project.
You don't have access to all our decision criteria,
but you are free to beat a dead horse if you want to.
AP
Article: 161102Not much of a thread really. Some guy demanding that others here do his work for him while being a bit surly about questions he considers irrelevant. I guess beggars can't be choosers. This conversation is still better than religious tirades. c.a.f is pretty light on topics these days. Rick C. -+ Get 6 months of free supercharging -+ Tesla referral code - https://ts.la/richard11209Article: 161103
I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simulators for both languages. I believe there are significant shortcomings in any case. I'm pretty sure there is an open source tool for backend place and route and bit stream generation of the Lattice iCE40 devices, well, some of them anyway. I don't recall what they use for synthesis front end. Are there other FOSS synthesis tools for either Verilog or VHDL? What are the limitations? Rick C. - Tesla referral code - https://ts.la/richard11209Article: 161104
Den 2019-02-02 kl. 04:27, skrev gnuarm.deletethisbit@gmail.com: > Not much of a thread really. Some guy demanding that others here do his work for him while being a bit surly about questions he considers irrelevant. > > I guess beggars can't be choosers. This conversation is still better than religious tirades. c.a.f is pretty light on topics these days. > > I specify already in my first entry what I am looking for. I also specify what I am not looking for. And no, I am not asking anyone to do work for me. I am asking people to share knowledge which they might have. That is what Newsgroups are for. You expect me to be pleased when anyone comes with a suggestion which directly violates the small list of requirements, and starts nagging, when I explain that things like the Zynq has been rejected. There are other reasons than I mentioned why the Zynq is rejected, but those reasons are not for public knowledge. AP > Rick C. > > -+ Get 6 months of free supercharging > -+ Tesla referral code - https://ts.la/richard11209 >Article: 161105
On Friday, February 1, 2019 at 11:54:58 PM UTC-5, A.P.Richelieu wrote: > Den 2019-02-02 kl. 04:27, skrev gnuarm.deletethisbit@gmail.com: > > Not much of a thread really. Some guy demanding that others here do hi= s work for him while being a bit surly about questions he considers irrelev= ant. > >=20 > > I guess beggars can't be choosers. This conversation is still better t= han religious tirades. c.a.f is pretty light on topics these days. > >=20 > >=20 > I specify already in my first entry what I am looking for. > I also specify what I am not looking for. >=20 > And no, I am not asking anyone to do work for me. > I am asking people to share knowledge which they might have. > That is what Newsgroups are for. >=20 > You expect me to be pleased when anyone comes with a suggestion > which directly violates the small list of requirements, > and starts nagging, when I explain that things like the Zynq > has been rejected. No one expects you to like anything. You just come across as rude. I'm no= t sure what you expected of this thread. If your tone had been a bit more = pleasant and willing to discuss things rather than sounding very irritated,= the thread would have been more interesting to read and participate in.=20 When someone offers a suggestion you don't like, it is perfectly acceptable= to not respond at all rather than berate them. Like this one. Rather tha= n come back with more rudeness, you could have just ignored the post. I su= ppose I am be a bit clueless, thinking that my post will have any impact. = People on the Internet are what they are. Silly to expect them to be any d= ifferent on such a limited medium.=20 BTW, you might try asking on comp.arch.embedded. Since the board you are l= ooking for is as much CPU as FPGA their might be more knowledge of the avai= lable modules in that group.=20 Rick C. +- Tesla referral code - https://ts.la/richard11209Article: 161106
Hello Rick On 02/02/2019 04:30, gnuarm.deletethisbit@gmail.com wrote: > I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simulators for both languages. I believe there are significant shortcomings in any case. > > I'm pretty sure there is an open source tool for backend place and route and bit stream generation of the Lattice iCE40 devices, well, some of them anyway. I don't recall what they use for synthesis front end. > > Are there other FOSS synthesis tools for either Verilog or VHDL? What are the limitations? There's this ASIC design tools suite from Pierre et Marie Curie University in Paris : https://www-soc.lip6.fr/equipe-cian/logiciels/alliance/ but it's more ASIC-oriented. NicolasArticle: 161107
Den 2019-02-02 kl. 06:07, skrev gnuarm.deletethisbit@gmail.com: > On Friday, February 1, 2019 at 11:54:58 PM UTC-5, A.P.Richelieu wrote: >> Den 2019-02-02 kl. 04:27, skrev gnuarm.deletethisbit@gmail.com: >>> Not much of a thread really. Some guy demanding that others here do his work for him while being a bit surly about questions he considers irrelevant. >>> >>> I guess beggars can't be choosers. This conversation is still better than religious tirades. c.a.f is pretty light on topics these days. >>> >>> >> I specify already in my first entry what I am looking for. >> I also specify what I am not looking for. >> >> And no, I am not asking anyone to do work for me. >> I am asking people to share knowledge which they might have. >> That is what Newsgroups are for. >> >> You expect me to be pleased when anyone comes with a suggestion >> which directly violates the small list of requirements, >> and starts nagging, when I explain that things like the Zynq >> has been rejected. > > No one expects you to like anything. You just come across as rude. I'm not sure what you expected of this thread. If your tone had been a bit more pleasant and willing to discuss things rather than sounding very irritated, the thread would have been more interesting to read and participate in. > > When someone offers a suggestion you don't like, it is perfectly acceptable to not respond at all rather than berate them. Like this one. Rather than come back with more rudeness, you could have just ignored the post. I suppose I am be a bit clueless, thinking that my post will have any impact. People on the Internet are what they are. Silly to expect them to be any different on such a limited medium. > > BTW, you might try asking on comp.arch.embedded. Since the board you are looking for is as much CPU as FPGA their might be more knowledge of the available modules in that group. > I personally consider it rude to suggest the Zynq, when I explicitly stated that this is not what I am looking for. There are people that tried to give genuine answers, and they are worth thanks, and respect. People that keep on derailing the question less so. AP > > Rick C. > > +- Tesla referral code - https://ts.la/richard11209 >Article: 161108
Am 02.02.19 um 04:30 schrieb gnuarm.deletethisbit@gmail.com: > I know there are some open source simulation tools for Verilog and/or VHDL... I can't recall which or if there are simulators for both languages. I believe there are significant shortcomings in any case. > > I'm pretty sure there is an open source tool for backend place and route and bit stream generation of the Lattice iCE40 devices, well, some of them anyway. I don't recall what they use for synthesis front end. > > Are there other FOSS synthesis tools for either Verilog or VHDL? What are the limitations? I guess the most well-known free simulators are GHDL and Icarus Verilog. Icarus Verilog used to have some synthesis support, but it was dropped. yosys is a well-known current synthesis tool (targeting Xilinx 7-Series and Lattice iCE40 and ASIC). I once used a flow based on Berkely vl2mv, vis, abc, Icarus Verilog to get to a simulated ASIC from Verilog. I guess there is a lot more out there. PhilippArticle: 161109
W dniu sobota, 2 lutego 2019 04:30:52 UTC+1 u=C5=BCytkownik gnuarm.del...@g= mail.com napisa=C5=82: > I know there are some open source simulation tools for Verilog and/or VHD= L... I can't recall which or if there are simulators for both languages. I= believe there are significant shortcomings in any case. =20 >=20 > I'm pretty sure there is an open source tool for backend place and route = and bit stream generation of the Lattice iCE40 devices, well, some of them = anyway. I don't recall what they use for synthesis front end. =20 >=20 > Are there other FOSS synthesis tools for either Verilog or VHDL? What ar= e the limitations?=20 >=20 >=20 > Rick C. >=20 > - Tesla referral code - https://ts.la/richard11209 I think that currently the most successful project is Yosys. It supports La= ttice and Xilinx 7 series FPGAs. https://github.com/YosysHQ/yosys There's also very nice frontend for Yosys - SymbiYosys, which can be used f= or formal verification of RTL code. It supports only Verilog in free versio= n, but also VHDL in paid version. https://github.com/YosysHQ/SymbiYosys There's also very preliminary VHDL frontend for Yosys based on GHDL: https://github.com/tgingold/ghdlsynth-beta AdrianArticle: 161110
Hello folks, Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? I don't want to connect any Hard or Soft core processor. also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. So how can it be done? It is not necessary to use spartan 6 board only.If it possible to workout with any another boards I would really like to know. ThanksArticle: 161111
On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil wrote: > Hello folks,=20 >=20 > Let's say I have Spartan 6 board only and i wanted to implement Ethernet = communication.So how can it be done? >=20 > I don't want to connect any Hard or Soft core processor. > also I have looked into WIZnet W5300 Ethernet controller interfacing to s= partan 6, but I don't want to connect any such controller just spartan 6. > So how can it be done? >=20 > It is not necessary to use spartan 6 board only.If it possible to workout= with any another boards I would really like to know. Thanks You can construct an Ethernet interface easily enough. I know cores have b= een written for that. What is hard is implementing the IP stack. Even on = a processor this is a lot of work. Because there are a lot of steps involv= ed and each step is not time critical, it makes much more sense to implemen= t the logic sequentially rather than in FPGA fabric. Even if implemented i= n the fabric, it will consist of many state machines with lots of timers an= d counters. =20 So it is doable, but since there is no reason to do it, no one has... yet. = You might want to dig into an implementation rather than the specs. My un= derstanding is there are a lot of details that aren't so clear in the spec.= =20 Rick C. - Tesla referral code - https://ts.la/richard11209Article: 161112
On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: > On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil wrote: >> Hello folks, >> >> Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? >> >> I don't want to connect any Hard or Soft core processor. >> also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. >> So how can it be done? >> >> It is not necessary to use spartan 6 board only.If it possible to workout with any another boards I would really like to know. Thanks > > > You can construct an Ethernet interface easily enough. I know cores have been written for that. What is hard is implementing the IP stack. Even on a processor this is a lot of work. Because there are a lot of steps involved and each step is not time critical, it makes much more sense to implement the logic sequentially rather than in FPGA fabric. Even if implemented in the fabric, it will consist of many state machines with lots of timers and counters. > > So it is doable, but since there is no reason to do it, no one has... yet. sure they have, I know of 2 companies just in the UK who have done this, 4links (since 2003) are Argon. Hans www.ht-lab.com You might want to dig into an implementation rather than the specs. My understanding is there are a lot of details that aren't so clear in the spec. > > > Rick C. > > - Tesla referral code - https://ts.la/richard11209 >Article: 161113
On 04/02/2019 07:37, gnuarm.deletethisbit@gmail.com wrote: > On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil > wrote: >> Hello folks, >> >> Let's say I have Spartan 6 board only and i wanted to implement >> Ethernet communication.So how can it be done? >> >> I don't want to connect any Hard or Soft core processor. also I >> have looked into WIZnet W5300 Ethernet controller interfacing to >> spartan 6, but I don't want to connect any such controller just >> spartan 6. So how can it be done? >> >> It is not necessary to use spartan 6 board only.If it possible to >> workout with any another boards I would really like to know. >> Thanks > > > You can construct an Ethernet interface easily enough. I know cores > have been written for that. What is hard is implementing the IP > stack. Even on a processor this is a lot of work. Because there are > a lot of steps involved and each step is not time critical, it makes > much more sense to implement the logic sequentially rather than in > FPGA fabric. Even if implemented in the fabric, it will consist of > many state machines with lots of timers and counters. > While most Ethernet systems use IP networking, it is not necessary. There are older non-IP Ethernet protocols like NetBIOS (not that I recommend it in any way), and modern ones like ATA-over-Ethernet (which is a little like iSCSI, but significantly more efficient as it does not use IP). There are also related technologies like EtherCAT that are best handled in hardware, rather than a software stack. Of course, I have no idea if the OP is thinking of anything like these things. If he is planning on IP, especially a general network with DHCP, ARP, TCP/IP and all the rest, then it would be madness to use FPGA hardware instead of software for the stack. A greatly simplified system, with static IP and ARP tables, only UDP, and other limitations - that could be done in hardware. > So it is doable, but since there is no reason to do it, no one has... > yet. You might want to dig into an implementation rather than the > specs. My understanding is there are a lot of details that aren't so > clear in the spec. > > > Rick C. > > - Tesla referral code - https://ts.la/richard11209 >Article: 161114
On Monday, February 4, 2019 at 11:59:45 AM UTC+5:30, Swapnil Patil wrote: > Hello folks, > > Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? > > I don't want to connect any Hard or Soft core processor. > also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. > So how can it be done? > > It is not necessary to use spartan 6 board only.If it possible to workout with any another boards I would really like to know. Thanks Thanks for replies. I understand it's not easy to implement still i want to give a try. If you have any links or document of work done related to this please share. Rick C. could you tell more how one should start to implement this with cores? I also wanted to know more about these written cores. Hans is it possible we can get information about work that companies made you know about? Thanks.Article: 161115
On 04/02/2019 09:20, Swapnil Patil wrote: > On Monday, February 4, 2019 at 11:59:45 AM UTC+5:30, Swapnil Patil wrote: >> Hello folks, >> >> Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? >> >> I don't want to connect any Hard or Soft core processor. >> also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. >> So how can it be done? >> >> It is not necessary to use spartan 6 board only.If it possible to workout with any another boards I would really like to know. Thanks > > > Thanks for replies. I understand it's not easy to implement still i want to give a try. If you have any links or document of work done related to this please share. > Rick C. could you tell more how one should start to implement this with cores? I also wanted to know more about these written cores. > Hans is it possible we can get information about work that companies made you know about? Hi Swapnil, I don't think you will get any info out of these companies as it's their IP. Try google, there might be some technical papers on the subject. However, as suggested by others you are better of using a softcore. Check out opencores.org. Good luck, Hans www.ht-lab.com > Thanks. >Article: 161116
On Monday, February 4, 2019 at 3:40:42 AM UTC-5, HT-Lab wrote: > On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: > > On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil wrote: > >> Hello folks, > >> > >> Let's say I have Spartan 6 board only and i wanted to implement Ethern= et communication.So how can it be done? > >> > >> I don't want to connect any Hard or Soft core processor. > >> also I have looked into WIZnet W5300 Ethernet controller interfacing t= o spartan 6, but I don't want to connect any such controller just spartan 6= . > >> So how can it be done? > >> > >> It is not necessary to use spartan 6 board only.If it possible to work= out with any another boards I would really like to know. Thanks > >=20 > >=20 > > You can construct an Ethernet interface easily enough. I know cores ha= ve been written for that. What is hard is implementing the IP stack. Even= on a processor this is a lot of work. Because there are a lot of steps in= volved and each step is not time critical, it makes much more sense to impl= ement the logic sequentially rather than in FPGA fabric. Even if implement= ed in the fabric, it will consist of many state machines with lots of timer= s and counters. > >=20 > > So it is doable, but since there is no reason to do it, no one has... y= et. =20 >=20 > sure they have, I know of 2 companies just in the UK who have done this,= =20 > 4links (since 2003) are Argon. I found 4links. Not sure if Argon is supposed to be another company or not= . =20 I guess I'm not sure what you mean when you say, "2 companies"... "have don= e this". What exactly do you mean by "this"?=20 Rick C. + Tesla referral code - https://ts.la/richard11209Article: 161117
On 04/02/2019 14:35, gnuarm.deletethisbit@gmail.com wrote: > On Monday, February 4, 2019 at 3:40:42 AM UTC-5, HT-Lab wrote: >> On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: >>> On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil wrote: >>>> Hello folks, >>>> >>>> Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? >>>> >>>> I don't want to connect any Hard or Soft core processor. >>>> also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. >>>> So how can it be done? >>>> >>>> It is not necessary to use spartan 6 board only.If it possible to workout with any another boards I would really like to know. Thanks >>> >>> >>> You can construct an Ethernet interface easily enough. I know cores have been written for that. What is hard is implementing the IP stack. Even on a processor this is a lot of work. Because there are a lot of steps involved and each step is not time critical, it makes much more sense to implement the logic sequentially rather than in FPGA fabric. Even if implemented in the fabric, it will consist of many state machines with lots of timers and counters. >>> >>> So it is doable, but since there is no reason to do it, no one has... yet. >> >> sure they have, I know of 2 companies just in the UK who have done this, >> 4links (since 2003) are Argon. > > I found 4links. Not sure if Argon is supposed to be another company or not. > > I guess I'm not sure what you mean when you say, "2 companies"... "have done this". What exactly do you mean by "this"? I meant to write 4links and Argon. These companies have implemented a TCP/IP stack in hardware. Hans www.ht-lab.com > > > Rick C. > > + Tesla referral code - https://ts.la/richard11209 >Article: 161118
On Monday, February 4, 2019 at 10:02:34 AM UTC-5, HT-Lab wrote: > On 04/02/2019 14:35, gnuarm.deletethisbit@gmail.com wrote: > > On Monday, February 4, 2019 at 3:40:42 AM UTC-5, HT-Lab wrote: > >> On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: > >>> On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil wrote: > >>>> Hello folks, > >>>> > >>>> Let's say I have Spartan 6 board only and i wanted to implement Ethe= rnet communication.So how can it be done? > >>>> > >>>> I don't want to connect any Hard or Soft core processor. > >>>> also I have looked into WIZnet W5300 Ethernet controller interfacing= to spartan 6, but I don't want to connect any such controller just spartan= 6. > >>>> So how can it be done? > >>>> > >>>> It is not necessary to use spartan 6 board only.If it possible to wo= rkout with any another boards I would really like to know. Thanks > >>> > >>> > >>> You can construct an Ethernet interface easily enough. I know cores = have been written for that. What is hard is implementing the IP stack. Ev= en on a processor this is a lot of work. Because there are a lot of steps = involved and each step is not time critical, it makes much more sense to im= plement the logic sequentially rather than in FPGA fabric. Even if impleme= nted in the fabric, it will consist of many state machines with lots of tim= ers and counters. > >>> > >>> So it is doable, but since there is no reason to do it, no one has...= yet. > >> > >> sure they have, I know of 2 companies just in the UK who have done thi= s, > >> 4links (since 2003) are Argon. > >=20 > > I found 4links. Not sure if Argon is supposed to be another company or= not. > >=20 > > I guess I'm not sure what you mean when you say, "2 companies"... "have= done this". What exactly do you mean by "this"? >=20 > I meant to write 4links and Argon. These companies have implemented a=20 > TCP/IP stack in hardware. I didn't find a company Argon, but maybe now that I know they are in the UK= they might be easier to find. Tough name to search for. =20 How do you know they've implemented a TCP/IP stack in hardware? Have you u= sed it? I didn't see anything on the 4links web site. They seem to be big= on tools for working with SpaceWire. =20 Rick C. -- Tesla referral code - https://ts.la/richard11209Article: 161119
On 04/02/2019 15:28, gnuarm.deletethisbit@gmail.com wrote: > On Monday, February 4, 2019 at 10:02:34 AM UTC-5, HT-Lab wrote: >> On 04/02/2019 14:35, gnuarm.deletethisbit@gmail.com wrote: >>> On Monday, February 4, 2019 at 3:40:42 AM UTC-5, HT-Lab wrote: >>>> On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: >>>>> On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil wrote: >>>>>> Hello folks, >>>>>> >>>>>> Let's say I have Spartan 6 board only and i wanted to implement Ethernet communication.So how can it be done? >>>>>> >>>>>> I don't want to connect any Hard or Soft core processor. >>>>>> also I have looked into WIZnet W5300 Ethernet controller interfacing to spartan 6, but I don't want to connect any such controller just spartan 6. >>>>>> So how can it be done? >>>>>> >>>>>> It is not necessary to use spartan 6 board only.If it possible to workout with any another boards I would really like to know. Thanks >>>>> >>>>> >>>>> You can construct an Ethernet interface easily enough. I know cores have been written for that. What is hard is implementing the IP stack. Even on a processor this is a lot of work. Because there are a lot of steps involved and each step is not time critical, it makes much more sense to implement the logic sequentially rather than in FPGA fabric. Even if implemented in the fabric, it will consist of many state machines with lots of timers and counters. >>>>> >>>>> So it is doable, but since there is no reason to do it, no one has... yet. >>>> >>>> sure they have, I know of 2 companies just in the UK who have done this, >>>> 4links (since 2003) are Argon. >>> >>> I found 4links. Not sure if Argon is supposed to be another company or not. >>> >>> I guess I'm not sure what you mean when you say, "2 companies"... "have done this". What exactly do you mean by "this"? >> >> I meant to write 4links and Argon. These companies have implemented a >> TCP/IP stack in hardware. > > I didn't find a company Argon, but maybe now that I know they are in the UK they might be easier to find. Tough name to search for. > > How do you know they've implemented a TCP/IP stack in hardware? Have you used it? I didn't see anything on the 4links web site. They seem to be big on tools for working with SpaceWire. https://www.electronicsweekly.com/news/archived/resources-archived/uk-company-creates-hardware-tcpip-stack-that-runs-in-2003-04/ Hans. www.ht-lab.com > > > Rick C. > > -- Tesla referral code - https://ts.la/richard11209 >Article: 161120
On Monday, February 4, 2019 at 10:55:55 AM UTC-5, HT-Lab wrote: > On 04/02/2019 15:28, gnuarm.deletethisbit@gmail.com wrote: > > On Monday, February 4, 2019 at 10:02:34 AM UTC-5, HT-Lab wrote: > >> On 04/02/2019 14:35, gnuarm.deletethisbit@gmail.com wrote: > >>> On Monday, February 4, 2019 at 3:40:42 AM UTC-5, HT-Lab wrote: > >>>> On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: > >>>>> On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil wrot= e: > >>>>>> Hello folks, > >>>>>> > >>>>>> Let's say I have Spartan 6 board only and i wanted to implement Et= hernet communication.So how can it be done? > >>>>>> > >>>>>> I don't want to connect any Hard or Soft core processor. > >>>>>> also I have looked into WIZnet W5300 Ethernet controller interfaci= ng to spartan 6, but I don't want to connect any such controller just spart= an 6. > >>>>>> So how can it be done? > >>>>>> > >>>>>> It is not necessary to use spartan 6 board only.If it possible to = workout with any another boards I would really like to know. Thanks > >>>>> > >>>>> > >>>>> You can construct an Ethernet interface easily enough. I know core= s have been written for that. What is hard is implementing the IP stack. = Even on a processor this is a lot of work. Because there are a lot of step= s involved and each step is not time critical, it makes much more sense to = implement the logic sequentially rather than in FPGA fabric. Even if imple= mented in the fabric, it will consist of many state machines with lots of t= imers and counters. > >>>>> > >>>>> So it is doable, but since there is no reason to do it, no one has.= .. yet. > >>>> > >>>> sure they have, I know of 2 companies just in the UK who have done t= his, > >>>> 4links (since 2003) are Argon. > >>> > >>> I found 4links. Not sure if Argon is supposed to be another company = or not. > >>> > >>> I guess I'm not sure what you mean when you say, "2 companies"... "ha= ve done this". What exactly do you mean by "this"? > >> > >> I meant to write 4links and Argon. These companies have implemented a > >> TCP/IP stack in hardware. > >=20 > > I didn't find a company Argon, but maybe now that I know they are in th= e UK they might be easier to find. Tough name to search for. > >=20 > > How do you know they've implemented a TCP/IP stack in hardware? Have y= ou used it? I didn't see anything on the 4links web site. They seem to be= big on tools for working with SpaceWire. >=20 > https://www.electronicsweekly.com/news/archived/resources-archived/uk-com= pany-creates-hardware-tcpip-stack-that-runs-in-2003-04/ I'm surprised, but not amazed. They said it took up about 2500 FFs and 500= 0 4LUTs which is also not surprising. =20 I guess the question is "why?" They say it can be easily verified and "sho= uld be more secure than software". Maybe I'm confused. I thought VHDL *wa= s* software?=20 I noticed they instantiated the design for a Virtex II fpga. That is a *ve= ry* old chip. I wonder if their design has actually sold? I suppose it's = not such a far fetched thing once I see the numbers for size. I expect a l= ogic based stack can be faster than software if you are willing to provide = the gates. =20 I wonder if they have ways of reusing the same hardware for multiple tasks = while tasks are waiting for timeouts or I/O? While you can get good throug= hput with hardware, it can be more difficult to handle a lot of different c= onnections.=20 Rick C. -+ Tesla referral code - https://ts.la/richard11209Article: 161121
On Monday, February 4, 2019 at 12:48:09 PM UTC-5, gnuarm.del...@gmail.com wrote: > On Monday, February 4, 2019 at 10:55:55 AM UTC-5, HT-Lab wrote: > > https://www.electronicsweekly.com/news/archived/resources-archived/uk-company-creates-hardware-tcpip-stack-that-runs-in-2003-04/ > > I'm surprised, but not amazed. They said it took up about 2500 FFs and 5000 4LUTs which is also not surprising. > > I guess the question is "why?" They say it can be easily verified and "should be more secure than software". Maybe I'm confused. I thought VHDL *was* software? I'm guessing it was implemented in software. A tiny, probably custom, CPU core used to execute the program that handles the translation for them. > I wonder if they have ways of reusing the same hardware for multiple tasks while tasks are waiting for timeouts or I/O? While you can get good throughput with hardware, it can be more difficult to handle a lot of different connections. I would be both surprised and amazed to learn it wasn't done in software, albeit in hardware. -- Rick C. HodginArticle: 161122
On 04/02/19 17:48, gnuarm.deletethisbit@gmail.com wrote: > On Monday, February 4, 2019 at 10:55:55 AM UTC-5, HT-Lab wrote: >> On 04/02/2019 15:28, gnuarm.deletethisbit@gmail.com wrote: >>> On Monday, February 4, 2019 at 10:02:34 AM UTC-5, HT-Lab wrote: >>>> On 04/02/2019 14:35, gnuarm.deletethisbit@gmail.com wrote: >>>>> On Monday, February 4, 2019 at 3:40:42 AM UTC-5, HT-Lab wrote: >>>>>> On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: >>>>>>> On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil >>>>>>> wrote: >>>>>>>> Hello folks, >>>>>>>> >>>>>>>> Let's say I have Spartan 6 board only and i wanted to implement >>>>>>>> Ethernet communication.So how can it be done? >>>>>>>> >>>>>>>> I don't want to connect any Hard or Soft core processor. also I >>>>>>>> have looked into WIZnet W5300 Ethernet controller interfacing >>>>>>>> to spartan 6, but I don't want to connect any such controller >>>>>>>> just spartan 6. So how can it be done? >>>>>>>> >>>>>>>> It is not necessary to use spartan 6 board only.If it possible >>>>>>>> to workout with any another boards I would really like to know. >>>>>>>> Thanks >>>>>>> >>>>>>> >>>>>>> You can construct an Ethernet interface easily enough. I know >>>>>>> cores have been written for that. What is hard is implementing >>>>>>> the IP stack. Even on a processor this is a lot of work. >>>>>>> Because there are a lot of steps involved and each step is not >>>>>>> time critical, it makes much more sense to implement the logic >>>>>>> sequentially rather than in FPGA fabric. Even if implemented in >>>>>>> the fabric, it will consist of many state machines with lots of >>>>>>> timers and counters. >>>>>>> >>>>>>> So it is doable, but since there is no reason to do it, no one >>>>>>> has... yet. >>>>>> >>>>>> sure they have, I know of 2 companies just in the UK who have done >>>>>> this, 4links (since 2003) are Argon. >>>>> >>>>> I found 4links. Not sure if Argon is supposed to be another company >>>>> or not. >>>>> >>>>> I guess I'm not sure what you mean when you say, "2 companies"... >>>>> "have done this". What exactly do you mean by "this"? >>>> >>>> I meant to write 4links and Argon. These companies have implemented a >>>> TCP/IP stack in hardware. >>> >>> I didn't find a company Argon, but maybe now that I know they are in the >>> UK they might be easier to find. Tough name to search for. >>> >>> How do you know they've implemented a TCP/IP stack in hardware? Have you >>> used it? I didn't see anything on the 4links web site. They seem to be >>> big on tools for working with SpaceWire. >> >> https://www.electronicsweekly.com/news/archived/resources-archived/uk-company-creates-hardware-tcpip-stack-that-runs-in-2003-04/ > >> > I'm surprised, but not amazed. They said it took up about 2500 FFs and 5000 > 4LUTs which is also not surprising. > > I guess the question is "why?" A reasonable question. The high frequency trading mob will pay ridiculous sums to shave off a millisecond here and a millisecond there - e.g. laying their own dedicate transatlantic fibres, or buying up the microwave links between Chichago and New York because the speed of light is higher in air than fibre. They also cast business /trading rules/ in FPGA hardware. > They say it can be easily verified and "should be more secure than software". > Maybe I'm confused. I thought VHDL *was* software? Not everybody appreciates that boundary is very grey, and changing all the time :)Article: 161123
On Monday, February 4, 2019 at 12:51:16 PM UTC-5, Rick C. Hodgin wrote: > On Monday, February 4, 2019 at 12:48:09 PM UTC-5, gnuarm.del...@gmail.com wrote: > > On Monday, February 4, 2019 at 10:55:55 AM UTC-5, HT-Lab wrote: > > > https://www.electronicsweekly.com/news/archived/resources-archived/uk-company-creates-hardware-tcpip-stack-that-runs-in-2003-04/ > > > > I'm surprised, but not amazed. They said it took up about 2500 FFs and 5000 4LUTs which is also not surprising. > > > > I guess the question is "why?" They say it can be easily verified and "should be more secure than software". Maybe I'm confused. I thought VHDL *was* software? > > I'm guessing it was implemented in software. A tiny, probably > custom, CPU core used to execute the program that handles the > translation for them. > > > I wonder if they have ways of reusing the same hardware for multiple tasks while tasks are waiting for timeouts or I/O? While you can get good throughput with hardware, it can be more difficult to handle a lot of different connections. > > I would be both surprised and amazed to learn it wasn't done > in software, albeit in hardware. Seek and ye shall find. You obviously haven't been reading the links. The info was there, you just had to read it. I guess you are going to say this was another hostile post aimed at you. It is aimed at you, but it isn't hostile. I'm just stating what are pretty clear facts. Rick C. +- Tesla referral code - https://ts.la/richard11209Article: 161124
On Monday, February 4, 2019 at 1:09:15 PM UTC-5, Tom Gardner wrote: > On 04/02/19 17:48, gnuarm.deletethisbit@gmail.com wrote: > > On Monday, February 4, 2019 at 10:55:55 AM UTC-5, HT-Lab wrote: > >> On 04/02/2019 15:28, gnuarm.deletethisbit@gmail.com wrote: > >>> On Monday, February 4, 2019 at 10:02:34 AM UTC-5, HT-Lab wrote: > >>>> On 04/02/2019 14:35, gnuarm.deletethisbit@gmail.com wrote: > >>>>> On Monday, February 4, 2019 at 3:40:42 AM UTC-5, HT-Lab wrote: > >>>>>> On 04/02/2019 06:37, gnuarm.deletethisbit@gmail.com wrote: > >>>>>>> On Monday, February 4, 2019 at 1:29:45 AM UTC-5, Swapnil Patil > >>>>>>> wrote: > >>>>>>>> Hello folks, > >>>>>>>>=20 > >>>>>>>> Let's say I have Spartan 6 board only and i wanted to implement > >>>>>>>> Ethernet communication.So how can it be done? > >>>>>>>>=20 > >>>>>>>> I don't want to connect any Hard or Soft core processor. also I > >>>>>>>> have looked into WIZnet W5300 Ethernet controller interfacing > >>>>>>>> to spartan 6, but I don't want to connect any such controller > >>>>>>>> just spartan 6. So how can it be done? > >>>>>>>>=20 > >>>>>>>> It is not necessary to use spartan 6 board only.If it possible > >>>>>>>> to workout with any another boards I would really like to know. > >>>>>>>> Thanks > >>>>>>>=20 > >>>>>>>=20 > >>>>>>> You can construct an Ethernet interface easily enough. I know > >>>>>>> cores have been written for that. What is hard is implementing > >>>>>>> the IP stack. Even on a processor this is a lot of work. > >>>>>>> Because there are a lot of steps involved and each step is not > >>>>>>> time critical, it makes much more sense to implement the logic > >>>>>>> sequentially rather than in FPGA fabric. Even if implemented in > >>>>>>> the fabric, it will consist of many state machines with lots of > >>>>>>> timers and counters. > >>>>>>>=20 > >>>>>>> So it is doable, but since there is no reason to do it, no one > >>>>>>> has... yet. > >>>>>>=20 > >>>>>> sure they have, I know of 2 companies just in the UK who have done > >>>>>> this, 4links (since 2003) are Argon. > >>>>>=20 > >>>>> I found 4links. Not sure if Argon is supposed to be another compan= y > >>>>> or not. > >>>>>=20 > >>>>> I guess I'm not sure what you mean when you say, "2 companies"... > >>>>> "have done this". What exactly do you mean by "this"? > >>>>=20 > >>>> I meant to write 4links and Argon. These companies have implemented = a=20 > >>>> TCP/IP stack in hardware. > >>>=20 > >>> I didn't find a company Argon, but maybe now that I know they are in = the > >>> UK they might be easier to find. Tough name to search for. > >>>=20 > >>> How do you know they've implemented a TCP/IP stack in hardware? Have= you > >>> used it? I didn't see anything on the 4links web site. They seem to= be > >>> big on tools for working with SpaceWire. > >>=20 > >> https://www.electronicsweekly.com/news/archived/resources-archived/uk-= company-creates-hardware-tcpip-stack-that-runs-in-2003-04/ > > > >>=20 > > I'm surprised, but not amazed. They said it took up about 2500 FFs and= 5000 > > 4LUTs which is also not surprising. > >=20 > > I guess the question is "why?" >=20 > A reasonable question. The high frequency trading mob will > pay ridiculous sums to shave off a millisecond here and a > millisecond there - e.g. laying their own dedicate > transatlantic fibres, or buying up the microwave links > between Chichago and New York because the speed of light > is higher in air than fibre. They also cast business > /trading rules/ in FPGA hardware. Yeah, I know those guys would pay immense sums for shorter latency. But th= at's not the design above I don't think. Who knows though. =20 I wonder if they include the delay in the data path in their calculations. = That is, do they predict where the price was before their results are comp= lete and the fastest trader wins? Or do they try to anticipate where the m= arket will be after all the delays have been accounted for and all the *exp= ected* transactions take place while the processing has been going on? =20 So do they just try to be faster than the rest of the electronic traders, o= r do they try to be faster than the market itself?=20 > > They say it can be easily verified and "should be more secure than soft= ware". > > Maybe I'm confused. I thought VHDL *was* software? >=20 > Not everybody appreciates that boundary is very grey, > and changing all the time :) The real difference is what is done in parallel in "hardware" and what appe= ars to be in parallel in "software". As long as you meet your time deadlin= e it doesn't really matter. In some cases there is no deadline, faster is = better. Not many though.=20 Rick C. ++ Tesla referral code - https://ts.la/richard11209
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